re PR target/70014 ([ARM] Predicate does not match constraint (*subsi3_carryin_const))

2016-03-03  Michael Collison  <michael.collison@linaro.org>

	PR target/70014
	* config/arm/arm.md (*subsi3_carryin_const): Change predicate
	for operand 1 to s_register_operand. Change predicate for operand
	2 to arm_not_immediate_operand.

From-SVN: r233927

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4800e1d1ebbb913e47803b86a5ee500f2516dafb..f149ebac2f0e290020bf7ca00fa483ff6c8cccbc 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2016-03-03  Michael Collison  <michael.collison@linaro.org>
+
+       PR target/70014
+       * config/arm/arm.md (*subsi3_carryin_const): Change predicate
+       for operand 1 to s_register_operand. Change predicate for operand
+       2 to arm_not_immediate_operand.
+
 2016-03-02  H.J. Lu  <hongjiu.lu@intel.com>
 
        * doc/tm.texi: Regenerated.

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index e67239deb6de88710fd6589311ef407dc6836a83..47171b99682207226aa4f9a76d4dfb54d6c2814b 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -883,8 +883,8 @@
 
 (define_insn "*subsi3_carryin_const"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
-        (minus:SI (plus:SI (match_operand:SI 1 "reg_or_int_operand" "r")
-                           (match_operand:SI 2 "arm_not_operand" "K"))
+        (minus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r")
+                           (match_operand:SI 2 "arm_not_immediate_operand" "K"))
                   (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
   "TARGET_32BIT"
   "sbc\\t%0, %1, #%B2"