arch-power: Add fixed-point logical count zeros instructions

This adds the following logical instructions:
  * Count Trailing Zeros Word (cnttzw[.])
  * Count Leading Zeros Doubleword (cntlzd[.])
  * Count Trailing Zeros Doubleword (cnttzd[.])

Change-Id: I4bcf090178d9241f230509ba55e8e58f5e7794ac
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc
index f87afa2821af34f65c0723dd3d5ffc02ed986a6e..6f190d331d8f1a0b91dc69e8b9ca3921fb79e111 100644 (file)
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -293,7 +293,10 @@ IntLogicOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     } else if (!myMnemonic.compare("extsb") ||
                !myMnemonic.compare("extsh") ||
                !myMnemonic.compare("extsw") ||
-               !myMnemonic.compare("cntlzw")) {
+               !myMnemonic.compare("cntlzw") ||
+               !myMnemonic.compare("cntlzd") ||
+               !myMnemonic.compare("cnttzw") ||
+               !myMnemonic.compare("cnttzd")) {
         printSecondSrc = false;
     }
 

diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh
index 6658760f5e673737054c75dbff6dd44f3ea18802..afbdc4341f507fb315a75397a784296c270589b8 100644 (file)
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -494,6 +494,8 @@ class IntLogicOp : public IntOp
     {
     }
 
+    /* Compute the number of consecutive zero bits starting from the
+       leftmost bit and moving right in a 32-bit integer */
     inline int
     findLeadingZeros(uint32_t rs) const
     {
@@ -509,6 +511,57 @@ class IntLogicOp : public IntOp
         }
     }
 
+    /* Compute the number of consecutive zero bits starting from the
+       leftmost bit and moving right in a 64-bit integer */
+    inline int
+    findLeadingZeros(uint64_t rs) const
+    {
+        if (rs) {
+    #if defined(__GNUC__) || (defined(__clang__) && \
+                              __has_builtin(__builtin_clzll))
+            return __builtin_clzll(rs);
+    #else
+            return 63 - findMsbSet(rs);
+    #endif
+        } else {
+            return 64;
+        }
+    }
+
+    /* Compute the number of consecutive zero bits starting from the
+       rightmost bit and moving left in a 32-bit integer */
+    inline int
+    findTrailingZeros(uint32_t rs) const
+    {
+        if (rs) {
+    #if defined(__GNUC__) || (defined(__clang__) && \
+                              __has_builtin(__builtin_ctz))
+            return __builtin_ctz(rs);
+    #else
+            return findLsbSet(rs);
+    #endif
+        } else {
+            return 32;
+        }
+    }
+
+    /* Compute the number of consecutive zero bits starting from the
+       rightmost bit and moving left in a 64-bit integer */
+    inline int
+    findTrailingZeros(uint64_t rs) const
+    {
+        if (rs) {
+    #if defined(__GNUC__) || (defined(__clang__) && \
+                              __has_builtin(__builtin_ctzll))
+            return __builtin_ctzll(rs);
+    #else
+            return findLsbSet(rs);
+    #endif
+        } else {
+            return 64;
+        }
+    }
+
     std::string generateDisassembly(
             Addr pc, const SymbolTable *symtab) const override;
 };

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 6390017af3bde4f33821d926b95faca859715cfa..01ca336b813c279d344ff6ea3280f371fa4ea669 100644 (file)
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -515,6 +515,9 @@ decode PO default Unknown::unknown() {
             922: extsh({{ Ra = Rs_sh; }}, true);
             986: extsw({{ Ra = Rs_sw; }}, true);
             26: cntlzw({{ Ra = findLeadingZeros(Rs_uw); }}, true);
+            58: cntlzd({{ Ra = findLeadingZeros(Rs); }}, true);
+            538: cnttzw({{ Ra = findTrailingZeros(Rs_uw); }}, true);
+            570: cnttzd({{ Ra = findTrailingZeros(Rs); }}, true);
 
             508: cmpb({{
                 uint64_t mask = 0xff;