remove MiSoC dependency

diff --git a/README b/README
index 09e94e9759eaa1610e4308572d0089253b752921..ee3f027bb215cba540db7715319c31afcca32035 100644 (file)
--- a/README
+++ b/README
@@ -64,40 +64,33 @@ devel [AT] lists.m-labs.hk.
   python3 setup.py install
   cd ..
 
-3. Obtain MiSoC and install it:
-  git clone https://github.com/m-labs/misoc --recursive
-  cd misoc
-  python3 setup.py install
-  cd ..
-
-Note: in case you have issues with Migen/MiSoC, please retry
-with our forks at:
+Note: in case you have issues with Migen, please retry
+with our fork at:
   https://github.com/enjoy-digital/misoc
-  https://github.com/enjoy-digital/migen
 until new features are merged.
 
-4. Obtain LiteScope and install it:
+3. Obtain LiteScope and install it:
   git clone https://github.com/enjoy-digital/litescope
   cd litescope
   python3 setup.py install
   cd ..
 
-5. Obtain LiteEth
+4. Obtain LiteEth
   git clone https://github.com/enjoy-digital/liteeth
 
-6. Build and load UDP loopback design (only for KC705 for now):
+5. Build and load UDP loopback design (only for KC705 for now):
   python3 make.py -t udp all
 
-7. Test design (only for KC705 for now):
+6. Test design (only for KC705 for now):
   try to ping 192.168.1.40
   go to ./test directory:
   change com port in config.py to your com port
   run make test_udp
 
-8. Build and load Etherbone design (only for KC705 for now):
+7. Build and load Etherbone design (only for KC705 for now):
   python3 make.py -t etherbone all
 
-9. Test design (only for KC705 for now):
+8. Test design (only for KC705 for now):
   try to ping 192.168.1.40
   go to ./test directory run:
   run make test_etherbone

diff --git a/doc/source/docs/getting_started/downloads.rst b/doc/source/docs/getting_started/downloads.rst
index 1dd182ebc8abaa6d22e01efae618184206325687..d4368a15948ced774b879fb1b90e00b68f2190bf 100644 (file)
--- a/doc/source/docs/getting_started/downloads.rst
+++ b/doc/source/docs/getting_started/downloads.rst
@@ -11,40 +11,33 @@ Download and install
   - python3 setup.py install
   - cd ..
 
+.. note::
+  In case you have issues with Migen, please retry with our forks at:
+  https://github.com/enjoy-digital/migen
+  until new features are merged.
+
 3. Obtain LiteScope and install it:
   - git clone https://github.com/enjoy-digital/litescope
   - cd litescope
   - python3 setup.py install
   - cd ..
 
-4. Obtain MiSoC and install it:
-  - git clone https://github.com/m-labs/misoc --recursive
-  - cd misoc
-  - python3 setup.py install
-  - cd ..
-
-.. note::
-       In case you have issues with Migen/MiSoC, please retry with our forks at:
-       https://github.com/enjoy-digital/misoc
-       https://github.com/enjoy-digital/migen
-       until new features are merged.
-
-5. Obtain LiteEth
+4. Obtain LiteEth
   - git clone https://github.com/enjoy-digital/liteeth
 
-6. Build and load UDP loopback design (only for KC705 for now):
+5. Build and load UDP loopback design (only for KC705 for now):
   - python3 make.py -t udp all
 
-7. Test design (only for KC705 for now):
+6. Test design (only for KC705 for now):
   - try to ping 192.168.1.40
   - go to ./test directory:
   - change com port in config.py to your com port
   - run make test_udp
 
-8. Build and load Etherbone design (only for KC705 for now):
+7. Build and load Etherbone design (only for KC705 for now):
   - python3 make.py -t etherbone all
 
-9. Test design (only for KC705 for now):
+8. Test design (only for KC705 for now):
   - try to ping 192.168.1.40
   - go to ./test directory run:
   - run make test_etherbone
\ No newline at end of file

diff --git a/make.py b/make.py
index 3bc0dbb15b2357cb11d710360cebcba210ad5db3..c55c83398c0406da09c99a93240c6cee4f85fb08 100644 (file)
--- a/make.py
+++ b/make.py
@@ -6,13 +6,22 @@ from mibuild.tools import write_to_file
 from migen.util.misc import autotype
 from migen.fhdl import verilog, edif
 from migen.fhdl.structure import _Fragment
+from migen.bank.description import CSRStatus
 from mibuild import tools
 from mibuild.xilinx_common import *
 
-from misoclib.gensoc import cpuif
-
 from liteeth.common import *
 
+def get_csr_csv(regions):
+       r = ""
+       for name, origin, busword, obj in regions:
+               if not isinstance(obj, Memory):
+                       for csr in obj:
+                               nr = (csr.size + busword - 1)//busword
+                               r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
+                               origin += 4*nr
+       return r
+
 def _import(default, name):
        return importlib.import_module(default + "." + name)
 
@@ -118,7 +127,7 @@ System Clk: {} MHz
                subprocess.call(["rm", "-rf", "build/*"])
 
        if actions["build-csr-csv"]:
-               csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
+               csr_csv = get_csr_csv(soc.cpu_csr_regions)
                write_to_file(args.csr_csv, csr_csv)
 
        if actions["build-bitstream"]:

diff --git a/targets/__init__.py b/targets/__init__.py
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..85efe5d95f5b4b86fef0ca348005cd7a2a2f6c27 100644 (file)
--- a/targets/__init__.py
+++ b/targets/__init__.py
@@ -0,0 +1,26 @@
+import subprocess
+
+from migen.fhdl.std import *
+from migen.bank.description import *
+
+def get_id():
+       output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii")
+       return int(output[:8], 16)
+
+class Identifier(Module, AutoCSR):
+       def __init__(self, sysid, frequency, revision=None):
+               self._r_sysid = CSRStatus(16)
+               self._r_revision = CSRStatus(32)
+               self._r_frequency = CSRStatus(32)
+
+               ###
+
+               if revision is None:
+                       revision = get_id()
+
+               self.comb += [
+                       self._r_sysid.status.eq(sysid),
+                       self._r_revision.status.eq(revision),
+                       self._r_frequency.status.eq(frequency),
+               ]
+

diff --git a/targets/base.py b/targets/base.py
index 7b3479ff25b818c92fb9cc9c171ef5e4591c369a..3fe1f2a4dc4ea8b73b6a11901f11f1d17a88643a 100644 (file)
--- a/targets/base.py
+++ b/targets/base.py
@@ -7,7 +7,7 @@ from migen.genlib.cdc import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.bank.description import *
 
-from misoclib import identifier
+from targets import *
 
 from litescope.common import *
 from litescope.bridge.uart2wb import LiteScopeUART2WB
@@ -76,7 +76,7 @@ class GenSoC(Module):
                self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
 
                # CSR
-               self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
+               self.submodules.identifier = Identifier(0, int(clk_freq), 0)
 
        def add_wb_master(self, wbm):
                if self.finalized: