Fix constraint on 64-bit VIS3 vector moves.

	* config/sparc/sparc.md (64-bit vector moves): Use 'e' not 'f'
	constraint.

From-SVN: r180601

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 54e059e5197735e47da6de40242330e2692691cb..2d864d81af2b7c75928a38226e23a0a605aa2289 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 2011-10-27  David S. Miller  <davem@davemloft.net>
 
+       * config/sparc/sparc.md (64-bit vector moves): Use 'e' not 'f'
+       constraint.
+
        * regcprop.c (copyprop_hardreg_forward_1): Reject the
        transformation when we narrow the mode on big endian.
 

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 2b4b2bb54a43e1408c69ca0f2bd2ace4ecfa1020..dcd23a16d91903c60b121174f24f6ff9a544c40c 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -7686,8 +7686,8 @@
    (set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,*,vis3,vis3")])
 
 (define_insn "*mov<VM64:mode>_insn_sp64"
-  [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,e,m,m,*r, m,*r, f,*r")
-       (match_operand:VM64 1 "input_operand"         "Y,C,e,m,e,Y, m,*r, f,*r,*r"))]
+  [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,e,m,m,*r, m,*r, e,*r")
+       (match_operand:VM64 1 "input_operand"         "Y,C,e,m,e,Y, m,*r, e,*r,*r"))]
   "TARGET_VIS
    && TARGET_ARCH64
    && (register_operand (operands[0], <VM64:MODE>mode)