targets/genesys2: set cmd_latency to 1.

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 8557c0c52c5ade499465462347ad1085ce0c5626..d0b33def0c398cae4b36d8e5098670cf2801983c 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -56,7 +56,8 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                 memtype      = "DDR3",
                 nphases      = 4,
-                sys_clk_freq = sys_clk_freq)
+                sys_clk_freq = sys_clk_freq,
+                cmd_latency  = 1)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,