i965/gen6: Limit the workaround flush to once per primitive.

We're about to call this function in a bunch of state emits, so let's
not spam the hardware with flushes too hard.

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index d6a99ab06e2860106f4c4d9bfdf14820e622c3ca..636821839a11f20610eba218385ac45c3f7cef60 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -240,6 +240,8 @@ GLboolean brwCreateContext( int api,
 
    brw->emit_state_always = 0;
 
+   intel->batch.need_workaround_flush = true;
+
    ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
    ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
 

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 6144f0a2bcec985e664225080b14cef7a9d1fa4e..350fc51a8a1962cd7b451dc9b7d1694182debc89 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -177,6 +177,8 @@ static void brw_emit_prim(struct brw_context *brw,
    OUT_BATCH(base_vertex_location);
    ADVANCE_BATCH();
 
+   intel->batch.need_workaround_flush = true;
+
    if (intel->always_flush_cache) {
       intel_batchbuffer_emit_mi_flush(intel);
    }

diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 0f731482629a6783d63bc8e5513bcfc1c13d5cdd..8612e7432655666acf19c0f46a346c06b33c2686 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -118,6 +118,11 @@ static void brw_new_batch( struct intel_context *intel )
     */
    brw->state.dirty.brw |= BRW_NEW_CONTEXT | BRW_NEW_BATCH;
 
+   /* Assume that the last command before the start of our batch was a
+    * primitive, for safety.
+    */
+   intel->batch.need_workaround_flush = true;
+
    brw->vb.nr_current_buffers = 0;
 
    /* Mark that the current program cache BO has been used by the GPU.

diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index 9e8f8b5eefdf23cd0990dc763b3771c2536b04fa..77563aefdc5cf02fe9898f282fc020eb1c847055 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -296,6 +296,9 @@ emit:
 static void
 intel_emit_post_sync_nonzero_flush(struct intel_context *intel)
 {
+   if (!intel->batch.need_workaround_flush)
+      return;
+
    BEGIN_BATCH(4);
    OUT_BATCH(_3DSTATE_PIPE_CONTROL);
    OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
@@ -303,6 +306,8 @@ intel_emit_post_sync_nonzero_flush(struct intel_context *intel)
             I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT, 0);
    OUT_BATCH(0); /* write data */
    ADVANCE_BATCH();
+
+   intel->batch.need_workaround_flush = false;
 }
 
 /* Emit a pipelined flush to either flush render and texture cache for

diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 751af459e9c179e2b0726013ef37efeb334bb13e..148fb0c2c9a2cc30050a0f14706449778a8e1b82 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -183,6 +183,8 @@ struct intel_context
       drm_intel_bo *last_bo;
       /** BO for post-sync nonzero writes for gen6 workaround. */
       drm_intel_bo *workaround_bo;
+      bool need_workaround_flush;
+
       struct cached_batch_item *cached_items;
 
       uint16_t emit, total;