arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2

the Cortex-A15 has a random replacement policy for its L2 cache. see the
Cortex-A15 Technical Reference Manual 1.7 About the L2 memory system. this
patch makes the PseudoLRU tags the default for the ARM O3 CPU's L2 cache.

diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py
index 0202d19e4bb8001c24a22ffae873637b79b2308e..5a94438d79f86ca934a8290abb1b0b16e902409d 100644 (file)
--- a/configs/common/O3_ARM_v7a.py
+++ b/configs/common/O3_ARM_v7a.py
@@ -189,4 +189,4 @@ class O3_ARM_v7aL2(BaseCache):
     prefetch_on_access = 'true'
     # Simple stride prefetcher
     prefetcher = StridePrefetcher(degree=8, latency = 1)
-
+    tags = RandomRepl()