static uint32_t
ilo_blitter_blt_begin(struct ilo_blitter *blitter, int max_cmd_size,
- struct intel_bo *dst, enum intel_tiling_mode dst_tiling,
- struct intel_bo *src, enum intel_tiling_mode src_tiling)
+ struct intel_bo *dst,
+ enum gen_surface_tiling dst_tiling,
+ struct intel_bo *src,
+ enum gen_surface_tiling src_tiling)
{
struct ilo_cp *cp = blitter->ilo->cp;
struct intel_bo *aper_check[2];
/* set BCS_SWCTRL */
swctrl = 0x0;
- if (dst_tiling == INTEL_TILING_Y) {
+ assert(dst_tiling == GEN6_TILING_NONE ||
+ dst_tiling == GEN6_TILING_X ||
+ dst_tiling == GEN6_TILING_Y);
+ assert(src_tiling == GEN6_TILING_NONE ||
+ src_tiling == GEN6_TILING_X ||
+ src_tiling == GEN6_TILING_Y);
+
+ if (dst_tiling == GEN6_TILING_Y) {
swctrl |= GEN6_REG_BCS_SWCTRL_DST_TILING_Y << 16 |
GEN6_REG_BCS_SWCTRL_DST_TILING_Y;
}
- if (src && src_tiling == INTEL_TILING_Y) {
+ if (src && src_tiling == GEN6_TILING_Y) {
swctrl |= GEN6_REG_BCS_SWCTRL_SRC_TILING_Y << 16 |
GEN6_REG_BCS_SWCTRL_SRC_TILING_Y;
}
ilo_blitter_blt_begin(blitter, GEN6_COLOR_BLT__SIZE *
(1 + size / 32764 / gen6_blt_max_scanlines),
- dst.bo, INTEL_TILING_NONE, NULL, INTEL_TILING_NONE);
+ dst.bo, GEN6_TILING_NONE, NULL, GEN6_TILING_NONE);
while (size) {
unsigned width, height;
ilo_blitter_blt_begin(blitter, GEN6_SRC_COPY_BLT__SIZE *
(1 + size / 32764 / gen6_blt_max_scanlines),
- dst_buf->bo, INTEL_TILING_NONE, src_buf->bo, INTEL_TILING_NONE);
+ dst_buf->bo, GEN6_TILING_NONE, src_buf->bo, GEN6_TILING_NONE);
while (size) {
unsigned width, height;
uint32_t swctrl;
int slice;
- /* no W-tiling support */
- if (dst_tex->separate_s8)
+ /* no W-tiling nor separate stencil support */
+ if (dst_tex->layout.tiling == GEN8_TILING_W || dst_tex->separate_s8)
return false;
if (dst_tex->layout.bo_stride > max_extent)
swctrl = ilo_blitter_blt_begin(blitter,
GEN6_XY_COLOR_BLT__SIZE * dst_box->depth,
- dst_tex->bo, dst_tex->layout.tiling, NULL, INTEL_TILING_NONE);
+ dst_tex->bo, dst_tex->layout.tiling, NULL, GEN6_TILING_NONE);
for (slice = 0; slice < dst_box->depth; slice++) {
unsigned x, y;
uint32_t swctrl;
int cpp, xscale, slice;
- /* no W-tiling support */
- if (dst_tex->separate_s8 || src_tex->separate_s8)
+ /* no W-tiling nor separate stencil support */
+ if (dst_tex->layout.tiling == GEN8_TILING_W || dst_tex->separate_s8 ||
+ src_tex->layout.tiling == GEN8_TILING_W || src_tex->separate_s8)
return false;
if (dst_tex->layout.bo_stride > max_extent ||
uint32_t offset;
int16_t pitch;
- enum intel_tiling_mode tiling;
+ enum gen_surface_tiling tiling;
int16_t x, y;
};
gen6_blt_translate_write_mask(write_mask) |
(cmd_len - 2);
- if (dst->tiling != INTEL_TILING_NONE) {
+ if (dst->tiling != GEN6_TILING_NONE) {
dw[0] |= GEN6_BLITTER_BR00_DST_TILED;
- dst_align = (dst->tiling == INTEL_TILING_Y) ? 128 : 512;
+ assert(dst->tiling == GEN6_TILING_X || dst->tiling == GEN6_TILING_Y);
+ dst_align = (dst->tiling == GEN6_TILING_Y) ? 128 : 512;
/* in dwords when tiled */
dst_pitch_shift = 2;
}
gen6_blt_translate_write_mask(write_mask) |
(cmd_len - 2);
- if (dst->tiling != INTEL_TILING_NONE) {
+ if (dst->tiling != GEN6_TILING_NONE) {
dw[0] |= GEN6_BLITTER_BR00_DST_TILED;
- dst_align = (dst->tiling == INTEL_TILING_Y) ? 128 : 512;
+ assert(dst->tiling == GEN6_TILING_X || dst->tiling == GEN6_TILING_Y);
+ dst_align = (dst->tiling == GEN6_TILING_Y) ? 128 : 512;
/* in dwords when tiled */
dst_pitch_shift = 2;
}
- if (src->tiling != INTEL_TILING_NONE) {
+ if (src->tiling != GEN6_TILING_NONE) {
dw[0] |= GEN6_BLITTER_BR00_SRC_TILED;
- src_align = (src->tiling == INTEL_TILING_Y) ? 128 : 512;
+ assert(src->tiling == GEN6_TILING_X || src->tiling == GEN6_TILING_Y);
+ src_align = (src->tiling == GEN6_TILING_Y) ? 128 : 512;
/* in dwords when tiled */
src_pitch_shift = 2;
}
#include "ilo_layout.h"
enum {
- LAYOUT_TILING_NONE = 1 << INTEL_TILING_NONE,
- LAYOUT_TILING_X = 1 << INTEL_TILING_X,
- LAYOUT_TILING_Y = 1 << INTEL_TILING_Y,
- LAYOUT_TILING_W = 1 << (INTEL_TILING_Y + 1),
+ LAYOUT_TILING_NONE = 1 << GEN6_TILING_NONE,
+ LAYOUT_TILING_X = 1 << GEN6_TILING_X,
+ LAYOUT_TILING_Y = 1 << GEN6_TILING_Y,
+ LAYOUT_TILING_W = 1 << GEN8_TILING_W,
LAYOUT_TILING_ALL = (LAYOUT_TILING_NONE |
LAYOUT_TILING_X |
(templ->nr_samples > 1) ||
(ilo_dev_gen(params->dev) >= ILO_GEN(8)) ||
(ilo_dev_gen(params->dev) >= ILO_GEN(7) &&
- layout->tiling == INTEL_TILING_Y &&
+ layout->tiling == GEN6_TILING_Y &&
(templ->bind & PIPE_BIND_RENDER_TARGET));
if (ilo_dev_gen(params->dev) >= ILO_GEN(7) &&
{
const struct pipe_resource *templ = params->templ;
const enum pipe_format format = layout->format;
- unsigned valid_tilings = LAYOUT_TILING_ALL;
+ /* W-tiling is too restrictive */
+ unsigned valid_tilings = LAYOUT_TILING_ALL & ~LAYOUT_TILING_W;
/*
* From the Sandy Bridge PRM, volume 1 part 2, page 32:
if (templ->bind & PIPE_BIND_DEPTH_STENCIL) {
switch (format) {
case PIPE_FORMAT_S8_UINT:
- valid_tilings &= LAYOUT_TILING_W;
+ /* this is the only case LAYOUT_TILING_W is valid */
+ valid_tilings = LAYOUT_TILING_W;
break;
default:
valid_tilings &= LAYOUT_TILING_Y;
const struct pipe_resource *templ = params->templ;
unsigned valid_tilings = layout_get_valid_tilings(layout, params);
- /* no hardware support for W-tile */
- if (valid_tilings & LAYOUT_TILING_W)
- valid_tilings = (valid_tilings & ~LAYOUT_TILING_W) | LAYOUT_TILING_NONE;
-
layout->valid_tilings = valid_tilings;
if (templ->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW)) {
/* prefer tiled over linear */
if (valid_tilings & LAYOUT_TILING_Y)
- layout->tiling = INTEL_TILING_Y;
+ layout->tiling = GEN6_TILING_Y;
else if (valid_tilings & LAYOUT_TILING_X)
- layout->tiling = INTEL_TILING_X;
+ layout->tiling = GEN6_TILING_X;
+ else if (valid_tilings & LAYOUT_TILING_W)
+ layout->tiling = GEN8_TILING_W;
else
- layout->tiling = INTEL_TILING_NONE;
+ layout->tiling = GEN6_TILING_NONE;
}
static void
* 32bpp, 64bpp and 128bpp.
* ..."
*/
- if (layout->tiling != INTEL_TILING_NONE &&
+ if (layout->tiling != GEN6_TILING_NONE &&
templ->last_level == 0 && templ->array_size == 1) {
switch (layout->block_size) {
case 4:
*/
if (ilo_dev_gen(params->dev) >= ILO_GEN(7.5) &&
(params->templ->bind & PIPE_BIND_SAMPLER_VIEW) &&
- layout->tiling == INTEL_TILING_NONE) {
+ layout->tiling == GEN6_TILING_NONE) {
layout->bo_height +=
(64 + layout->bo_stride - 1) / layout->bo_stride;
}
* need to check layout->templ->bind.
*/
switch (layout->tiling) {
- case INTEL_TILING_X:
+ case GEN6_TILING_X:
align_w = 512;
align_h = 8;
break;
- case INTEL_TILING_Y:
+ case GEN6_TILING_Y:
align_w = 128;
align_h = 32;
break;
+ case GEN8_TILING_W:
+ /*
+ * From the Sandy Bridge PRM, volume 1 part 2, page 22:
+ *
+ * "A 4KB tile is subdivided into 8-high by 8-wide array of
+ * Blocks for W-Major Tiles (W Tiles). Each Block is 8 rows by 8
+ * bytes."
+ */
+ align_w = 64;
+ align_h = 64;
+ break;
default:
- if (layout->format == PIPE_FORMAT_S8_UINT) {
- /*
- * From the Sandy Bridge PRM, volume 1 part 2, page 22:
- *
- * "A 4KB tile is subdivided into 8-high by 8-wide array of
- * Blocks for W-Major Tiles (W Tiles). Each Block is 8 rows by 8
- * bytes."
- *
- * Since we asked for INTEL_TILING_NONE instead of the non-existent
- * INTEL_TILING_W, we want to align to W tiles here.
- */
- align_w = 64;
- align_h = 64;
- } else {
- /* some good enough values */
- align_w = 64;
- align_h = 2;
- }
+ assert(layout->tiling == GEN6_TILING_NONE);
+ /* some good enough values */
+ align_w = 64;
+ align_h = 2;
break;
}
h = align(h, align_h);
/* make sure the bo is mappable */
- if (layout->tiling != INTEL_TILING_NONE) {
+ if (layout->tiling != GEN6_TILING_NONE) {
/*
* Usually only the first 256MB of the GTT is mappable.
*
*/
if (mappable_gtt_size / w / 4 < h) {
if (layout->valid_tilings & LAYOUT_TILING_NONE) {
- layout->tiling = INTEL_TILING_NONE;
+ layout->tiling = GEN6_TILING_NONE;
/* MCS support for non-MSRTs is limited to tiled RTs */
if (layout->aux == ILO_LAYOUT_AUX_MCS &&
params->templ->nr_samples <= 1)
* hit out-of-bound access.
*/
switch (layout->tiling) {
- case INTEL_TILING_X:
+ case GEN6_TILING_X:
downscale_x = 64 / layout->block_size;
downscale_y = 2;
break;
- case INTEL_TILING_Y:
+ case GEN6_TILING_Y:
downscale_x = 32 / layout->block_size;
downscale_y = 4;
break;
layout->walk = ILO_LAYOUT_WALK_LOD;
layout->valid_tilings = LAYOUT_TILING_NONE;
- layout->tiling = INTEL_TILING_NONE;
+ layout->tiling = GEN6_TILING_NONE;
layout->align_i = layout->block_width;
layout->align_j = layout->block_height;
*/
bool
ilo_layout_update_for_imported_bo(struct ilo_layout *layout,
- enum intel_tiling_mode tiling,
+ enum gen_surface_tiling tiling,
unsigned bo_stride)
{
if (!(layout->valid_tilings & (1 << tiling)))
return false;
- if ((tiling == INTEL_TILING_X && bo_stride % 512) ||
- (tiling == INTEL_TILING_Y && bo_stride % 128))
+ if ((tiling == GEN6_TILING_X && bo_stride % 512) ||
+ (tiling == GEN6_TILING_Y && bo_stride % 128) ||
+ (tiling == GEN8_TILING_W && bo_stride % 64))
return false;
layout->tiling = tiling;
#ifndef ILO_LAYOUT_H
#define ILO_LAYOUT_H
-#include "intel_winsys.h"
+#include "genhw/genhw.h"
#include "ilo_common.h"
/* bitmask of valid tiling modes */
unsigned valid_tilings;
- enum intel_tiling_mode tiling;
+ enum gen_surface_tiling tiling;
/* mipmap alignments */
unsigned align_i;
bool
ilo_layout_update_for_imported_bo(struct ilo_layout *layout,
- enum intel_tiling_mode tiling,
+ enum gen_surface_tiling tiling,
unsigned bo_stride);
/**
unsigned tile_w, tile_h;
switch (layout->tiling) {
- case INTEL_TILING_NONE:
- if (layout->format == PIPE_FORMAT_S8_UINT) {
- /* W-tile */
- tile_w = 64;
- tile_h = 64;
- } else {
- tile_w = 1;
- tile_h = 1;
- }
+ case GEN6_TILING_NONE:
+ tile_w = 1;
+ tile_h = 1;
break;
- case INTEL_TILING_X:
+ case GEN6_TILING_X:
tile_w = 512;
tile_h = 8;
break;
- case INTEL_TILING_Y:
+ case GEN6_TILING_Y:
tile_w = 128;
tile_h = 32;
break;
+ case GEN8_TILING_W:
+ tile_w = 64;
+ tile_h = 64;
+ break;
default:
assert(!"unknown tiling");
tile_w = 1;
PIPE_BIND_STREAM_OUTPUT)) ? false : true;
}
+static enum gen_surface_tiling
+winsys_to_surface_tiling(enum intel_tiling_mode tiling)
+{
+ switch (tiling) {
+ case INTEL_TILING_NONE:
+ return GEN6_TILING_NONE;
+ case INTEL_TILING_X:
+ return GEN6_TILING_X;
+ case INTEL_TILING_Y:
+ return GEN6_TILING_Y;
+ default:
+ assert(!"unknown tiling");
+ return GEN6_TILING_NONE;
+ }
+}
+
+static inline enum intel_tiling_mode
+surface_to_winsys_tiling(enum gen_surface_tiling tiling)
+{
+ switch (tiling) {
+ case GEN6_TILING_NONE:
+ return INTEL_TILING_NONE;
+ case GEN6_TILING_X:
+ return INTEL_TILING_X;
+ case GEN6_TILING_Y:
+ return INTEL_TILING_Y;
+ default:
+ assert(!"unknown tiling");
+ return GEN6_TILING_NONE;
+ }
+}
+
static void
tex_free_slices(struct ilo_texture *tex)
{
if (!tex->bo)
return false;
- if (!ilo_layout_update_for_imported_bo(&tex->layout, tiling, pitch)) {
+ if (!ilo_layout_update_for_imported_bo(&tex->layout,
+ winsys_to_surface_tiling(tiling), pitch)) {
ilo_err("imported handle has incompatible tiling/pitch\n");
intel_bo_unreference(tex->bo);
tex->bo = NULL;
struct ilo_screen *is = ilo_screen(tex->base.screen);
const char *name = resource_get_bo_name(&tex->base);
const bool cpu_init = resource_get_cpu_init(&tex->base);
+ enum intel_tiling_mode tiling;
+
+ /* no native support */
+ if (tex->layout.tiling == GEN8_TILING_W)
+ tiling = INTEL_TILING_NONE;
+ else
+ tiling = surface_to_winsys_tiling(tex->layout.tiling);
- tex->bo = intel_winsys_alloc_bo(is->winsys, name, tex->layout.tiling,
+ tex->bo = intel_winsys_alloc_bo(is->winsys, name, tiling,
tex->layout.bo_stride, tex->layout.bo_height, cpu_init);
return (tex->bo != NULL);
struct ilo_screen *is = ilo_screen(tex->base.screen);
unsigned lv;
- tex->aux_bo = intel_winsys_alloc_bo(is->winsys, "hiz texture",
- INTEL_TILING_Y, tex->layout.aux_stride, tex->layout.aux_height,
- false);
+ tex->aux_bo = intel_winsys_alloc_buffer(is->winsys, "hiz texture",
+ tex->layout.aux_stride * tex->layout.aux_height, false);
if (!tex->aux_bo)
return false;
assert(tex->layout.aux_enables == (1 << (tex->base.last_level + 1)) - 1);
- tex->aux_bo = intel_winsys_alloc_bo(is->winsys, "mcs texture",
- INTEL_TILING_Y, tex->layout.aux_stride, tex->layout.aux_height,
- false);
+ tex->aux_bo = intel_winsys_alloc_buffer(is->winsys, "mcs texture",
+ tex->layout.aux_stride * tex->layout.aux_height, false);
if (!tex->aux_bo)
return false;
if (templ->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) {
/* require on-the-fly tiling/untiling or format conversion */
- if (layout->separate_stencil ||
- layout->format == PIPE_FORMAT_S8_UINT ||
+ if (layout->tiling == GEN8_TILING_W || layout->separate_stencil ||
layout->format != templ->format)
return false;
}
tex_get_handle(struct ilo_texture *tex, struct winsys_handle *handle)
{
struct ilo_screen *is = ilo_screen(tex->base.screen);
+ enum intel_tiling_mode tiling;
int err;
- err = intel_winsys_export_handle(is->winsys, tex->bo, tex->layout.tiling,
+ /* no native support */
+ if (tex->layout.tiling == GEN8_TILING_W)
+ tiling = INTEL_TILING_NONE;
+ else
+ tiling = surface_to_winsys_tiling(tex->layout.tiling);
+
+ err = intel_winsys_export_handle(is->winsys, tex->bo, tiling,
tex->layout.bo_stride, tex->layout.bo_height, handle);
return !err;
struct ilo_texture *tex = ilo_texture(res);
/* warn about degraded performance because of a missing binding flag */
- if (tex->layout.tiling == INTEL_TILING_NONE &&
+ if (tex->layout.tiling == GEN6_TILING_NONE &&
!(tex->base.bind & PIPE_BIND_SAMPLER_VIEW)) {
ilo_warn("creating sampler view for a resource "
"not created for sampling\n");
#include "ilo_common.h"
#include "ilo_state.h"
-/**
- * Translate winsys tiling to hardware tiling.
- */
-static inline int
-ilo_gpe_gen6_translate_winsys_tiling(enum intel_tiling_mode tiling)
-{
- switch (tiling) {
- case INTEL_TILING_NONE:
- return GEN6_TILING_NONE;
- case INTEL_TILING_X:
- return GEN6_TILING_X;
- case INTEL_TILING_Y:
- return GEN6_TILING_Y;
- default:
- assert(!"unknown tiling");
- return GEN6_TILING_NONE;
- }
-}
-
/**
* Translate a pipe texture target to the matching hardware surface type.
*/
struct intel_bo *bo;
unsigned stride;
unsigned qpitch;
- enum intel_tiling_mode tiling;
+ enum gen_surface_tiling tiling;
uint32_t offset;
} zs, stencil, hiz;
assert(tex->layout.aux_layer_height % 4 == 0);
info->hiz.qpitch = tex->layout.aux_layer_height / 4;
- info->hiz.tiling = INTEL_TILING_Y;
+ info->hiz.tiling = GEN6_TILING_Y;
/* offset to the level */
if (ilo_dev_gen(dev) == ILO_GEN(6))
if (info.zs.bo) {
/* required for GEN6+ */
- assert(info.zs.tiling == INTEL_TILING_Y);
+ assert(info.zs.tiling == GEN6_TILING_Y);
assert(info.zs.stride > 0 && info.zs.stride < 128 * 1024 &&
info.zs.stride % 128 == 0);
assert(info.width <= info.zs.stride);
*
* "For linear surfaces, this field (X Offset) must be zero"
*/
- if (tex->layout.tiling == INTEL_TILING_NONE) {
+ if (tex->layout.tiling == GEN6_TILING_NONE) {
if (is_rt) {
const int elem_size = util_format_get_blocksize(format);
assert(pitch % elem_size == 0);
(width - 1) << GEN6_SURFACE_DW2_WIDTH__SHIFT |
lod << GEN6_SURFACE_DW2_MIP_COUNT_LOD__SHIFT;
+ assert(tex->layout.tiling != GEN8_TILING_W);
dw[3] = (depth - 1) << GEN6_SURFACE_DW3_DEPTH__SHIFT |
(pitch - 1) << GEN6_SURFACE_DW3_PITCH__SHIFT |
- ilo_gpe_gen6_translate_winsys_tiling(tex->layout.tiling);
+ tex->layout.tiling;
dw[4] = first_level << GEN6_SURFACE_DW4_MIN_LOD__SHIFT |
first_layer << 17 |
*
* "For linear surfaces, this field (X Offset) must be zero."
*/
- if (tex->layout.tiling == INTEL_TILING_NONE) {
+ if (tex->layout.tiling == GEN6_TILING_NONE) {
if (is_rt) {
const int elem_size = util_format_get_blocksize(format);
assert(pitch % elem_size == 0);
break;
}
- dw[0] |= ilo_gpe_gen6_translate_winsys_tiling(tex->layout.tiling) <<
- GEN8_SURFACE_DW0_TILING__SHIFT;
+ dw[0] |= tex->layout.tiling << GEN8_SURFACE_DW0_TILING__SHIFT;
} else {
assert(tex->layout.align_i == 4 || tex->layout.align_i == 8);
assert(tex->layout.align_j == 2 || tex->layout.align_j == 4);
if (tex->layout.align_i == 8)
dw[0] |= GEN7_SURFACE_DW0_HALIGN_8;
- dw[0] |= ilo_gpe_gen6_translate_winsys_tiling(tex->layout.tiling) <<
- GEN7_SURFACE_DW0_TILING__SHIFT;
+ assert(tex->layout.tiling != GEN8_TILING_W);
+ dw[0] |= tex->layout.tiling << GEN7_SURFACE_DW0_TILING__SHIFT;
if (tex->layout.walk == ILO_LAYOUT_WALK_LOD)
dw[0] |= GEN7_SURFACE_DW0_ARYSPC_LOD0;
if (res->target == PIPE_BUFFER) {
tiled = false;
- }
- else {
+ } else {
struct ilo_texture *tex = ilo_texture(res);
bool need_convert = false;
/* we may need to convert on the fly */
- if (tex->separate_s8 || tex->layout.format == PIPE_FORMAT_S8_UINT) {
+ if (tex->layout.tiling == GEN8_TILING_W || tex->separate_s8) {
/* on GEN6, separate stencil is enabled only when HiZ is */
if (ilo_dev_gen(&is->dev) >= ILO_GEN(7) ||
ilo_texture_can_enable_hiz(tex, transfer->level,
return true;
}
- tiled = (tex->layout.tiling != INTEL_TILING_NONE);
+ tiled = (tex->layout.tiling != GEN6_TILING_NONE);
}
if (tiled)
if (xfer->staging.res && xfer->staging.res->target != PIPE_BUFFER) {
assert(ilo_texture(xfer->staging.res)->layout.tiling ==
- INTEL_TILING_NONE);
+ GEN6_TILING_NONE);
}
return (xfer->staging.res != NULL);
unsigned *tiles_per_row)
{
switch (tex->layout.tiling) {
- case INTEL_TILING_X:
+ default:
+ assert(!"unknown tiling");
+ /* fall through */
+ case GEN6_TILING_NONE:
+ *tiles_per_row = tex->layout.bo_stride;
+ return tex_tile_none_offset;
+ case GEN6_TILING_X:
*tiles_per_row = tex->layout.bo_stride / 512;
return tex_tile_x_offset;
- case INTEL_TILING_Y:
+ case GEN6_TILING_Y:
*tiles_per_row = tex->layout.bo_stride / 128;
return tex_tile_y_offset;
- case INTEL_TILING_NONE:
- default:
- /* W-tiling */
- if (tex->layout.format == PIPE_FORMAT_S8_UINT) {
- *tiles_per_row = tex->layout.bo_stride / 64;
- return tex_tile_w_offset;
- }
- else {
- *tiles_per_row = tex->layout.bo_stride;
- return tex_tile_none_offset;
- }
+ case GEN8_TILING_W:
+ *tiles_per_row = tex->layout.bo_stride / 64;
+ return tex_tile_w_offset;
}
}
const bool prefer_cpu = (is->dev.has_llc || for_read_back);
void *ptr;
- if (prefer_cpu && (tex->layout.tiling == INTEL_TILING_NONE ||
+ if (prefer_cpu && (tex->layout.tiling == GEN6_TILING_NONE ||
!linear_view))
ptr = intel_bo_map(tex->bo, !for_read_back);
else
projects / mesa.git / commitdiff