Add a sparc simulator with the sparc bareboard target.

gdb/ChangeLog:

        * configure.tgt (sparc-*-*): Set gdb_sim to ../sim/erc32/libsim.a.
        (sparc-*-rtems*): Delete, now redundant with the sparc-*-* case.

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 7cf8d9066b0cb27000aa1039a7cf145c4abf16c5..e8b81e81f21174d4866ae0d2876f956d0f2c7568 100644 (file)
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,8 @@
+2010-09-28  Joel Brobecker  <brobecker@adacore.com>
+
+       * configure.tgt (sparc-*-*): Set gdb_sim to ../sim/erc32/libsim.a.
+        (sparc-*-rtems*): Delete. Now redundant with sparc-*-*.
+
 2010-09-28  Joel Brobecker  <brobecker@adacore.com>
 
        * NEWS: Announce Ravenscar Profile support.

diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index 80cfb4902724a608f8bf217a3360f865eb50af2e..24a6bf91c12a6206708025f1ec4bf01b748cc348 100644 (file)
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -514,15 +514,11 @@ sparc-*-solaris2* | sparcv9-*-solaris2* | sparc64-*-solaris2*)
        gdb_target_obs="sparc64-tdep.o sparc64-sol2-tdep.o sparc-tdep.o \
                        sparc-sol2-tdep.o sol2-tdep.o solib.o solib-svr4.o"
        ;;
-sparc-*-rtems*)
-       # Target: SPARC embedded with simulator
-       gdb_target_obs="sparc-tdep.o"
-       gdb_sim=../sim/erc32/libsim.a
-       ;;
 sparc-*-*)
        # Target: SPARC
        gdb_target_obs="sparc-tdep.o ravenscar-thread.o \
                        ravenscar-sparc-thread.o"
+       gdb_sim=../sim/erc32/libsim.a
        ;;
 sparc64-*-*)
        # Target: UltraSPARC