Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 09d6e9670d45a21fad08d65b6eb4993cc8edc64f..8932e860a32fb9c958d5797bef03febe7537212c 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -247,7 +247,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
                bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
                bool show_tempdir, std::string box_file, std::string lut_file,
-               std::string wire_delay, const dict<int,IdString> &box_lookup
+               std::string wire_delay, const dict<int,IdString> &box_lookup, bool nomfs
 )
 {
        module = current_module;
@@ -346,6 +346,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
        for (size_t pos = abc_script.find("{W}"); pos != std::string::npos; pos = abc_script.find("{W}", pos))
                abc_script = abc_script.substr(0, pos) + wire_delay + abc_script.substr(pos+3);
 
+       if (nomfs)
+               for (size_t pos = abc_script.find("&mfs"); pos != std::string::npos; pos = abc_script.find("&mfs", pos))
+                       abc_script = abc_script.erase(pos, strlen("&mfs"));
+
+
        abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
        abc_script = add_echos_to_abc_cmd(abc_script);
 
@@ -921,6 +926,7 @@ struct Abc9Pass : public Pass {
                std::string delay_target, lutin_shared = "-S 1", wire_delay;
                bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
                bool show_tempdir = false;
+               bool nomfs = false;
                vector<int> lut_costs;
                markgroups = false;
 
@@ -1043,6 +1049,10 @@ struct Abc9Pass : public Pass {
                                wire_delay = "-W " + args[++argidx];
                                continue;
                        }
+                       if (arg == "-nomfs") {
+                               nomfs = true;
+                               continue;
+                       }
                        break;
                }
                extra_args(args, argidx, design);
@@ -1131,7 +1141,7 @@ struct Abc9Pass : public Pass {
                        if (!dff_mode || !clk_str.empty()) {
                                abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
                                                delay_target, lutin_shared, fast_mode, show_tempdir,
-                                               box_file, lut_file, wire_delay, box_lookup);
+                                               box_file, lut_file, wire_delay, box_lookup, nomfs);
                                continue;
                        }
 
@@ -1277,7 +1287,7 @@ struct Abc9Pass : public Pass {
                                en_sig = assign_map(std::get<3>(it.first));
                                abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$",
                                                keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
-                                               box_file, lut_file, wire_delay, box_lookup);
+                                               box_file, lut_file, wire_delay, box_lookup, nomfs);
                                assign_map.set(mod);
                        }
                }

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7085214de52fd5bf36a2dd9afce3b3b893fed619..1cddd2a921bb6eedaba1235ed8416db13c039d67 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -477,10 +477,14 @@ struct SynthXilinxPass : public ScriptPass
                                        log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
                                run("techmap -map +/xilinx/abc_map.v -max_iter 1");
                                run("read_verilog -icells -lib +/xilinx/abc_model.v");
+                               std::string abc9_opts = " -box +/xilinx/abc_xc7.box";
+                               abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
+                               abc9_opts += " -nomfs";
                                if (nowidelut)
-                                       run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
+                                       abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut";
                                else
-                                       run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
+                                       abc9_opts += " -lut +/xilinx/abc_xc7.lut";
+                               run("abc9" + abc9_opts);
                        }
                        else {
                                if (nowidelut)