* simops.c: Fix carry bit computation for "add" instructions.

More bugs exposed by new mn10300 compiler optimizations.

diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index d6010654246c687c64589fa4d8d7fe4cf7e1e445..b0d179112e8e977d18dac8347504d9ebab250efc 100644 (file)
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,5 +1,7 @@
 Wed Mar 12 15:04:00 1997  Jeffrey A Law  (law@cygnus.com)
 
+       * simops.c: Fix carry bit computation for "add" instructions.
+
        * simops.c: Fix typos in bset insns.  Fix arguments to store_mem
        for bset imm8,(d8,an) and bclr imm8,(d8,an).
 

diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index cd4c98fea2984e9a23c39798a17e0d4d202c02ff..3fe6799821901595ae3eb471e34fe09ffeefcc2f 100644 (file)
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -997,7 +997,7 @@ void OP_E0 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < reg2);
+  c = (value < reg1) || (value < reg2);
   v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));
 
@@ -1020,7 +1020,7 @@ void OP_F160 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < reg2);
+  c = (value < reg1) || (value < reg2);
   v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));
 
@@ -1043,7 +1043,7 @@ void OP_F150 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < reg2);
+  c = (value < reg1) || (value < reg2);
   v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));
 
@@ -1066,7 +1066,7 @@ void OP_F170 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < reg2);
+  c = (value < reg1) || (value < reg2);
   v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));
 
@@ -1089,7 +1089,7 @@ void OP_2800 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < imm);
+  c = (value < reg1) || (value < imm);
   v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
@@ -1112,7 +1112,7 @@ void OP_FAC00000 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < imm);
+  c = (value < reg1) || (value < imm);
   v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
@@ -1135,7 +1135,7 @@ void OP_FCC00000 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < imm);
+  c = (value < reg1) || (value < imm);
   v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
@@ -1158,7 +1158,7 @@ void OP_2000 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < imm);
+  c = (value < reg1) || (value < imm);
   v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
@@ -1181,7 +1181,7 @@ void OP_FAD00000 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < imm);
+  c = (value < reg1) || (value < imm);
   v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
@@ -1204,7 +1204,7 @@ void OP_FCD00000 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < imm);
+  c = (value < reg1) || (value < imm);
   v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
@@ -1263,7 +1263,7 @@ void OP_F140 (insn, extension)
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < reg2);
+  c = (value < reg1) || (value < reg2);
   v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));