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Fix DDR3 module parameter
authorJean THOMAS <git0@pub.jeanthomas.me>
Fri, 10 Jul 2020 16:32:32 +0000 (18:32 +0200)
committerJean THOMAS <git0@pub.jeanthomas.me>
Fri, 10 Jul 2020 16:32:32 +0000 (18:32 +0200)
examples/headless-ecpix5.py patch | blob | history

diff --git a/examples/headless-ecpix5.py b/examples/headless-ecpix5.py
index a7e4867bee250fe9838435b425f5887a337777bd..14733c58dc69c9bb1f7f04c24c998a295bc66335 100644 (file)
--- a/examples/headless-ecpix5.py
+++ b/examples/headless-ecpix5.py
@@ -185,7 +185,7 @@ class DDR3SoC(SoC, Elaboratable):
         self.ddrphy = ECP5DDRPHY(platform.request("ddr3", 0))
         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
 
-        ddrmodule = MT41K256M16(clk_freq, "1:4")
+        ddrmodule = MT41K256M16(platform.default_clk_frequency, "1:2")
 
         self.dramcore = gramCore(
             phy=self.ddrphy,