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diff --git a/3d_gpu/architecture/dynamic_simd/logicops.mdwn b/3d_gpu/architecture/dynamic_simd/logicops.mdwn
index 8a51be53e0293e750df18b9a795f6ffe5e6b5068..f44712a19d0f3bd24f1fc50542bab50ec9c1698c 100644 (file)
--- a/3d_gpu/architecture/dynamic_simd/logicops.mdwn
+++ b/3d_gpu/architecture/dynamic_simd/logicops.mdwn
@@ -16,6 +16,9 @@ they are instead SIMD versions of:
      for i in range(64):
          result = result xor a[i] # one operand
 
+Each of the logic ops, "some bool any all xor" are a single bit for
+scalar, but for Partitioned SIMD produce one bit per lane.
+
 # Requirements
 
 Given a signal width (typically 64) and given an array of "Partition Points" (typically 7) that break the signal down into an arbitrary permutaion of 8 bit to 64 bit independent SIMD results, compute the following: