for i in xrange(options.num_cpus) ]
# create the desired simulated system
-system = System(cpu = cpus, physmem = SimpleMemory(),
- mem_ranges = [AddrRange(options.mem_size)])
+system = System(cpu = cpus, mem_ranges = [AddrRange(options.mem_size)])
# Create a top-level voltage domain and clock domain
# run simulation
# -----------------------
-root = Root( full_system = False, system = system )
+root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'
# Not much point in this being higher than the L1 latency