hdl.ast: allow sampling ClockSignal, ResetSignal.
authorwhitequark <cz@m-labs.hk>
Thu, 17 Jan 2019 05:23:06 +0000 (05:23 +0000)
committerwhitequark <cz@m-labs.hk>
Thu, 17 Jan 2019 05:23:06 +0000 (05:23 +0000)
nmigen/hdl/ast.py
nmigen/hdl/xfrm.py
nmigen/test/test_hdl_ast.py

index 4b413811000dc953410b118103b5dbe510b2bf6d..735f412b0ad0ec23bda0fcb9bb115b7757de04c7 100644 (file)
@@ -844,7 +844,7 @@ class Sample(Value):
         self.value  = Value.wrap(expr)
         self.clocks = int(clocks)
         self.domain = domain
-        if not isinstance(self.value, (Const, Signal)):
+        if not isinstance(self.value, (Const, Signal, ClockSignal, ResetSignal)):
             raise TypeError("Sampled value may only be a signal or a constant, not {!r}"
                             .format(self.value))
         if self.clocks < 0:
index 40ce767ef7a5ba805b26d32e9847814712f5cfda..473139b900e53349afca77964bb425567e70093f 100644 (file)
@@ -364,6 +364,10 @@ class SampleLowerer(FragmentTransformer, ValueTransformer, StatementTransformer)
             return "c${}".format(value.value), value.value
         elif isinstance(value, Signal):
             return "s${}".format(value.name), value.reset
+        elif isinstance(value, ClockSignal):
+            return "clk", 0
+        elif isinstance(value, ResetSignal):
+            return "rst", 1
         else:
             raise NotImplementedError # :nocov:
 
index 1aee24b18745d608857c699b558c3eb07435a9ab..d1c5bb52a134e7c6d4e980c96880012485e16c59 100644 (file)
@@ -504,8 +504,10 @@ class SampleTestCase(FHDLTestCase):
         self.assertEqual(s.shape(), (1, False))
 
     def test_signal(self):
-        s = Sample(Signal(2), 1, "sync")
-        self.assertEqual(s.shape(), (2, False))
+        s1 = Sample(Signal(2), 1, "sync")
+        self.assertEqual(s1.shape(), (2, False))
+        s2 = Sample(ClockSignal(), 1, "sync")
+        s3 = Sample(ResetSignal(), 1, "sync")
 
     def test_wrong_value_operator(self):
         with self.assertRaises(TypeError,