Fix typo

diff --git a/src/sim/System.py b/src/sim/System.py
index 5712a5c03d24a4d7caa4aac2d004e41821a1e63f..3b0bc1e46254bba00ef5f0eea2ada60211cce8f7 100644 (file)
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -38,7 +38,7 @@ class System(SimObject):
     type = 'System'
     swig_objdecls = [ '%include "python/swig/system.i"' ]
 
-    physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
+    physmem = Param.PhysicalMemory(Parent.any, "physical memory")
     mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
     if build_env['FULL_SYSTEM']:
         abstract = True