radv: Add queue masks for htile usage determination.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index e0574f5cbf1c3ec85189278453091a87871caeac..d0101259fb16ed4259f737639c125b766c8abf0a 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -928,7 +928,10 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
        uint32_t db_z_info = ds->db_z_info;
        uint32_t db_stencil_info = ds->db_stencil_info;
 
-       if (!radv_layout_has_htile(image, layout)) {
+       if (!radv_layout_has_htile(image, layout,
+                                  radv_image_queue_family_mask(image,
+                                                               cmd_buffer->queue_family_index,
+                                                               cmd_buffer->queue_family_index))) {
                db_z_info &= C_028040_TILE_SURFACE_ENABLE;
                db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
        }
@@ -1103,10 +1106,12 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
                struct radv_attachment_info *att = &framebuffer->attachments[idx];
                struct radv_image *image = att->attachment->image;
                cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
-
+               uint32_t queue_mask = radv_image_queue_family_mask(image,
+                                                                  cmd_buffer->queue_family_index,
+                                                                  cmd_buffer->queue_family_index);
                /* We currently don't support writing decompressed HTILE */
-               assert(radv_layout_has_htile(image, layout) ==
-                      radv_layout_is_htile_compressed(image, layout));
+               assert(radv_layout_has_htile(image, layout, queue_mask) ==
+                      radv_layout_is_htile_compressed(image, layout, queue_mask));
 
                radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
 
@@ -2993,6 +2998,8 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe
                                               struct radv_image *image,
                                               VkImageLayout src_layout,
                                               VkImageLayout dst_layout,
+                                              unsigned src_queue_mask,
+                                              unsigned dst_queue_mask,
                                               const VkImageSubresourceRange *range,
                                               VkImageAspectFlags pending_clears)
 {
@@ -3004,11 +3011,11 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe
                /* The clear will initialize htile. */
                return;
        } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
-                  radv_layout_has_htile(image, dst_layout)) {
+                  radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
                /* TODO: merge with the clear if applicable */
                radv_initialize_htile(cmd_buffer, image, range);
-       } else if (radv_layout_is_htile_compressed(image, src_layout) &&
-                  !radv_layout_is_htile_compressed(image, dst_layout)) {
+       } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
+                  !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
                VkImageSubresourceRange local_range = *range;
                local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
                local_range.baseMipLevel = 0;
@@ -3124,7 +3131,9 @@ static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
 
        if (image->surface.htile_size)
                radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
-                                                  dst_layout, range, pending_clears);
+                                                  dst_layout, src_queue_mask,
+                                                  dst_queue_mask, range,
+                                                  pending_clears);
 
        if (image->cmask.size)
                radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 62f5f01400e0dfd8bec95ddd41ec25ba98fd1c0c..9a76d2852429476e469f79adbe3fc042519d4eab 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -771,19 +771,23 @@ radv_image_view_init(struct radv_image_view *iview,
 }
 
 bool radv_layout_has_htile(const struct radv_image *image,
-                           VkImageLayout layout)
+                           VkImageLayout layout,
+                           unsigned queue_mask)
 {
        return image->surface.htile_size &&
               (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
-               layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
+               layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
+              queue_mask == (1u << RADV_QUEUE_GENERAL);
 }
 
 bool radv_layout_is_htile_compressed(const struct radv_image *image,
-                                     VkImageLayout layout)
+                                     VkImageLayout layout,
+                                     unsigned queue_mask)
 {
        return image->surface.htile_size &&
               (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
-               layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
+               layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
+              queue_mask == (1u << RADV_QUEUE_GENERAL);
 }
 
 bool radv_layout_can_fast_clear(const struct radv_image *image,

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 18b4ca9ba2b4af555558fe0f98f63b39626264b3..6b91d17402023632efa5a1f8de92e5ea452376cf 100644 (file)
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -540,10 +540,14 @@ create_depthstencil_pipeline(struct radv_device *device,
        return result;
 }
 
-static bool depth_view_can_fast_clear(const struct radv_image_view *iview,
+static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer,
+                                     const struct radv_image_view *iview,
                                      VkImageLayout layout,
                                      const VkClearRect *clear_rect)
 {
+       uint32_t queue_mask = radv_image_queue_family_mask(iview->image,
+                                                          cmd_buffer->queue_family_index,
+                                                          cmd_buffer->queue_family_index);
        if (clear_rect->rect.offset.x || clear_rect->rect.offset.y ||
            clear_rect->rect.extent.width != iview->extent.width ||
            clear_rect->rect.extent.height != iview->extent.height)
@@ -551,14 +555,15 @@ static bool depth_view_can_fast_clear(const struct radv_image_view *iview,
        if (iview->image->surface.htile_size &&
            iview->base_mip == 0 &&
            iview->base_layer == 0 &&
-           radv_layout_is_htile_compressed(iview->image, layout) &&
+           radv_layout_is_htile_compressed(iview->image, layout, queue_mask) &&
            !radv_image_extent_compare(iview->image, &iview->extent))
                return true;
        return false;
 }
 
 static struct radv_pipeline *
-pick_depthstencil_pipeline(struct radv_meta_state *meta_state,
+pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
+                          struct radv_meta_state *meta_state,
                           const struct radv_image_view *iview,
                           int samples_log2,
                           VkImageAspectFlags aspects,
@@ -566,7 +571,7 @@ pick_depthstencil_pipeline(struct radv_meta_state *meta_state,
                           const VkClearRect *clear_rect,
                           VkClearDepthStencilValue clear_value)
 {
-       bool fast = depth_view_can_fast_clear(iview, layout, clear_rect);
+       bool fast = depth_view_can_fast_clear(cmd_buffer, iview, layout, clear_rect);
        int index = DEPTH_CLEAR_SLOW;
 
        if (fast) {
@@ -622,7 +627,8 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
                                                  clear_value.stencil);
        }
 
-       struct radv_pipeline *pipeline = pick_depthstencil_pipeline(meta_state,
+       struct radv_pipeline *pipeline = pick_depthstencil_pipeline(cmd_buffer,
+                                                                   meta_state,
                                                                    iview,
                                                                    samples_log2,
                                                                    aspects,
@@ -634,7 +640,7 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
                                           radv_pipeline_to_handle(pipeline));
        }
 
-       if (depth_view_can_fast_clear(iview, subpass->depth_stencil_attachment.layout, clear_rect))
+       if (depth_view_can_fast_clear(cmd_buffer, iview, subpass->depth_stencil_attachment.layout, clear_rect))
                radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects);
 
        radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index f9049802939b618115eaf8fcb4d8400db5c50be0..a6db5cd4ae0e38621ae63bf54c3f0da76dbdf9e4 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1189,7 +1189,8 @@ struct radv_image {
 /* Whether the image has a htile that is known consistent with the contents of
  * the image. */
 bool radv_layout_has_htile(const struct radv_image *image,
-                           VkImageLayout layout);
+                           VkImageLayout layout,
+                           unsigned queue_mask);
 
 /* Whether the image has a htile  that is known consistent with the contents of
  * the image and is allowed to be in compressed form.
@@ -1198,7 +1199,8 @@ bool radv_layout_has_htile(const struct radv_image *image,
  * correct results.
  */
 bool radv_layout_is_htile_compressed(const struct radv_image *image,
-                                     VkImageLayout layout);
+                                     VkImageLayout layout,
+                                     unsigned queue_mask);
 
 bool radv_layout_can_fast_clear(const struct radv_image *image,
                                VkImageLayout layout,