void
ilo_3d_own_render_ring(struct ilo_3d *hw3d)
{
- ilo_cp_set_ring(hw3d->cp, ILO_CP_RING_RENDER);
+ ilo_cp_set_ring(hw3d->cp, INTEL_RING_RENDER);
if (ilo_cp_set_owner(hw3d->cp, &hw3d->owner, hw3d->owner_reserve))
ilo_3d_resume_queries(hw3d);
struct ilo_context *ilo = ilo_context(pipe);
struct ilo_3d *hw3d = ilo->hw3d;
- if (ilo->cp->ring != ILO_CP_RING_RENDER)
+ if (ilo->cp->ring != INTEL_RING_RENDER)
return;
ilo_3d_pipeline_emit_flush(hw3d->pipeline);
uint32_t swctrl;
/* change ring */
- ilo_cp_set_ring(ilo->cp, ILO_CP_RING_BLT);
+ ilo_cp_set_ring(ilo->cp, INTEL_RING_BLT);
ilo_cp_set_owner(ilo->cp, NULL, 0);
/* check aperture space */
int devid;
int max_batch_size;
bool has_llc;
- bool has_gen7_sol_reset;
bool has_address_swizzling;
bool has_timestamp;
+ bool has_gen7_sol_reset;
int gen;
int gt;
ilo_cp_exec_bo(struct ilo_cp *cp)
{
const bool do_exec = !(ilo_debug & ILO_DEBUG_NOHW);
- unsigned long flags;
int err;
- switch (cp->ring) {
- case ILO_CP_RING_RENDER:
- flags = INTEL_EXEC_RENDER;
- break;
- case ILO_CP_RING_BLT:
- flags = INTEL_EXEC_BLT;
- break;
- default:
- assert(!"unknown cp ring");
- flags = 0;
- break;
- }
-
- flags |= cp->one_off_flags;
-
if (likely(do_exec)) {
- err = intel_winsys_submit_bo(cp->winsys,
- cp->bo, cp->used * 4, cp->render_ctx, flags);
+ err = intel_winsys_submit_bo(cp->winsys, cp->ring,
+ cp->bo, cp->used * 4, cp->render_ctx, cp->one_off_flags);
}
else {
err = 0;
cp->winsys = winsys;
cp->render_ctx = intel_winsys_create_context(winsys);
- cp->ring = ILO_CP_RING_RENDER;
+ cp->ring = INTEL_RING_RENDER;
cp->no_implicit_flush = false;
cp->bo_size = size;
struct ilo_cp;
-enum ilo_cp_ring {
- ILO_CP_RING_RENDER,
- ILO_CP_RING_BLT,
-
- ILO_CP_RING_COUNT,
-};
-
typedef void (*ilo_cp_callback)(struct ilo_cp *cp, void *data);
struct ilo_cp_owner {
const struct ilo_cp_owner *owner;
int owner_reserve;
- enum ilo_cp_ring ring;
+ enum intel_ring_type ring;
bool no_implicit_flush;
unsigned one_off_flags;
{
if (ilo_debug & ILO_DEBUG_FLUSH) {
ilo_printf("cp flushed for %s with %d+%d DWords (%.1f%%) because of %s\n",
- (cp->ring == ILO_CP_RING_RENDER) ? "render" : "blt",
+ (cp->ring == INTEL_RING_RENDER) ? "render" : "other",
cp->used, cp->stolen,
(float) (100 * (cp->used + cp->stolen)) / cp->bo_size,
reason);
* Set the ring buffer.
*/
static inline void
-ilo_cp_set_ring(struct ilo_cp *cp, enum ilo_cp_ring ring)
+ilo_cp_set_ring(struct ilo_cp *cp, enum intel_ring_type ring)
{
if (cp->ring != ring) {
ilo_cp_implicit_flush(cp);
dev->devid = info->devid;
dev->max_batch_size = info->max_batch_size;
dev->has_llc = info->has_llc;
- dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
dev->has_address_swizzling = info->has_address_swizzling;
dev->has_timestamp = info->has_timestamp;
+ dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
/*
* From the Sandy Bridge PRM, volume 4 part 2, page 18:
get_param(winsys, I915_PARAM_HAS_LLC, &val);
info->has_llc = val;
+ info->has_address_swizzling = test_address_swizzling(winsys);
/* test TIMESTAMP read */
info->has_timestamp = test_reg_read(winsys, 0x2358);
get_param(winsys, I915_PARAM_HAS_GEN7_SOL_RESET, &val);
info->has_gen7_sol_reset = val;
- info->has_address_swizzling = test_address_swizzling(winsys);
-
return true;
}
int
intel_winsys_submit_bo(struct intel_winsys *winsys,
+ enum intel_ring_type ring,
struct intel_bo *bo, int used,
struct intel_context *ctx,
unsigned long flags)
{
+ const unsigned long exec_flags = (unsigned long) ring | flags;
+
/* logical contexts are only available for the render ring */
- if ((flags & 0x7) > INTEL_EXEC_RENDER)
+ if (ring != INTEL_RING_RENDER)
ctx = NULL;
if (ctx) {
return drm_intel_gem_bo_context_exec(gem_bo(bo),
- (drm_intel_context *) ctx, used, flags);
+ (drm_intel_context *) ctx, used, exec_flags);
}
else {
return drm_intel_bo_mrb_exec(gem_bo(bo),
- used, NULL, 0, 0, flags);
+ used, NULL, 0, 0, exec_flags);
}
}
#include "pipe/p_compiler.h"
/* this is compatible with i915_drm.h's definitions */
-enum intel_exec_flag {
- /* bits[2:0]: ring type */
- INTEL_EXEC_DEFAULT = 0 << 0,
- INTEL_EXEC_RENDER = 1 << 0,
- INTEL_EXEC_BSD = 2 << 0,
- INTEL_EXEC_BLT = 3 << 0,
-
- /* bits[7:6]: constant buffer addressing mode */
+enum intel_ring_type {
+ INTEL_RING_RENDER = 1,
+ INTEL_RING_BSD = 2,
+ INTEL_RING_BLT = 3,
+ INTEL_RING_VEBOX = 4,
+};
- /* bits[8]: reset SO write offset register on GEN7+ */
+/* this is compatible with i915_drm.h's definitions */
+enum intel_exec_flag {
INTEL_EXEC_GEN7_SOL_RESET = 1 << 8,
};
int max_batch_size;
bool has_llc;
- bool has_gen7_sol_reset;
bool has_address_swizzling;
/* valid registers for intel_winsys_read_reg() */
bool has_timestamp;
+
+ /* valid flags for intel_winsys_submit_bo() */
+ bool has_gen7_sol_reset;
};
struct intel_winsys *
*/
int
intel_winsys_submit_bo(struct intel_winsys *winsys,
+ enum intel_ring_type ring,
struct intel_bo *bo, int used,
struct intel_context *ctx,
unsigned long flags);