[AArch64]Add vec_shr pattern for 64-bit vectors using ush{l,r}; enable tests.

gcc/:

	* config/aarch64/aarch64-simd.md (vec_shr<mode>): New.

gcc/testsuite/:

	* lib/target-supports.exp (check_effective_target_whole_vector_shift):
	Add aarch64{,_be}.

From-SVN: r218022

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f1171a7d7cb30fcec0ea64acc226119bc3c89dfe..ee51e9bb72de3cb735c83ab52e366aff3feab76e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2014-11-24  Alan Lawrence  <alan.lawrence@arm.com>
+
+       * config/aarch64/aarch64-simd.md (vec_shr<mode>): New.
+
 2014-11-24  Alan Lawrence  <alan.lawrence@arm.com>
 
        * config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args):

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index eed01cf7754c603814cd623bf935e13ae27c84c5..8e31456381f4324fe64a88a289ce6ec65d6a9e92 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -795,6 +795,21 @@
   }
 )
 
+;; For 64-bit modes we use ushl/r, as this does not require a SIMD zero.
+(define_insn "vec_shr_<mode>"
+  [(set (match_operand:VD 0 "register_operand" "=w")
+        (lshiftrt:VD (match_operand:VD 1 "register_operand" "w")
+                    (match_operand:SI 2 "immediate_operand" "i")))]
+  "TARGET_SIMD"
+  {
+    if (BYTES_BIG_ENDIAN)
+      return "ushl %d0, %d1, %2";
+    else
+      return "ushr %d0, %d1, %2";
+  }
+  [(set_attr "type" "neon_shift_imm")]
+)
+
 (define_insn "aarch64_simd_vec_setv2di"
   [(set (match_operand:V2DI 0 "register_operand" "=w,w")
         (vec_merge:V2DI

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7db895bd2a227073191e292982fbea6d67962f13..e67389395c2a351e732c6cb8c8ff03e31d19d584 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2014-11-24  Alan Lawrence  <alan.lawrence@arm.com>
+
+        * lib/target-supports.exp (check_effective_target_whole_vector_shift):
+       Add aarch64{,_be}.
+
 2014-11-24  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/63679

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 02b2b778418ee9ceb9c4c0526f5d37f80dc70749..ac04d95f7c5131b3a7f3bb68d8ba01b915aa050a 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3399,6 +3399,7 @@ proc check_effective_target_vect_shift { } {
 proc check_effective_target_whole_vector_shift { } {
     if { [istarget i?86-*-*] || [istarget x86_64-*-*]
         || [istarget ia64-*-*]
+        || [istarget aarch64*-*-*]
         || ([check_effective_target_arm32]
             && [check_effective_target_arm_little_endian])
         || ([istarget mips*-*-*]