I had previously considered that unsafe.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
const uint8_t *ptr, unsigned size,
uint32_t *const_offset)
{
- if (R600_BIG_ENDIAN) {
+ if (SI_BIG_ENDIAN) {
uint32_t *tmpPtr;
unsigned i;
/* Count in framebuffer cache flushes at the end of CS. */
num_dw += ctx->atoms.cache_flush->num_dw;
-#if R600_TRACE_CS
+#if SI_TRACE_CS
if (ctx->screen->trace_bo) {
- num_dw += R600_TRACE_CS_DWORDS;
+ num_dw += SI_TRACE_CS_DWORDS;
}
#endif
/* force to keep tiling flags */
flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
-#if R600_TRACE_CS
+#if SI_TRACE_CS
if (ctx->screen->trace_bo) {
struct si_screen *rscreen = ctx->screen;
unsigned i;
/* Flush the CS. */
ctx->b.ws->cs_flush(ctx->b.rings.gfx.cs, flags, 0);
-#if R600_TRACE_CS
+#if SI_TRACE_CS
if (ctx->screen->trace_bo) {
struct si_screen *rscreen = ctx->screen;
unsigned i;
}
}
-#if R600_TRACE_CS
+#if SI_TRACE_CS
void si_trace_emit(struct si_context *rctx)
{
struct si_screen *rscreen = rctx->screen;
r600_common_screen_cleanup(&rscreen->b);
-#if R600_TRACE_CS
+#if SI_TRACE_CS
if (rscreen->trace_bo) {
rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
-#if R600_TRACE_CS
+#if SI_TRACE_CS
rscreen->cs_count = 0;
if (rscreen->info.drm_minor >= 28) {
rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->screen,
#include "si_state.h"
#ifdef PIPE_ARCH_BIG_ENDIAN
-#define R600_BIG_ENDIAN 1
+#define SI_BIG_ENDIAN 1
#else
-#define R600_BIG_ENDIAN 0
+#define SI_BIG_ENDIAN 0
#endif
-#define R600_TRACE_CS 0
-#define R600_TRACE_CS_DWORDS 6
+#define SI_TRACE_CS 0
+#define SI_TRACE_CS_DWORDS 6
#define SI_MAX_DRAW_CS_DWORDS 18
struct si_screen {
struct r600_common_screen b;
-#if R600_TRACE_CS
+#if SI_TRACE_CS
struct r600_resource *trace_bo;
uint32_t *trace_ptr;
unsigned cs_count;
struct pipe_index_buffer *ib,
unsigned count);
-#if R600_TRACE_CS
+#if SI_TRACE_CS
void si_trace_emit(struct si_context *rctx);
#endif
continue;
count += state->ndw;
-#if R600_TRACE_CS
+#if SI_TRACE_CS
/* for tracing each states */
if (rctx->screen->trace_bo) {
- count += R600_TRACE_CS_DWORDS;
+ count += SI_TRACE_CS_DWORDS;
}
#endif
}
cs->cdw += state->ndw;
-#if R600_TRACE_CS
+#if SI_TRACE_CS
if (rctx->screen->trace_bo) {
r600_trace_emit(rctx);
}
}
ptr = (uint32_t*)rctx->b.ws->buffer_map(shader->bo->cs_buf, rctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
- if (0 /*R600_BIG_ENDIAN*/) {
+ if (0 /*SI_BIG_ENDIAN*/) {
for (i = 0; i < binary.code_size / 4; ++i) {
ptr[i] = util_bswap32(*(uint32_t*)(binary.code + i*4));
}
static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
{
- if (R600_BIG_ENDIAN) {
+ if (SI_BIG_ENDIAN) {
switch(colorformat) {
/* 8-bit buffers. */
case V_028C70_COLOR_8:
/* draw packet */
si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
if (ib->index_size == 4) {
- si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
+ si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN ?
V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
} else {
- si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
+ si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ?
V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
}
si_pm4_cmd_end(pm4, rctx->predicate_drawing);
si_pm4_emit_dirty(rctx);
rctx->pm4_dirty_cdwords = 0;
-#if R600_TRACE_CS
+#if SI_TRACE_CS
if (rctx->screen->trace_bo) {
r600_trace_emit(rctx);
}