RISC-V: Add Sign/Zero extend patterns for PIC loads

Loads on RISC-V are sign-extending by default, but we weren't telling
GCC this in our PIC load patterns.  This corrects the problem, and adds
a zero-extending pattern as well.

gcc/ChangeLog

2017-10-25  Palmer Dabbelt  <palmer@dabbelt.com>

       * config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define.
       * config/riscv/pic.md (local_pic_load): Rename to local_pic_load_s,
       mark as a sign-extending load.
       (local_pic_load_u): Define.

From-SVN: r254092

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 796a7e8cee9384823cd1500724f26f0288f85e99..5e297fb8b0fdf396a6b5f69b91ea828bff5bc26d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2017-10-25  Palmer Dabbelt  <palmer@dabbelt.com>
+
+       * config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define.
+       * config/riscv/pic.md (local_pic_load): Rename to local_pic_load_s,
+       mark as a sign-extending load.
+       (local_pic_load_u): Define.
+
 2017-10-25  Eric Botcazou  <ebotcazou@adacore.com>
 
        PR middle-end/82062

diff --git a/gcc/config/riscv/pic.md b/gcc/config/riscv/pic.md
index 6a29ead32d363ec540e2cda206971e97ddd2eb31..03b8f9bc669e826d31abc0ffcf08a261d9219880 100644 (file)
--- a/gcc/config/riscv/pic.md
+++ b/gcc/config/riscv/pic.md
@@ -22,13 +22,20 @@
 ;; Simplify PIC loads to static variables.
 ;; These should go away once we figure out how to emit auipc discretely.
 
-(define_insn "*local_pic_load<mode>"
+(define_insn "*local_pic_load_s<mode>"
   [(set (match_operand:ANYI 0 "register_operand" "=r")
-       (mem:ANYI (match_operand 1 "absolute_symbolic_operand" "")))]
+       (sign_extend:ANYI (mem:ANYI (match_operand 1 "absolute_symbolic_operand" ""))))]
   "USE_LOAD_ADDRESS_MACRO (operands[1])"
   "<load>\t%0,%1"
   [(set (attr "length") (const_int 8))])
 
+(define_insn "*local_pic_load_u<mode>"
+  [(set (match_operand:ZERO_EXTEND_LOAD 0 "register_operand" "=r")
+       (zero_extend:ZERO_EXTEND_LOAD (mem:ZERO_EXTEND_LOAD (match_operand 1 "absolute_symbolic_operand" ""))))]
+  "USE_LOAD_ADDRESS_MACRO (operands[1])"
+  "<load>u\t%0,%1"
+  [(set (attr "length") (const_int 8))])
+
 (define_insn "*local_pic_load<mode>"
   [(set (match_operand:ANYF 0 "register_operand" "=f")
        (mem:ANYF (match_operand 1 "absolute_symbolic_operand" "")))

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index fd9236c7c170c185484fd80fb8c47084989cecd6..9f056bbcda4fe9bc07a24b23c6a5e6cf9c6a013c 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -259,6 +259,9 @@
 ;; Iterator for QImode extension patterns.
 (define_mode_iterator SUPERQI [HI SI (DI "TARGET_64BIT")])
 
+;; Iterator for extending loads.
+(define_mode_iterator ZERO_EXTEND_LOAD [QI HI (SI "TARGET_64BIT")])
+
 ;; Iterator for hardware integer modes narrower than XLEN.
 (define_mode_iterator SUBX [QI HI (SI "TARGET_64BIT")])