Add DSP_{A,B}_SIGNEDONLY macro

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 6f2281c0ae3627dffaea52b385a85e7cca1490ac..258ddf021344914159c63c120e8b0e0dc88cc01c 100644 (file)
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -3,24 +3,25 @@
 // revised by Andre DeHon\r
 // further revised by David Shah\r
 `ifndef DSP_A_MAXWIDTH\r
-`define DSP_A_MAXWIDTH 18\r
+$error("Macro DSP_A_MAXWIDTH must be defined");\r
 `endif\r
-`ifndef DSP_A_MAXWIDTH\r
-`define DSP_B_MAXWIDTH 25\r
+`ifndef DSP_A_SIGNEDONLY\r
+`define DSP_A_SIGNEDONLY 0\r
 `endif\r
-\r
-`ifndef ADDER_MINWIDTH\r
-`define ADDER_MINWIDTH AAA\r
+`ifndef DSP_B_MAXWIDTH\r
+$error("Macro DSP_B_MAXWIDTH must be defined");\r
+`endif\r
+`ifndef DSP_B_SIGNEDONLY\r
+`define DSP_B_SIGNEDONLY 0\r
 `endif\r
 \r
 `ifndef DSP_NAME\r
-`define DSP_NAME M18x25\r
+$error("Macro DSP_NAME must be defined");\r
 `endif\r
 \r
 `define MAX(a,b) (a > b ? a : b)\r
 `define MIN(a,b) (a < b ? a : b)\r
 \r
-(* techmap_celltype = "$mul" *)\r
 module \$mul (A, B, Y); \r
        parameter A_SIGNED = 0;\r
        parameter B_SIGNED = 0;\r
@@ -33,14 +34,42 @@ module \$mul (A, B, Y);
        output [Y_WIDTH-1:0] Y;\r
 \r
        generate\r
-               if (A_WIDTH >= B_WIDTH)\r
+        if (`DSP_A_SIGNEDONLY && !A_SIGNED) begin\r
+            wire dummy;\r
+                       \$mul #(\r
+                               .A_SIGNED(1),\r
+                               .B_SIGNED(B_SIGNED),\r
+                               .A_WIDTH(A_WIDTH+1),\r
+                               .B_WIDTH(B_WIDTH),\r
+                               .Y_WIDTH(Y_WIDTH+1)\r
+                       ) _TECHMAP_REPLACE_ (\r
+                               .A({1'b0, A}),\r
+                               .B(B),\r
+                               .Y({dummy, Y})\r
+                       );\r
+        end\r
+        else if (`DSP_B_SIGNEDONLY && !B_SIGNED) begin\r
+            wire dummy;\r
+                       \$mul #(\r
+                               .A_SIGNED(A_SIGNED),\r
+                               .B_SIGNED(1),\r
+                               .A_WIDTH(A_WIDTH),\r
+                               .B_WIDTH(B_WIDTH+1),\r
+                               .Y_WIDTH(Y_WIDTH+1)\r
+                       ) _TECHMAP_REPLACE_ (\r
+                               .A(A),\r
+                               .B({1'b0, B}),\r
+                               .Y({dummy, Y})\r
+                       );\r
+        end\r
+               else if (A_WIDTH >= B_WIDTH)\r
                        \$__mul_gen #(\r
                                .A_SIGNED(A_SIGNED),\r
                                .B_SIGNED(B_SIGNED),\r
                                .A_WIDTH(A_WIDTH),\r
                                .B_WIDTH(B_WIDTH),\r
                                .Y_WIDTH(Y_WIDTH)\r
-                       ) mul_slice (\r
+                       ) _TECHMAP_REPLACE_ (\r
                                .A(A),\r
                                .B(B),\r
                                .Y(Y)\r
@@ -52,7 +81,7 @@ module \$mul (A, B, Y);
                                .A_WIDTH(B_WIDTH),\r
                                .B_WIDTH(A_WIDTH),\r
                                .Y_WIDTH(Y_WIDTH)\r
-                       ) mul_slice (\r
+                       ) _TECHMAP_REPLACE_ (\r
                                .A(B),\r
                                .B(A),\r
                                .Y(Y)\r