add out2, out, 0
# set Vector Length
- setvl 0, 0, 7, 0, 1, 1 # setvli MVL=8, VL=8
+ setvl 0, 0, 7, 1, 1, 0# setvli MVL=8, VL=8
addi win2, win, 124 # w2 = window + 31
lfiwax sum, 0, 5 # sum = *dither_state
SVSTATE[0:6] <- MVL
SVSTATE[7:13] <- VL
if _RT != 0b00000 then
- GPR(_RT) <- [0]*57 || VL
+ GPR(_RT) <- [0]*57 || VL
MSR[6] <- vf
Special Registers Altered:
SVM-Form
-* svshape SVxd, SVyd, SVzd, SVRM
+* svshape SVxd, SVyd, SVzd, SVRM, vf
Pseudo-code:
+ # for convenience, VL to be calculated and stored in SVSTATE
+ vlen <- [0] * 7
+ SVSTATE[0:31] <- [0] * 32
# clear out all SVSHAPEs
SVSHAPE0[0:31] <- [0] * 32
SVSHAPE1[0:31] <- [0] * 32
SVSHAPE2[0:31] <- [0] * 32
SVSHAPE3[0:31] <- [0] * 32
# set schedule up for multiply
- if (SVRM = 0b00000) then
+ if (SVRM = 0b0000) then
+ # VL in Matrix Multiply is xd*yd*zd
+ n <- (0b00 || SVxd) * (0b00 || SVyd) * (0b00 || SVzd)
+ vlen[0:6] <- n[14:20]
# set up template in SVSHAPE0, then copy to 1-3
SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim
SVSHAPE0[6:11] <- (0b0 || SVyd) # ydim
SVSHAPE2[18:20] <- 0b001 # permute x,z,y
SVSHAPE2[28:29] <- 0b11 # skip y
# set schedule up for butterfly
- if (SVRM = 0b00001) then
+ if (SVRM = 0b0001) then
+ # calculate O(N log2 N)
+ n <- [0] * 3
+ do while n < 5
+ if SVxd[4-n] = 0 then
+ leave
+ n <- n + 1
+ n <- ((0b0 || SVxd) + 1) * n
+ vlen[0:6] <- n[1:7]
# set up template in SVSHAPE0, then copy to 1-3
# for FRA and FRT
SVSHAPE0[0:5] <- (0b0 || SVxd) # xdim
SVSHAPE1[28:29] <- 0b01 # j+halfstep schedule
# FRC (coefficients)
SVSHAPE2[28:29] <- 0b10 # k schedule
+ # set VL, MVL and MSR Vertical-First
+ SVSTATE[0:6] <- vlen
+ SVSTATE[7:13] <- vlen
+ MSR[6] <- vf
Special Registers Altered:
# 1.6.28 SVL-FORM
|0 |6 |11 |16 |23 |24 |25 |26 |31 |
- | PO | RT | RA | SVi |vf |vs |ms | XO |Rc |
+ | PO | RT | RA | SVi |ms |vs |vf | XO |Rc |
# 1.6.29 SVC-FORM
|0 |6 |9 |11 |
| PO | RS | RA | RC | SVDS | XO |
# 1.6.33 SVM-FORM
- |0 |6 |11 |16 |21 |26 |31 |
- | PO | SVxd | SVyd | SVzd | SVRM | XO | / |
+ |0 |6 |11 |16 |21 |25 |26 |31 |
+ | PO | SVxd | SVyd | SVzd | SVRM |vf | XO | / |
# 1.6.34 SVRM-FORM
|0 |6 |11 |13 |15 |17 |19 |21 |26 |31 |
Field used in X-form instructions to specify a sub-
set of storage accesses.
Formats: X
- ms (25)
+ ms (23)
Field used in Simple-V to specify whether MVL is to be set
Formats: SVL
NB (16:20)
SVme (6:10)
Simple-V "REMAP" map-enable bits (0-4)
Formats: SVRM
- SVRM (21:25)
+ SVRM (21:24)
Simple-V "REMAP" Mode
Formats: SVM
SVxd (6:10)
VRT (6:10)
Field used to specify a VR to be used as a target.
Formats: DS, VA, VC, VX, X
- vf (23)
+ vf (25)
Field used in Simple-V to specify whether "Vertical" Mode is set
- Formats: SVL
+ Formats: SVL, SVM
vs (24)
Field used in Simple-V to specify whether VL is to be set
Formats: SVL
self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
def test_sv_remap_fpmadds_fft(self):
- """>>> lst = ["svshape 8, 1, 1, 1",
+ """>>> lst = ["svshape 8, 1, 1, 1, 0",
"svremap 31, 1, 0, 2, 0, 1",
"sv.ffmadds 2.v, 2.v, 2.v, 10.v"
]
SVP64 "REMAP" in Butterfly Mode is applied to a twin +/- FMAC
(3 inputs, 2 outputs)
"""
- lst = SVP64Asm( ["svshape 8, 1, 1, 1",
+ lst = SVP64Asm( ["svshape 8, 1, 1, 1, 0",
"svremap 31, 1, 0, 2, 0, 1",
"sv.ffmadds 0.v, 0.v, 0.v, 8.v"
])
for i, a in enumerate(av):
fprs[i+0] = fp64toselectable(a)
- # set total. err don't know how to calculate how many there are...
- # do it manually for now
- VL = 0
- size = 2
- n = len(av)
- while size <= n:
- halfsize = size // 2
- tablestep = n // size
- for i in range(0, n, size):
- for j in range(i, i + halfsize):
- VL += 1
- size *= 2
-
- # SVSTATE (calculated VL)
- svstate = SVP64State()
- svstate.vl[0:7] = VL # VL
- svstate.maxvl[0:7] = VL # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
-
with Program(lst, bigendian=False) as program:
- sim = self.run_tst_program(program, svstate=svstate,
- initial_fprs=fprs)
+ sim = self.run_tst_program(program, initial_fprs=fprs)
print ("spr svshape0", sim.spr['SVSHAPE0'])
print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz)
print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz)
self.assertTrue(err < 1e-7)
def test_sv_remap_fpmadds_fft_svstep(self):
- """>>> lst = SVP64Asm( ["setvl 0, 0, 11, 1, 1, 1",
- "svshape 8, 1, 1, 1",
+ """>>> lst = SVP64Asm( [
+ "svshape 8, 1, 1, 1, 1",
"svremap 31, 1, 0, 2, 0, 1",
"sv.ffmadds 0.v, 0.v, 0.v, 8.v",
"setvl. 0, 0, 0, 1, 0, 0",
SVP64 "REMAP" in Butterfly Mode is applied to a twin +/- FMAC
(3 inputs, 2 outputs)
"""
- lst = SVP64Asm( ["setvl 0, 0, 11, 1, 1, 1",
- "svshape 8, 1, 1, 1",
+ lst = SVP64Asm( [
+ "svshape 8, 1, 1, 1, 1",
"svremap 31, 1, 0, 2, 0, 1",
"sv.ffmadds 0.v, 0.v, 0.v, 8.v",
"setvl. 0, 0, 0, 1, 0, 0",
vec[jl] = temp2 + temp1
"""
lst = SVP64Asm( ["setvl 0, 0, 11, 1, 1, 1",
- "svshape 8, 1, 1, 1",
+ "svshape 8, 1, 1, 1, 1",
# tpre
"svremap 31, 1, 0, 2, 0, 1",
"sv.fmuls 24, 0.v, 16.v",
- "svshape 8, 1, 1, 1",
"svremap 31, 1, 0, 2, 0, 1",
"sv.fmuls 25, 8.v, 20.v",
"fadds 24, 24, 25",
# tpim
"svremap 31, 1, 0, 2, 0, 1",
"sv.fmuls 26, 0.v, 20.v",
- "svshape 8, 1, 1, 1",
+ "svremap 31, 1, 0, 2, 0, 1",
"sv.fmuls 26, 8.v, 16.v",
"fsubs 26, 26, 27",
# vec_r jh/jl
self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
def test_sv_remap1(self):
- """>>> lst = ["svshape 2, 2, 3, 0",
+ """>>> lst = ["svshape 2, 2, 3, 0, 0",
"svremap 31, 1, 2, 3, 0, 0",
"sv.fmadds 0.v, 8.v, 16.v, 0.v"
]
REMAP fmadds FRT, FRA, FRC, FRB
"""
- lst = SVP64Asm(["svshape 2, 2, 3, 0",
+ lst = SVP64Asm(["svshape 2, 2, 3, 0, 0",
"svremap 31, 1, 2, 3, 0, 0",
"sv.fmadds 0.v, 16.v, 32.v, 0.v"
])
# self.assertEqual(sim.fpr(i+6), u)
def test_sv_remap2(self):
- """>>> lst = ["svshape 5, 4, 3, 0",
+ """>>> lst = ["svshape 5, 4, 3, 0, 0",
"svremap 31, 1, 2, 3, 0, 0",
"sv.fmadds 0.v, 8.v, 16.v, 0.v"
]
REMAP fmadds FRT, FRA, FRC, FRB
"""
- lst = SVP64Asm(["svshape 4, 3, 3, 0",
+ lst = SVP64Asm(["svshape 4, 3, 3, 0, 0",
"svremap 31, 1, 2, 3, 0, 0",
"sv.fmadds 0.v, 16.v, 32.v, 0.v"
])
xdim2 = len(Y[0])
ydim2 = len(Y)
- VL = ydim2 * xdim2 * ydim1
print ("xdim2 ydim1 ydim2", xdim2, ydim1, ydim2)
xf = reduce(operator.add, X)
#print ("FFT", i, "in", a, b, "coeff", c, "mul",
# mul, "res", t, u)
- # SVSTATE (in this case, VL=12, to cover all of matrix)
- svstate = SVP64State()
- svstate.vl[0:7] = VL # VL
- svstate.maxvl[0:7] = VL # MAXVL
- print ("SVSTATE", bin(svstate.spr.asint()))
-
with Program(lst, bigendian=False) as program:
- sim = self.run_tst_program(program, svstate=svstate,
- initial_fprs=fprs)
+ sim = self.run_tst_program(program, initial_fprs=fprs)
print ("spr svshape0", sim.spr['SVSHAPE0'])
print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz)
print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz)
insn |= fields[0] << (31-10) # RT , bits 6-10
insn |= fields[1] << (31-15) # RA , bits 11-15
insn |= fields[2] << (31-22) # SVi , bits 16-22
- insn |= fields[3] << (31-23) # vf , bit 23
+ insn |= fields[3] << (31-25) # ms , bit 25
insn |= fields[4] << (31-24) # vs , bit 24
- insn |= fields[5] << (31-25) # ms , bit 25
+ insn |= fields[5] << (31-23) # vf , bit 23
insn |= 0b00000 << (31-30) # XO , bits 26..30
if opcode == 'setvl.':
insn |= 1 << (31-31) # Rc=1 , bit 31
insn |= (fields[0]-1) << (31-10) # SVxd , bits 6-10
insn |= (fields[1]-1) << (31-15) # SVyd , bits 11-15
insn |= (fields[2]-1) << (31-20) # SVzd , bits 16-20
- insn |= (fields[3]) << (31-25) # SVRM , bits 21-25
+ insn |= (fields[3]) << (31-24) # SVRM , bits 21-24
+ insn |= (fields[4]) << (31-25) # vf , bits 25
insn |= 0b00001 << (31-30) # XO , bits 26..30
#insn &= ((1<<32)-1)
log ("svshape", bin(insn))
]
lst = [
#'sv.fmadds 0.v, 8.v, 16.v, 4.v',
- #'svshape 8, 1, 1, 1',
#'sv.ffadds 0.v, 8.v, 4.v',
- 'svremap 11, 0, 1, 2, 3, 2',
+ #'svremap 11, 0, 1, 2, 3, 2',
+ 'svshape 8, 1, 1, 1, 0',
+ 'svshape 8, 1, 1, 1, 1',
]
isa = SVP64Asm(lst, macros=macros)
print ("list", list(isa))
projects / openpower-isa.git / commitdiff