add fnabs unit test

diff --git a/openpower/isa/fpmove.mdwn b/openpower/isa/fpmove.mdwn
index 5247e834d6737dd24d9bb40e33db2cb83723039c..75d3741d4b61490bb1fc4bf1b8bfd42d27cbadc2 100644 (file)
--- a/openpower/isa/fpmove.mdwn
+++ b/openpower/isa/fpmove.mdwn
@@ -41,7 +41,7 @@ X-Form
 
 Pseudo-code:
 
-    FRT[0] <- 0b1 || FRB[1:63]
+    FRT <- 0b1 || FRB[1:63]
 
 Special Registers Altered:
 

diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index d677be4f3a2e2ec680a636e71847084cabf11cb3..3fff1dfb62eeb4979cce6c8d760bf0b550f87e6e 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -99,10 +99,14 @@ class DecoderTestCase(FHDLTestCase):
     def test_fp_abs(self):
         """>>> lst = ["fabs 3, 1",
                       "fabs 4, 2",
+                      "fnabs 5, 1",
+                      "fnabs 6, 2",
                      ]
         """
         lst = ["fabs 3, 1",
                "fabs 4, 2",
+               "fnabs 5, 1",
+               "fnabs 6, 2",
                      ]
 
         fprs = [0] * 32
@@ -111,14 +115,12 @@ class DecoderTestCase(FHDLTestCase):
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_fprs=fprs)
-            print("FPR 1", sim.fpr(1))
-            print("FPR 2", sim.fpr(2))
-            print("FPR 3", sim.fpr(3))
-            print("FPR 4", sim.fpr(4))
             self.assertEqual(sim.fpr(1), SelectableInt(0xC040266660000000, 64))
             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
             self.assertEqual(sim.fpr(3), SelectableInt(0x4040266660000000, 64))
             self.assertEqual(sim.fpr(4), SelectableInt(0x4040266660000000, 64))
+            self.assertEqual(sim.fpr(5), SelectableInt(0xC040266660000000, 64))
+            self.assertEqual(sim.fpr(6), SelectableInt(0xC040266660000000, 64))
 
     def run_tst_program(self, prog, initial_regs=None,
                               initial_mem=None,