Saves ~2KB of code.
clip.clip5.api_mode = BRW_CLIP_API_OGL;
clip.clip5.clip_mode = key->clip_mode;
- if (BRW_IS_G4X(brw))
+ if (intel->is_g4x)
clip.clip5.negative_w_clip_test = 1;
clip.clip6.clipper_viewport_state_ptr = 0;
GLboolean force_edgeflag)
{
struct brw_compile *p = &c->func;
+ struct intel_context *intel = &p->brw->intel;
struct brw_reg tmp = get_tmp(c);
GLuint i;
*/
/*
* After CLIP stage, only first 256 bits of the VUE are read
- * back on IGDNG, so needn't change it
+ * back on Ironlake, so needn't change it
*/
brw_copy_indirect_to_indirect(p, dest_ptr, v0_ptr, 1);
for (i = 0; i < c->nr_attrs; i++) {
GLuint delta = i*16 + 32;
- if (BRW_IS_IGDNG(p->brw))
+ if (intel->is_ironlake)
delta = i * 16 + 32 * 3;
if (delta == c->offset[VERT_RESULT_EDGE]) {
if (i & 1) {
GLuint delta = i*16 + 32;
- if (BRW_IS_IGDNG(p->brw))
+ if (intel->is_ironlake)
delta = i * 16 + 32 * 3;
brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0));
MIN2(ctx->Const.FragmentProgram.MaxNativeParameters,
ctx->Const.FragmentProgram.MaxEnvParams);
+ if (intel->is_ironlake || intel->is_g4x) {
+ brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_GM45;
+ brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45;
+ brw->has_surface_tile_offset = GL_TRUE;
+ brw->has_compr4 = GL_TRUE;
+ } else {
+ brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_965;
+ brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965;
+ brw->has_surface_tile_offset = GL_FALSE;
+ brw->has_compr4 = GL_FALSE;
+ }
+
+ /* WM maximum threads is number of EUs times number of threads per EU. */
+ if (intel->is_ironlake) {
+ brw->urb.size = 1024;
+ brw->vs_max_threads = 72;
+ brw->wm_max_threads = 12 * 6;
+ } else if (intel->is_g4x) {
+ brw->urb.size = 384;
+ brw->vs_max_threads = 32;
+ brw->wm_max_threads = 10 * 5;
+ } else {
+ brw->urb.size = 256;
+ brw->vs_max_threads = 16;
+ brw->wm_max_threads = 8 * 4;
+ }
+
+ if (INTEL_DEBUG & DEBUG_SINGLE_THREAD) {
+ brw->vs_max_threads = 1;
+ brw->wm_max_threads = 1;
+ }
+
brw_init_state( brw );
brw->state.dirty.mesa = ~0;
GLuint primitive;
GLboolean emit_state_always;
-
+ GLboolean has_surface_tile_offset;
+ GLboolean has_compr4;
+;
struct {
struct brw_state_flags dirty;
*/
GLuint next_free_page;
+ /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
+ uint32_t CMD_VF_STATISTICS;
+ /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
+ uint32_t CMD_PIPELINE_SELECT;
+ int vs_max_threads;
+ int wm_max_threads;
/* BRW_NEW_URB_ALLOCATIONS:
*/
GLuint clip_start;
GLuint sf_start;
GLuint cs_start;
+ GLuint size; /* Hardware URB size, in KB. */
} urb;
#include "intel_chipset.h"
-#define BRW_IS_G4X(brw) (IS_G4X((brw)->intel.intelScreen->deviceID))
-#define BRW_IS_IGDNG(brw) (IS_IGDNG((brw)->intel.intelScreen->deviceID))
-#define BRW_IS_965(brw) (!(BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)))
-#define CMD_PIPELINE_SELECT(brw) ((BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) ? CMD_PIPELINE_SELECT_GM45 : CMD_PIPELINE_SELECT_965)
-#define CMD_VF_STATISTICS(brw) ((BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) ? CMD_VF_STATISTICS_GM45 : CMD_VF_STATISTICS_965)
-#define URB_SIZES(brw) (BRW_IS_IGDNG(brw) ? 1024 : \
- (BRW_IS_G4X(brw) ? 384 : 256)) /* 512 bit units */
+#define BRW_IS_965(brw) (!(brw)->intel.is_g4x && \
+ !(brw)->intel.is_ironlake)
#endif
insn->bits3.sampler_igdng.end_of_thread = eot;
insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_SAMPLER;
insn->bits2.send_igdng.end_of_thread = eot;
- } else if (BRW_IS_G4X(brw)) {
+ } else if (intel->is_g4x) {
insn->bits3.sampler_g4x.binding_table_index = binding_table_index;
insn->bits3.sampler_g4x.sampler = sampler;
insn->bits3.sampler_g4x.msg_type = msg_type;
static GLboolean do_check_fallback(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
GLcontext *ctx = &brw->intel.ctx;
GLuint i;
}
/* _NEW_BUFFERS */
- if (IS_965(intel->intelScreen->deviceID) &&
- !IS_G4X(intel->intelScreen->deviceID)) {
+ if (!brw->has_surface_tile_offset) {
for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
{
struct intel_context *intel = &brw->intel;
struct intel_region *region = brw->state.depth_region;
- unsigned int len = (BRW_IS_G4X(brw) || intel->is_ironlake) ? 6 : 5;
+ unsigned int len = (intel->is_g4x || intel->is_ironlake) ? 6 : 5;
if (region == NULL) {
BEGIN_BATCH(len, IGNORE_CLIPRECTS);
OUT_BATCH(0);
OUT_BATCH(0);
- if (BRW_IS_G4X(brw) || intel->is_ironlake)
+ if (intel->is_g4x || intel->is_ironlake)
OUT_BATCH(0);
ADVANCE_BATCH();
((region->height - 1) << 19));
OUT_BATCH(0);
- if (BRW_IS_G4X(brw) || intel->is_ironlake)
+ if (intel->is_g4x || intel->is_ironlake)
OUT_BATCH(0);
ADVANCE_BATCH();
struct brw_pipeline_select ps;
memset(&ps, 0, sizeof(ps));
- ps.header.opcode = CMD_PIPELINE_SELECT(brw);
+ ps.header.opcode = brw->CMD_PIPELINE_SELECT;
ps.header.pipeline_select = 0;
BRW_BATCH_STRUCT(brw, &ps);
}
struct brw_vf_statistics vfs;
memset(&vfs, 0, sizeof(vfs));
- vfs.opcode = CMD_VF_STATISTICS(brw);
+ vfs.opcode = brw->CMD_VF_STATISTICS;
if (INTEL_DEBUG & DEBUG_STATS)
vfs.statistics_enable = 1;
brw->urb.sf_start = brw->urb.clip_start + brw->urb.nr_clip_entries * brw->urb.vsize;
brw->urb.cs_start = brw->urb.sf_start + brw->urb.nr_sf_entries * brw->urb.sfsize;
- return brw->urb.cs_start + brw->urb.nr_cs_entries * brw->urb.csize <= URB_SIZES(brw);
+ return brw->urb.cs_start + brw->urb.nr_cs_entries *
+ brw->urb.csize <= brw->urb.size;
}
/* Most minimal update, forces re-emit of URB fence packet after GS
brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries;
}
- } else if (BRW_IS_G4X(brw)) {
+ } else if (intel->is_g4x) {
brw->urb.nr_vs_entries = 64;
if (check_urb_layout(brw)) {
goto done;
brw->urb.clip_start,
brw->urb.sf_start,
brw->urb.cs_start,
- URB_SIZES(brw));
+ brw->urb.size);
brw->state.dirty.brw |= BRW_NEW_URB_FENCE;
}
uf.bits0.gs_fence = brw->urb.clip_start;
uf.bits0.clp_fence = brw->urb.sf_start;
uf.bits1.sf_fence = brw->urb.cs_start;
- uf.bits1.cs_fence = URB_SIZES(brw);
+ uf.bits1.cs_fence = brw->urb.size;
BRW_BATCH_STRUCT(brw, &uf);
}
struct intel_context *intel = &brw->intel;
struct brw_vs_unit_state vs;
dri_bo *bo;
- int chipset_max_threads;
memset(&vs, 0, sizeof(vs));
case 32:
break;
case 64:
- assert(BRW_IS_G4X(brw));
+ assert(intel->is_g4x);
break;
default:
assert(0);
vs.thread4.urb_entry_allocation_size = key->urb_size - 1;
- if (intel->is_ironlake)
- chipset_max_threads = 72;
- else if (BRW_IS_G4X(brw))
- chipset_max_threads = 32;
- else
- chipset_max_threads = 16;
vs.thread4.max_threads = CLAMP(key->nr_urb_entries / 2,
- 1, chipset_max_threads) - 1;
-
- if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
- vs.thread4.max_threads = 0;
+ 1, brw->vs_max_threads) - 1;
/* No samplers for ARB_vp programs:
*/
{
struct brw_compile *p = &c->func;
struct brw_context *brw = p->brw;
- struct intel_context *intel = &brw->intel;
GLuint nr = 2;
GLuint channel;
brw_push_insn_state(p);
for (channel = 0; channel < 4; channel++) {
- if (c->dispatch_width == 16 && (BRW_IS_G4X(brw) || intel->is_ironlake)) {
+ if (c->dispatch_width == 16 && brw->has_compr4) {
/* By setting the high bit of the MRF register number, we indicate
* that we want COMPR4 mode - instead of doing the usual destination
* + 1 for the second half we get destination + 4.
unsigned int curbe_offset;
unsigned int urb_size;
- unsigned int max_threads;
-
unsigned int nr_surfaces, sampler_count;
GLboolean uses_depth, computes_depth, uses_kill, is_glsl;
GLboolean polygon_stipple, stats_wm, line_stipple, offset_enable;
memset(key, 0, sizeof(*key));
- if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
- key->max_threads = 1;
- else {
- /* WM maximum threads is number of EUs times number of threads per EU. */
- if (intel->is_ironlake)
- key->max_threads = 12 * 6;
- else if (BRW_IS_G4X(brw))
- key->max_threads = 10 * 5;
- else
- key->max_threads = 8 * 4;
- }
-
/* CACHE_NEW_WM_PROG */
key->total_grf = brw->wm.prog_data->total_grf;
key->urb_entry_read_length = brw->wm.prog_data->urb_read_length;
else
wm.wm5.enable_16_pix = 1;
- wm.wm5.max_threads = key->max_threads - 1;
+ wm.wm5.max_threads = brw->wm_max_threads - 1;
wm.wm5.thread_dispatch_enable = 1; /* AKA: color_write */
wm.wm5.legacy_line_rast = 0;
wm.wm5.legacy_global_depth_bias = 0;
*/
assert(key.total_scratch <= 12 * 1024);
if (key.total_scratch) {
- GLuint total = key.total_scratch * key.max_threads;
+ GLuint total = key.total_scratch * brw->wm_max_threads;
if (brw->wm.scratch_bo && total > brw->wm.scratch_bo->size) {
dri_bo_unreference(brw->wm.scratch_bo);
surf.ss1.base_addr = key.draw_offset - tile_offset;
- assert(BRW_IS_G4X(brw) || tile_offset == 0);
- if (BRW_IS_G4X(brw)) {
+ if (brw->has_surface_tile_offset) {
if (key.tiling == I915_TILING_X) {
/* Note that the low bits of these fields are missing, so
* there's the possibility of getting in trouble.
surf.ss5.x_offset = (tile_offset % 128) / key.cpp / 4;
surf.ss5.y_offset = tile_offset / 128 / 2;
}
+ } else {
+ assert(tile_offset == 0);
}
}
if (region_bo != NULL)
if (IS_IGDNG(intel->intelScreen->deviceID)) {
intel->is_ironlake = GL_TRUE;
intel->needs_ff_sync = GL_TRUE;
+ intel->has_luminance_srgb = GL_TRUE;
+ } else if (IS_G4X(intel->intelScreen->deviceID)) {
+ intel->has_luminance_srgb = GL_TRUE;
+ intel->is_g4x = GL_TRUE;
}
/* Dri stuff */
int gen;
GLboolean needs_ff_sync;
GLboolean is_ironlake;
+ GLboolean is_g4x;
+ GLboolean has_luminance_srgb;
+
+ int urb_size;
struct intel_region *front_region;
struct intel_region *back_region;
return MESA_FORMAT_SARGB8;
case GL_SLUMINANCE_EXT:
case GL_SLUMINANCE8_EXT:
- if (IS_G4X(intel->intelScreen->deviceID))
+ if (intel->has_luminance_srgb)
return MESA_FORMAT_SL8;
else
return MESA_FORMAT_SARGB8;
case GL_SLUMINANCE_ALPHA_EXT:
case GL_SLUMINANCE8_ALPHA8_EXT:
- if (IS_G4X(intel->intelScreen->deviceID))
+ if (intel->has_luminance_srgb)
return MESA_FORMAT_SLA8;
else
return MESA_FORMAT_SARGB8;
projects / mesa.git / commitdiff