AArch64 backend support for SBC instruction.

From-SVN: r196797

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d55999eec691a8a046061fb506a0bd3f59663a0f..b6ae43aa33654b9cab1ec6c62c162fbf793ba03c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-03-19  Ian Bolton  <ian.bolton@arm.com>
+
+       * config/aarch64/aarch64.md (*sub<mode>3_carryin): New pattern.
+       (*subsi3_carryin_uxtw): Likewise.
+
 2013-03-19  Ian Bolton  <ian.bolton@arm.com>
 
        * config/aarch64/aarch64.md (*ror<mode>3_insn): New pattern.

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 4358b448c6d7c32e1346730d0cd11ee6280cdd15..c99e188a7b5e47fb8e3b36ec66a5fbc786a9d025 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1790,6 +1790,34 @@
    (set_attr "mode" "SI")]
 )
 
+(define_insn "*sub<mode>3_carryin"
+  [(set
+    (match_operand:GPI 0 "register_operand" "=r")
+    (minus:GPI (minus:GPI
+               (match_operand:GPI 1 "register_operand" "r")
+               (ltu:GPI (reg:CC CC_REGNUM) (const_int 0)))
+              (match_operand:GPI 2 "register_operand" "r")))]
+   ""
+   "sbc\\t%<w>0, %<w>1, %<w>2"
+  [(set_attr "v8type" "adc")
+   (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of the above
+(define_insn "*subsi3_carryin_uxtw"
+  [(set
+    (match_operand:DI 0 "register_operand" "=r")
+    (zero_extend:DI
+     (minus:SI (minus:SI
+               (match_operand:SI 1 "register_operand" "r")
+               (ltu:SI (reg:CC CC_REGNUM) (const_int 0)))
+              (match_operand:SI 2 "register_operand" "r"))))]
+   ""
+   "sbc\\t%w0, %w1, %w2"
+  [(set_attr "v8type" "adc")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*sub_uxt<mode>_multp2"
   [(set (match_operand:GPI 0 "register_operand" "=rk")
        (minus:GPI (match_operand:GPI 4 "register_operand" "r")

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e198a6e0af2e3ec290084860606d14a52e743e72..6769ff794aa21d603b105923aa2e82ea5d0b02fb 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2013-03-19  Ian Bolton  <ian.bolton@arm.com>
+
+       * gcc.target/aarch64/sbc.c: New test.
+
 2013-03-19  Ian Bolton  <ian.bolton@arm.com>
 
        * gcc.target/aarch64/ror.c: New test.