(no commit message)

diff --git a/crypto_router_asic.mdwn b/crypto_router_asic.mdwn
index c6efce26b73148140df92c38cf1eecb00aa2f193..92c8333a3d096092447bbf77153a15286a00455c 100644 (file)
--- a/crypto_router_asic.mdwn
+++ b/crypto_router_asic.mdwn
@@ -20,17 +20,19 @@ To build the foundations of a cryptographic extension of the Power ISA, allowing
 anyone interested to build upon this effort and make an Cryptorouter FPGA or ASIC
 for oneself.
 
-# Deliverables
+# Deliverables are at top-level bugreport 589
 
-* a set of instructions suitable for crypto applications
-* documentation of said instructions
+* a set of general-purpose scalar instructions suitable for cryptographic applications
+as well as many other purposes
+* documentation of said instructions (already done, [[bitmanip]] [[bigint]])
 * reference HDL implementation of a number of them
-* additional definitions for concepts like a REMAP engine and element width
+(not possible within limited 2021-02-051 budget [[nlnet_2021_crypto_router]] )
+* additional specification and simulation for concepts like a REMAP engine and element width
 overrides which, when implemented, will allow efficient implementation of many
-fundamental crypto algorithms
+fundamental crypto algorithms. (implemented 100% in simulator, allowing 100% successful implementation of Simple-V-PowerISA assembler to be made, but limited budget of 2021-02-051 was insufficient to complete HDL implementation of REMAP and elwidths)
 * a flexible HDL platform (ls2) for implementing a System-on-Chip on an FPGA or ASIC
 
-# TODO
+## TODO
 
 Links to:
 
@@ -43,7 +45,7 @@ Links to:
 Given the work above, the information below is useful for allowing anyone
 interested to work towards building a Cryptorouter FPGA or ASIC for oneself:
 
-# Specifications
+## Specifications, 2020
 
 All of these are entirely Libre-Licensed or are to be written as Libre-Licensed:
 
@@ -67,7 +69,7 @@ All of these are entirely Libre-Licensed or are to be written as Libre-Licensed:
 
 
 
-# Example packet transfer
+## Example packet transfer
 
 * Packet comes in on RGMII port 1.  Each PHY has its own dual-ported SRAM
 * Packet is **directly** stored in internal (dual-ported SRAM) by
@@ -84,7 +86,7 @@ All of these are entirely Libre-Licensed or are to be written as Libre-Licensed:
 * Processor notifies target RGM-II PHY to activate "send" of frame out
   through target RGM-II port 2.
 
-# Testing and Verification
+## Testing and Verification
 
 We will need full HDL simulations as well as post P&R simulations.
 These may be achieved as follows: