Fix PR target/57731 PR target/57837

2013-07-25  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/19599
	PR target/57731
	PR target/57837
	* config/arm/arm.md ("*sibcall_value_insn): Replace use of
	Ss with US. Adjust output for v5 and v4t.
	(*sibcall_value_insn): Likewise and loosen predicate on
	operand0.
	* config/arm/constraints.md ("Ss"): Rename to US.

From-SVN: r201240

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fa582e306b1000282001ea69bb1d5e87d3ad7c21..87f1deb4c3f4742e78ec274a1853a426c47caffa 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2013-07-25  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+       PR target/19599
+       PR target/57731
+       PR target/57748
+       * config/arm/arm.md ("*sibcall_value_insn): Replace use of
+       Ss with US. Adjust output for v5 and v4t.
+       (*sibcall_value_insn): Likewise and loosen predicate on
+       operand0.
+       * config/arm/constraints.md ("Ss"): Rename to US.
+
 2013-07-25  Terry Guo  <terry.guo@arm.com>
 
        * config/arm/arm.c (thumb1_size_rtx_costs): Assign proper cost for

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 86e41a28854908b0176a273a6cc1f3188624b046..185037438d8ec1a5406020a466ba9c059e4333b4 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -9619,7 +9619,7 @@
 )
 
 (define_insn "*sibcall_insn"
- [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "Cs,Ss"))
+ [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "Cs, US"))
        (match_operand 1 "" ""))
   (return)
   (use (match_operand 2 "" ""))]
@@ -9630,7 +9630,7 @@
   else
     {
       if (arm_arch5 || arm_arch4t)
-       return \" bx\\t%0\\t%@ indirect register sibling call\";
+       return \" bx%?\\t%0\\t%@ indirect register sibling call\";
       else
        return \"mov%?\\t%|pc, %0\\t%@ indirect register sibling call\";
     }
@@ -9639,8 +9639,8 @@
 )
 
 (define_insn "*sibcall_value_insn"
- [(set (match_operand 0 "s_register_operand" "")
-       (call (mem:SI (match_operand:SI 1 "call_insn_operand" "Cs,Ss"))
+ [(set (match_operand 0 "" "")
+       (call (mem:SI (match_operand:SI 1 "call_insn_operand" "Cs,US"))
             (match_operand 2 "" "")))
   (return)
   (use (match_operand 3 "" ""))]
@@ -9651,7 +9651,7 @@
   else
     {
       if (arm_arch5 || arm_arch4t)
-       return \"bx\\t%1\";
+       return \"bx%?\\t%1\";
       else
        return \"mov%?\\t%|pc, %1\\t@ indirect sibling call \";
     }

diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
index e7cafe58e9c08b614e5dea155713c478917535f1..e2a3099e041ce52d5a5a9d423cd68e74ace3a53e 100644 (file)
--- a/gcc/config/arm/constraints.md
+++ b/gcc/config/arm/constraints.md
@@ -21,7 +21,7 @@
 ;; The following register constraints have been used:
 ;; - in ARM/Thumb-2 state: t, w, x, y, z
 ;; - in Thumb state: h, b
-;; - in both states: l, c, k, q
+;; - in both states: l, c, k, q, US
 ;; In ARM state, 'l' is an alias for 'r'
 ;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
 
@@ -417,6 +417,12 @@
                                                   0)
                   && GET_CODE (XEXP (op, 0)) != POST_INC")))
 
+(define_constraint "US"
+ "@internal
+  US is a symbol reference."
+ (match_code "symbol_ref")
+)
+
 ;; We used to have constraint letters for S and R in ARM state, but
 ;; all uses of these now appear to have been removed.
 
@@ -424,8 +430,3 @@
 ;; this wasn't really a valid memory constraint.  Again, all uses of
 ;; this now seem to have been removed.
 
-(define_constraint "Ss"
- "@internal
-  Ss is a symbol reference."
- (match_code "symbol_ref")
-)