added english language description for lbzsux instruction

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index 481547c9bcb626f0877d9ae57ea029e00c1826b6..7a4fe66082c712afaf9e1a29a8384e278fd1422b 100644 (file)
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -42,6 +42,7 @@ Description:
 
     Let the effective address (EA) be the sum of the contents of
     register RB shifted by (SH+1), and (RA|0).
+
     The byte in storage addressed by EA is loaded into
     RT[56:63]. RT[0:55] are set to 0.
 
@@ -62,6 +63,18 @@ Pseudo-code:
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1), and (RA).
+
+    The byte in storage addressed by EA is
+    loaded into RT[56:63] . RT[0:55] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None