Clean up config scripts to not have to worry about attaching a cache only to the...

configs/common/Simulation.py:
    Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.

    However the O3CPU must always use caches, so a check for that must still exist.

    Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU.
configs/example/fs.py:
configs/example/se.py:
    Atomic CPU now handles caches.

--HG--
extra : convert_revision : 534ded558ef96cafd76b4b5c5317bd8f4d05076e

diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index d88373d5450ac74e539167954ad515a6525439bb..f43fa9a6f9df643b3c642bb4ce2e4cc479ecaaaf 100644 (file)
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -84,10 +84,6 @@ def run(options, root, testsys, cpu_class):
             if not m5.build_env['FULL_SYSTEM']:
                 switch_cpus[i].workload = testsys.cpu[i].workload
             switch_cpus[i].clock = testsys.cpu[0].clock
-            if options.caches:
-                switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
-                                                       L1Cache(size = '64kB'))
-                switch_cpus[i].connectMemPorts(testsys.membus)
 
         root.switch_cpus = switch_cpus
         switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
@@ -107,19 +103,15 @@ def run(options, root, testsys, cpu_class):
             switch_cpus[i].clock = testsys.cpu[0].clock
             switch_cpus_1[i].clock = testsys.cpu[0].clock
 
-            if options.caches:
-                switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
-                                                       L1Cache(size = '64kB'))
-                switch_cpus[i].connectMemPorts(testsys.membus)
-            else:
+            if not options.caches:
                 # O3 CPU must have a cache to work.
                 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                                          L1Cache(size = '64kB'))
                 switch_cpus_1[i].connectMemPorts(testsys.membus)
 
 
-            root.switch_cpus = switch_cpus
-            root.switch_cpus_1 = switch_cpus_1
+            testsys.switch_cpus = switch_cpus
+            testsys.switch_cpus_1 = switch_cpus_1
             switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
             switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
 
@@ -222,5 +214,5 @@ def run(options, root, testsys, cpu_class):
 
     if exit_cause == '':
         exit_cause = exit_event.getCause()
-    print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause
+    print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause)
 

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 180cd271934c90ecd3280d73366f1e0e5e4d74d4..a9f1d579a07c3cfdc6871bdc39e72572635396f8 100644 (file)
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -95,7 +95,7 @@ test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
 np = options.num_cpus
 test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
 for i in xrange(np):
-    if options.caches and not options.standard_switch and not FutureClass:
+    if options.caches:
         test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                                 L1Cache(size = '64kB'))
     test_sys.cpu[i].connectMemPorts(test_sys.membus)

diff --git a/configs/example/se.py b/configs/example/se.py
index 0a158244fa02ae704b1892e2251d65d289d0c0a9..0944a030e8a5bd72da2ce6b8a7681f767e0a0ad6 100644 (file)
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -101,7 +101,7 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
 system.physmem.port = system.membus.port
 
 for i in xrange(np):
-    if options.caches and not options.standard_switch and not FutureClass:
+    if options.caches:
         system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                               L1Cache(size = '64kB'))
     system.cpu[i].connectMemPorts(system.membus)