fix uart selection when opening wishbone

diff --git a/miscope/host/uart2wishbone.py b/miscope/host/uart2wishbone.py
index ca4e5874f4a7a0389f32e23451d55ccd16d99f9d..df79a1a1282f415568bb1466aebd3c9db664856f 100644 (file)
--- a/miscope/host/uart2wishbone.py
+++ b/miscope/host/uart2wishbone.py
@@ -23,13 +23,13 @@ class Uart2Wishbone:
                self.uart.open()
                self.uart.flushInput()
                try:
-                       wb.regs.uart2wb_sel.write(1)
+                       self.regs.uart2wb_sel.write(1)
                except:
                        pass
                
        def close(self):
                try:
-                       wb.regs.uart2wb_sel.write(0)
+                       self.regs.uart2wb_sel.write(0)
                except:
                        pass
                self.uart.close()

diff --git a/miscope/host/vcd.py b/miscope/host/vcd.py
index 4b2bad8a442694c2c6232dfb887a68e71e82c4d4..0259e609ddd7b8dc49557cd06152c350b7cdcde9 100644 (file)
--- a/miscope/host/vcd.py
+++ b/miscope/host/vcd.py
@@ -1,7 +1,17 @@
 import sys
 import datetime
 
-from miscope.std.misc import *
+def dec2bin(d, nb=0):
+       if d=="x":
+               return "x"*nb
+       elif d==0:
+               b="0"
+       else:
+               b=""
+               while d!=0:
+                       b="01"[d&1]+b
+                       d=d>>1
+       return b.zfill(nb)
 
 def get_bits(values, width, low, high=None):
        r = []