static void evergreen_set_rat(
struct r600_pipe_compute *pipe,
- int id,
+ unsigned id,
struct r600_resource* bo,
int start,
int size)
{
struct r600_context *ctx = (struct r600_context *)ctx_;
struct r600_pipe_compute *shader = ctx->cs_shader_state.shader;
- int i;
+ unsigned i;
/* We need to reserve 9 dwords (36 bytes) for implicit kernel
* parameters.
*/
const uint *grid_layout)
{
struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
- int i;
+ unsigned i;
/* make sure that the gfx ring is only one active */
if (ctx->b.rings.dma.cs && ctx->b.rings.dma.cs->cdw) {
COMPUTE_DBG(ctx->screen, "*** evergreen_set_compute_resources: start = %u count = %u\n",
start, count);
- for (int i = 0; i < count; i++) {
+ for (unsigned i = 0; i < count; i++) {
/* The First two vertex buffers are reserved for parameters and
* global buffers. */
unsigned vtx_id = 2 + i;
struct r600_pipe_sampler_view **resource =
(struct r600_pipe_sampler_view **)views;
- for (int i = 0; i < count; i++) {
+ for (unsigned i = 0; i < count; i++) {
if (resource[i]) {
assert(i+1 < 12);
/* XXX: Implement */
/* We mark these items for promotion to the pool if they
* aren't already there */
- for (int i = 0; i < n; i++) {
+ for (unsigned i = 0; i < n; i++) {
struct compute_memory_item *item = buffers[i]->chunk;
if (!is_item_in_pool(item))
return;
}
- for (int i = 0; i < n; i++)
+ for (unsigned i = 0; i < n; i++)
{
uint32_t buffer_offset;
uint32_t handle;