+2017-12-01 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * config/rs6000/rs6000-protos.h (emit_fusion_addis): Remove last two
+ parameters from prototype.
+ * config/rs6000/rs6000.c (emit_fusion_addis): Remove last two
+ parameters. Don't print a comment.
+ (emit_fusion_gpr_load): Adjust.
+ (emit_fusion_load_store): Adjust.
+ * config/rs6000/rs6000.md (*fusion_p9_<mode>_constant): Adjust.
+ * config/rs6000/vsx.md (two peepholes): Print the "vector load fusion"
+ comment on the second line.
+
2017-12-01 Segher Boessenkool <segher@kernel.crashing.org>
PR target/43871
extern bool quad_load_store_p (rtx, rtx);
extern bool fusion_gpr_load_p (rtx, rtx, rtx, rtx);
extern void expand_fusion_gpr_load (rtx *);
-extern void emit_fusion_addis (rtx, rtx, const char *, const char *);
+extern void emit_fusion_addis (rtx, rtx);
extern void emit_fusion_load_store (rtx, rtx, rtx, const char *);
extern const char *emit_fusion_gpr_load (rtx, rtx);
extern bool fusion_p9_p (rtx, rtx, rtx, rtx);
sequence. */
void
-emit_fusion_addis (rtx target, rtx addis_value, const char *comment,
- const char *mode_name)
+emit_fusion_addis (rtx target, rtx addis_value)
{
rtx fuse_ops[10];
- char insn_template[80];
const char *addis_str = NULL;
- const char *comment_str = ASM_COMMENT_START;
-
- if (*comment_str == ' ')
- comment_str++;
/* Emit the addis instruction. */
fuse_ops[0] = target;
if (!addis_str)
fatal_insn ("Could not generate addis value for fusion", addis_value);
- sprintf (insn_template, "%s\t\t%s %s, type %s", addis_str, comment_str,
- comment, mode_name);
- output_asm_insn (insn_template, fuse_ops);
+ output_asm_insn (addis_str, fuse_ops);
}
/* Emit a D-form load or store instruction that is the second instruction
rtx addr;
rtx load_offset;
const char *load_str = NULL;
- const char *mode_name = NULL;
machine_mode mode;
if (GET_CODE (mem) == ZERO_EXTEND)
switch (mode)
{
case E_QImode:
- mode_name = "char";
load_str = "lbz";
break;
case E_HImode:
- mode_name = "short";
load_str = "lhz";
break;
case E_SImode:
case E_SFmode:
- mode_name = (mode == SFmode) ? "float" : "int";
load_str = "lwz";
break;
case E_DImode:
case E_DFmode:
gcc_assert (TARGET_POWERPC64);
- mode_name = (mode == DFmode) ? "double" : "long";
load_str = "ld";
break;
}
/* Emit the addis instruction. */
- emit_fusion_addis (target, addis_value, "gpr load fusion", mode_name);
+ emit_fusion_addis (target, addis_value);
/* Emit the D-form load instruction. */
emit_fusion_load_store (target, target, load_offset, load_str);
fusion_split_address (addr, &hi, &lo);
/* Emit the addis instruction. */
- emit_fusion_addis (tmp_reg, hi, "power9 load fusion", GET_MODE_NAME (mode));
+ emit_fusion_addis (tmp_reg, hi);
/* Emit the D-form load instruction. */
emit_fusion_load_store (reg, tmp_reg, lo, load_string);
fusion_split_address (addr, &hi, &lo);
/* Emit the addis instruction. */
- emit_fusion_addis (tmp_reg, hi, "power9 store fusion", GET_MODE_NAME (mode));
+ emit_fusion_addis (tmp_reg, hi);
/* Emit the D-form load instruction. */
emit_fusion_load_store (reg, tmp_reg, lo, store_string);
UNSPEC_FUSION_P9))]
"TARGET_P9_FUSION"
{
- emit_fusion_addis (operands[0], operands[1], "constant", "<MODE>");
+ emit_fusion_addis (operands[0], operands[1]);
return "ori %0,%0,%2";
}
[(set_attr "type" "two")
(mem:VSX_M (plus:P (match_dup 0)
(match_operand:P 3 "int_reg_operand" ""))))]
"TARGET_VSX && TARGET_P8_FUSION && !TARGET_P9_VECTOR"
- "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M:VSm>x %x2,%0,%3"
+ "li %0,%1\;lx<VSX_M:VSm>x %x2,%0,%3\t\t\t# vector load fusion"
[(set_attr "length" "8")
(set_attr "type" "vecload")])
(mem:VSX_M (plus:P (match_operand:P 3 "int_reg_operand" "")
(match_dup 0))))]
"TARGET_VSX && TARGET_P8_FUSION && !TARGET_P9_VECTOR"
- "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M:VSm>x %x2,%0,%3"
+ "li %0,%1\;lx<VSX_M:VSm>x %x2,%0,%3\t\t\t# vector load fusion"
[(set_attr "length" "8")
(set_attr "type" "vecload")])
+2017-12-01 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * gcc.target/powerpc/fusion.c: Add -dp to options. Adjust the expected
+ output.
+ * gcc.target/powerpc/fusion3.c: Ditto.
+ * gcc.target/powerpc/fusion4.c: Ditto.
+
2017-12-01 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81959
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-mcpu=power7 -mtune=power8 -O3" } */
+/* { dg-options "-mcpu=power7 -mtune=power8 -O3 -dp" } */
#define LARGE 0x12345
int fusion_int (int *p){ return p[LARGE]; }
unsigned fusion_uns (unsigned *p){ return p[LARGE]; }
-/* { dg-final { scan-assembler-times "gpr load fusion" 6 } } */
+/* { dg-final { scan-assembler-times "fusion_gpr_load" 6 } } */
/* { dg-final { scan-assembler-times "lbz" 2 } } */
/* { dg-final { scan-assembler-times "extsb" 1 } } */
/* { dg-final { scan-assembler-times "lhz" 2 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-mcpu=power7 -mtune=power9 -O3" } */
+/* { dg-options "-mcpu=power7 -mtune=power9 -O3 -dp" } */
#define LARGE 0x12345
void fusion_float_write (float *p, float f){ p[LARGE] = f; }
void fusion_double_write (double *p, double d){ p[LARGE] = d; }
-/* { dg-final { scan-assembler "load fusion, type SF" } } */
-/* { dg-final { scan-assembler "load fusion, type DF" } } */
-/* { dg-final { scan-assembler "store fusion, type SF" } } */
-/* { dg-final { scan-assembler "store fusion, type DF" } } */
+/* { dg-final { scan-assembler {fusion_vsx_[sd]i_sf_load} } } */
+/* { dg-final { scan-assembler {fusion_vsx_[sd]i_df_load} } } */
+/* { dg-final { scan-assembler {fusion_vsx_[sd]i_sf_store} } } */
+/* { dg-final { scan-assembler {fusion_vsx_[sd]i_df_store} } } */
-/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-mcpu=power7 -mtune=power9 -O3 -msoft-float" } */
+/* { dg-options "-mcpu=power7 -mtune=power9 -O3 -msoft-float -dp" } */
#define LARGE 0x12345
void fusion_float_write (float *p, float f){ p[LARGE] = f; }
-/* { dg-final { scan-assembler "store fusion, type SF" } } */
+/* { dg-final { scan-assembler {fusion_gpr_[sd]i_sf_store} } } */