i965: Don't force a header for texture offsets of 0.

Calling textureOffset() with an offset of <0, 0, 0> is equivalent to
calliing texture().  We don't actually need to set up an offset,
which causes a message header to be created.

A fairly common pattern is to sample at a point with a bunch of
offsets, and average them.  It's natural to write all the lookups
as textureOffset, but use <0, 0> for the center sample.

shader-db results on Skylake:

total instructions in shared programs: 9092095 -> 9092087 (-0.00%)
instructions in affected programs: 2826 -> 2818 (-0.28%)
helped: 12
HURT: 2

total cycles in shared programs: 70870166 -> 70870144 (-0.00%)
cycles in affected programs: 15924 -> 15902 (-0.14%)
helped: 2
HURT: 0

This also helps prevent code quality regressions in a future patch.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by Jason Ekstrand <jason@jlekstrand.net>

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 7ef3062a247804a74633eeb70f46fe351f228ee8..725f5dac0c7bc62252aae1cc00791e3715737d2d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -3132,7 +3132,9 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
          nir_const_value *const_offset =
             nir_src_as_const_value(instr->src[i].src);
          if (const_offset) {
-            tex_offset = brw_imm_ud(brw_texture_offset(const_offset->i32, 3));
+            unsigned header_bits = brw_texture_offset(const_offset->i32, 3);
+            if (header_bits != 0)
+               tex_offset = brw_imm_ud(header_bits);
          } else {
             tex_offset = retype(src, BRW_REGISTER_TYPE_D);
          }