-add mask on Term

diff --git a/examples/de0_nano/client/test_MigLa.py b/examples/de0_nano/client/test_MigLa.py
index 0922d6fe55e3876cc781b20877f104354c5bf6dd..a5b41e688369f283619afd927c42eb8c4a93d472 100644 (file)
--- a/examples/de0_nano/client/test_MigLa.py
+++ b/examples/de0_nano/client/test_MigLa.py
@@ -47,7 +47,7 @@ migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0, csr)
 dat_vcd = []
 recorder0.size(1024)
 
-def capture():
+def capture(size):
        global trigger0
        global recorder0
        global dat_vcd
@@ -64,26 +64,26 @@ def capture():
        
        print("-Receiving Data...", end = ' ')
        sys.stdout.flush()
-       dat_vcd += migLa0.rec.read(1024)
+       dat_vcd += migLa0.rec.read(size)
        print("[Done]")
        
 print("Capturing Ramp..")
 print("----------------------")
-term0.write(0x0000)
+term0.write(0x0000,0xFFFF)
 csr.write(0x0000, 0)
-capture()
+capture(1024)
 
 print("Capturing Square..")
 print("----------------------")
-term0.write(0x0000)
+term0.write(0x0000,0xFFFF)
 csr.write(0x0000, 1)
-capture()
+capture(1024)
 
 print("Capturing Sinus..")
 print("----------------------")
-term0.write(0x0080)
+term0.write(0x0080,0xFFFF)
 csr.write(0x0000, 2)
-capture()
+capture(1024)
 
 myvcd = Vcd()
 myvcd.add(Var("wire", 16, "trig_dat", dat_vcd))

diff --git a/examples/de1/client/test_MigLa.py b/examples/de1/client/test_MigLa.py
index 0922d6fe55e3876cc781b20877f104354c5bf6dd..a5b41e688369f283619afd927c42eb8c4a93d472 100644 (file)
--- a/examples/de1/client/test_MigLa.py
+++ b/examples/de1/client/test_MigLa.py
@@ -47,7 +47,7 @@ migLa0 = migLa.MigLa(MIGLA_ADDR, trigger0, recorder0, csr)
 dat_vcd = []
 recorder0.size(1024)
 
-def capture():
+def capture(size):
        global trigger0
        global recorder0
        global dat_vcd
@@ -64,26 +64,26 @@ def capture():
        
        print("-Receiving Data...", end = ' ')
        sys.stdout.flush()
-       dat_vcd += migLa0.rec.read(1024)
+       dat_vcd += migLa0.rec.read(size)
        print("[Done]")
        
 print("Capturing Ramp..")
 print("----------------------")
-term0.write(0x0000)
+term0.write(0x0000,0xFFFF)
 csr.write(0x0000, 0)
-capture()
+capture(1024)
 
 print("Capturing Square..")
 print("----------------------")
-term0.write(0x0000)
+term0.write(0x0000,0xFFFF)
 csr.write(0x0000, 1)
-capture()
+capture(1024)
 
 print("Capturing Sinus..")
 print("----------------------")
-term0.write(0x0080)
+term0.write(0x0080,0xFFFF)
 csr.write(0x0000, 2)
-capture()
+capture(1024)
 
 myvcd = Vcd()
 myvcd.add(Var("wire", 16, "trig_dat", dat_vcd))

diff --git a/migScope/trigger.py b/migScope/trigger.py
index 477fc926c1eb958cbebcce1162ddd39f7b9b0573..144d5747b1db9d938a9edf9eb17ba5eb7e2abe27 100644 (file)
--- a/migScope/trigger.py
+++ b/migScope/trigger.py
@@ -15,16 +15,17 @@ class Term:
                
                self.reg_name = "term_reg"
                self.reg_base = 0
-               self.reg_size = 1*width
+               self.reg_size = 2*width
                self.words = int(2**bits_for(width-1)/8)
                
                self.i = Signal(BV(self.width))
                self.t = Signal(BV(self.width))
+               self.m = Signal(BV(self.width))
                self.o = Signal()
                
        def get_fragment(self):
                frag = [
-                       self.o.eq(self.i==self.t)
+                       self.o.eq((self.m & self.i) == self.t)
                        ]
                if self.pipe:
                        return Fragment(sync=frag)
@@ -34,13 +35,17 @@ class Term:
        def connect_to_reg(self, reg):
                comb = []
                comb += [self.t.eq(reg.field.r[0*self.width:1*self.width])]
+               comb += [self.m.eq(reg.field.r[1*self.width:2*self.width])]
                return comb
        #       
        #Driver
        #
-       def write(self, dat):
-               self.interface.write_n(self.reg_base, dat ,self.width)
-
+       def write(self, dat, mask = None):
+               if mask == None:
+                       mask = (2**self.width)-1
+               self.interface.write_n(self.reg_base + self.words, dat ,self.width)
+               self.interface.write_n(self.reg_base, mask ,self.width)
+               
 class RangeDetector:
        # 
        # Definition
@@ -163,21 +168,30 @@ class EdgeDetector:
        #
        #Driver
        #
+       
+       def get_offset(self, type):
+               if type == "R":
+                       r = 0
+                       r = r+self.words if "F" in self.mode else r
+                       r = r+self.words if "B" in self.mode else r
+                       return r
+               elif type == "F":
+                       r = 0
+                       r = r+self.words if "B" in self.mode else r
+                       return r
+               elif type == "B":
+                       r = 0
+                       return r
+               return 0
+                       
        def write_r(self, dat):
-               self.interface.write_n(self.reg_base, dat ,self.width)
+               self.interface.write_n(self.reg_base + self.get_offset("R"), dat ,self.width)
        
        def write_f(self, dat):
-               offset = 0
-               if "R" in self.mode:
-                       offset += self.words
-               self.interface.write_n(self.reg_base + offset, dat ,self.width)
+               self.interface.write_n(self.reg_base + self.get_offset("F"), dat ,self.width)
                
        def write_b(self, dat):
-               if "R" in self.mode:
-                       offset += self.words
-               if "F" in self.mode:
-                       offset += self.words
-               self.interface.write_n(self.reg_base + offset, dat ,self.width)
+               self.interface.write_n(self.reg_base + self.get_offset("B"), dat ,self.width)
 
 class Timer:
        #