asmi: dat_wm high to disable data write

diff --git a/doc/index.rst b/doc/index.rst
index 8db436f2fe8f0633a9fd032695cc1e499e054494..553529370032f1bf05e4c965f905cd7753d8d327 100644 (file)
--- a/doc/index.rst
+++ b/doc/index.rst
@@ -377,7 +377,7 @@ The data signals are used to complete requests.
 * Master-to-Hub
 
   * ``data_w`` must supply data to the controller from the appropriate write transaction, on the cycle after they have been called using ``call`` and ``tag_call``.
-  * ``data_wm`` are the byte-granular write data masks. They are used in combination with ``data_w`` to identify the bytes that should be modified in the memory. The ``data_wm`` bit should be high for its corresponding ``data_w`` byte to be written.
+  * ``data_wm`` are the byte-granular write data masks. They are used in combination with ``data_w`` to identify the bytes that should be modified in the memory. The ``data_wm`` bit should be low for its corresponding ``data_w`` byte to be written.
 
 In order to avoid duplicating the tag matching and tracking logic, the master-to-hub data signals must be driven low when they are not in use, so that they can be simply ORed together inside the memory controller. This way, only masters have to track (their own) transactions for arbitrating the data lines.
 

diff --git a/migen/bus/asmibus.py b/migen/bus/asmibus.py
index 4bae4ef7cb0c1cd8da05825d32485b3f6a643ccb..93644781e39f2d2cbaee6a99ff3d6ce30e6be915 100644 (file)
--- a/migen/bus/asmibus.py
+++ b/migen/bus/asmibus.py
@@ -205,7 +205,7 @@ class Initiator:
                                        yield
                                if isinstance(transaction, TWrite):
                                        s.wr(port.dat_w, transaction.data)
-                                       s.wr(port.dat_wm, transaction.sel)
+                                       s.wr(port.dat_wm, ~transaction.sel)
                                        yield
                                        s.wr(port.dat_w, 0)
                                        s.wr(port.dat_wm, 0)

diff --git a/migen/bus/wishbone2asmi.py b/migen/bus/wishbone2asmi.py
index 178925a27307db8f4584a03fbd840b822ed2e9af..856be225740f9dc9ed85bbb3d69dec7902833428 100644 (file)
--- a/migen/bus/wishbone2asmi.py
+++ b/migen/bus/wishbone2asmi.py
@@ -54,10 +54,8 @@ class WB2ASMI:
                                        displacer(self.wishbone.sel, adr_offset, data_we, 2**offsetbits, reverse=True)
                                )
                        ),
-                       If(write_to_asmi,
-                               self.asmiport.dat_w.eq(data_do),
-                               self.asmiport.dat_wm.eq(Replicate(1, adw//8))
-                       ),
+                       If(write_to_asmi, self.asmiport.dat_w.eq(data_do)),
+                       self.asmiport.dat_wm.eq(0),
                        chooser(data_do, adr_offset_r, self.wishbone.dat_r, reverse=True)
                ]
                sync += [