open AMDIL, '<', 'AMDILInstructions.td';
-my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32', 'BINARY_NOT_i32', 'ROUND_POSINF_f32', 'ROUND_NEAREST_f32');
+my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32', 'BINARY_NOT_i32', 'ROUND_NEAREST_f32');
while (<AMDIL>) {
if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)</) {
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+
+ // Library functions. These default to Expand, but we have instructions
+ // for them.
+ setOperationAction(ISD::FCEIL, MVT::f32, Legal);
+
}
SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
case AMDGPUIntrinsic::AMDGPU_umin:
return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
Op.getOperand(2));
+ case AMDGPUIntrinsic::AMDIL_round_posinf:
+ return DAG.getNode(ISD::FCEIL, DL, VT, Op.getOperand(1));
}
}
int_AMDIL_round_nearest>;
defm ROUND_NEGINF : UnaryIntrinsicFloat<IL_OP_ROUND_NEG_INF,
int_AMDIL_round_neginf>;
-defm ROUND_POSINF : UnaryIntrinsicFloat<IL_OP_ROUND_POS_INF,
- int_AMDIL_round_posinf>;
defm ROUND_ZERO : UnaryIntrinsicFloat<IL_OP_ROUND_ZERO,
int_AMDIL_round_zero>;
defm ACOS : UnaryIntrinsicFloatScalar<IL_OP_ACOS, int_AMDIL_acos>;
def CEIL : R600_1OP <
0x12, "CEIL",
- [(set R600_Reg32:$dst, (int_AMDIL_round_posinf R600_Reg32:$src))]> {
- let AMDILOp = AMDILInst.ROUND_POSINF_f32;
-}
+ [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))]
+>;
def RNDNE : R600_1OP <
0x13, "RNDNE",