-2009-01-02 Matthias Klose <doko@ubuntu.com>
-
- * itbl-ops.c (itbl_disassemble): Don't rely on undefined sprintf
- behaviour.
-
-2008-12-23 Jon Beniston <jon@beniston.com>
-
- * NEWS: Record that support for LM32 has been added.
- * Makefile.am: Add LM32 object files and dependencies.
- * Makefile.in: Regenerate.
- * configure.in: Indicate LM32 uses cgen.
- * configure: Regenerate.
- * configure.tgt: Add LM32 target.
- * config/tc-lm32.c: New file.
- * config/tc-lm32.h: New file.
- * doc/Makefile.am: Add c-lm32.texi to CPU_DOCS.
- * doc/Makefile.in: Regenerate.
- * doc/all.texi: Add LM32 as CPU of interest.
- * doc/as.texinfo: Add LM32 dependent features link.
- * doc/c-lm32.texi: New file.
-
-2008-12-23 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (match_template): Changed to return
- const template *. Handle i.swap_operand for 3 operands.
- (build_vex_prefix): Take const template *. Swap operand for
- 2-byte VEX prefix if possible.
- (md_assemble): Updated.
- (build_modrm_byte): Handle RegMem bit for SSE2AVX.
-
-2008-12-23 Anatoly Sokolov <aesok@post.ru>
-
- * config/tc-avr.c (mcu_types): Add attiny87, attiny327, atmega4hvd,
- atmega8hvd, atmega16hvb, atmega32hvb, atmega64c1, atmega16m1,
- atmega64m1, atmega32u6, atmega128rfa1, at90pwm81, at90scr100,
- m3000f, m3000s and m3001b devices.
- * doc/c-avr.texi: Likewise.
-
-2008-12-23 Nick Clifton <nickc@redhat.com>
-
- * NEWS :Remove mention of STT_IFUNC support.
- * config/obj-elf.c (obj_elf_type): Remove STT_IFUNC support.
- * doc/as.texinfo: Remove mention of STT_IFUNC support.
-
-2008-12-21 Hans-Peter Nilsson <hp@axis.com>
-
- * config/tc-cris.c (s_cris_dtpoff): New function.
- (md_pseudo_table): Add "dtpoffd".
-
-2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (parse_insn): Optimize ".s" handling.
-
-2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (_i386_insn): Add swap_operand.
- (parse_insn): Handle ".s".
- (match_template): Handle swap_operand.
-
- * doc/c-i386.texi: Document .s suffix.
-
-2008-12-20 Hans-Peter Nilsson <hp@axis.com>
-
- * config/tc-cris.c (cris_process_instruction): Handle
- BFD_RELOC_CRIS_32_IE, in the test whether the relocation fits.
- (get_3op_or_dip_prefix_op): Handle TLS/PIC decoration for the
- "double indirect" addressing mode.
- (cris_get_reloc_suffix): Add entry for :IE for BFD_RELOC_CRIS_32_IE.
- (cris_number_to_imm, tc_gen_reloc): Handle BFD_RELOC_CRIS_32_IE.
-
-2008-12-18 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
-
- * configure: Regenerate.
-
-2008-12-08 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (build_modrm_byte): Remove an extra blank
- line.
-
-2008-12-04 Ben Elliston <bje@au.ibm.com>
-
- * config/tc-ppc.c (parse_cpu): Remove booke64 support. Update
- usage strings.
- (ppc_setup_opcodes): Likewise, remove booke64 support.
- * doc/c-ppc.texi (PowerPC-Opts): Remove -mbooke32 and -mbooke64.
- * doc/as.texinfo (Overview): Likewise.
-
-2008-12-04 Nick Clifton <nickc@redhat.com>
-
- * doc/as.texinfo (Type): Reword description of STT_IFUNC type.
-
-2008-12-03 Nick Clifton <nickc@redhat.com>
-
- * config/obj-elf.c (obj_elf_type): Add support for STT_IFUNC type.
- * doc/as.texinfo: Document new feature.
- * NEWS: Mention new feature.
-
-2008-11-29 Kai Tietz <kai.tietz@onevision.com>
-
- * config/tc-i386.c (i386_target_format): For coff flavour in TE_PEP
- use "pe-i386" for 32-bit.
-
-2008-11-28 Jakub Jelinek <jakub@redhat.com>
-
- * Makefile.am (ehopt.o): Add struc-symbol.h.
- * Makefile.in: Regenerated.
- * ehopt.c: Include struc-symbol.h.
- (check_eh_frame): For very small O_constant DW_CFA_advance_loc4
- create correct DW_CFA_advance_loc. Handle O_subtract only
- for code alignment factor 1, otherwise handle O_divide or
- O_right_shift of O_subtract and O_constant.
- (eh_frame_estimate_size_before_relax): Always divide by ca.
- (eh_frame_convert_frag): Likewise.
-
-2008-11-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
-
- * dw2gencfi.c (output_cfi_insn): Scale DW_CFA_advance_loc1,
- DW_CFA_advance_loc2 and DW_CFA_advance_loc4 outputs.
-
-2008-11-28 Joshua Kinard <kumba@gentoo.org>
-
- * config/tc-mips.c (hilo_interlocks): Handle CPU_R14000, CPU_R16000.
- (mips_cpu_info_table): Add r14000, r16000.
- * doc/c-mips.texi: Add entries for 14000, 16000.
-
-2008-11-27 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
-
- * config/tc-cr16.h (GLOBAL_OFFSET_TABLE_NAME): Defined
- * config/tc-cr16.c (md_pseudo_table): Add "4byte" directive to
- md_pseudo_table and accept @c prefix, same as long directive.
- (cr16_cons_fix_new): Initialize rtype to BFD_RELOC_UNUSED.
- (tc_gen_reloc): Declare a variable of type bfd_reloc_code_real_type
- and set it for GOT related relocations.
- (md_undefined_symbol): Defined
- (process_label_constant): Added checks for GOT/got and cGOT/cGOT
- prefixes with constant label and set the appropriate relocation type.
- * doc/c-cr16.texi (cr16-operand specifiers): Add got/GOT and cgot/cGOT.
-
-2008-11-26 DJ Delorie <dj@redhat.com>
-
- * config/tc-m32c.c (md_pseudo_table): Add support for .loc et al.
-
-2008-11-25 DJ Delorie <dj@redhat.com>
-
- * config/tc-m32c.c (md_convert_frag): Fix ADJNZ reloc math.
-
-2008-11-21 Sterling Augustine <sterling@tensilica.com>
-
- * config/tc-xtensa.c (check_t1_t2_reads_and_writes): Call
- xtensa_state_is_shared_or to allow multiple opcodes within a
- single FLIX bundle to write to these special states.
-
-2008-11-19 Hans-Peter Nilsson <hp@axis.com>
-
- * config/tc-cris.c (cris_number_to_imm): Apply S_SET_THREAD_LOCAL
- on symbols in TLS relocs.
-
-2008-11-19 Nick Clifton <nickc@redhat.com>
-
- * doc/fdl.texi: Update to v1.3
- * doc/as.texinfo: Change license to v1.3.
-
-2008-11-18 Catherine Moore <clm@cm00re.com>
-
- * config/tc-arm.c (neon_type_mask): Renumber.
- (type_chk_of_el_type): Handle F_F16.
- (neon_cvt_flavour): Recognize half-precision conversions.
- (do_neon_cvt): New shapes NS_QD and
- NS_DQ. Encode half-precision conversions.
- (do_neon_cvtt): Encode the T bit.
- (asm_opcode_insns): vcvt, vcvtt support.
- (arm_option_cpu_value): Add neon-fp16 support.
-
-2008-11-17 Nick Clifton <nickc@redhat.com>
-
- * as.c (parse_args): Update copyright year.
-
-2008-11-14 Mat Hostetter <mat@lcs.mit.edu>
-
- * read.c (emit_expr): Grow frag before filling it so that
- dot_value remains valid.
-
-2008-11-14 Peter Jansen <pwjansen@yahoo.com>
-
- PR 7026
- * config/tc-arm.c: Ensure that all uses of as_bad have a
- formatting string.
-
-2008-11-12 Hans-Peter Nilsson <hp@axis.com>
-
- * config/tc-cris.c (cris_number_to_imm): Except for
- BFD_RELOC_NONE, always set contents. Where previously this was
- skipped, set contents to 0.
-
- PR gas/7025
- * input-scrub.c (input_scrub_include_sb): Make the position
- after the input have defined contents, a 0 character.
-
- * config/tc-cris.c (cris_relax_frag): Add missing case for
- ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD).
-
- PR gas/7020
- * read.c (read_a_source_file): Rearrange evaluation order when
- looking for '=' to avoid conditional on undefined contents of
- input_line_pointer[1].
-
-2008-11-06 Adam Nemet <anemet@caviumnetworks.com>
-
- * config/tc-mips.c (COP_INSN): Change logic to always return false
- for FP instructions.
-
-2008-11-06 Chao-ying Fu <fu@mips.com>
-
- * config/tc-mips.c (validate_mips_insn): Add case '1'.
- (mips_ip): Add case '1' to process sync type.
-
-2008-11-06 Joel Sherrill <joel.sherrill@oarcorp.com>
-
- * configure.tgt: Add m32c-*-rtems* and m32r-*-rtems*.
-
-2008-11-04 Sterling Augustine <sterling@tensilica.com>
-
- * config/tc-xtensa.c (tinsn_check_arguments): Check for multiple
- writes to the same register.
-
-2008-11-04 Sterling Augustine <sterling@tensilica.com>
-
- * config/tc-xtensa.c (xtensa_j_opcode): New.
- (xg_instruction_matches_option_term): Handle "FREEREG" option.
- (xg_build_to_insn): Likewise. Update renamed tls_reloc reference.
- (md_begin): Initialize xtensa_j_opcode.
- (md_assemble): Update renamed tls_reloc reference. Handle "j.l".
- (xg_assemble_vliw_tokens): Save free_reg info in the frag.
- (tinsn_immed_from_frag): Get free_reg info back out of the frag.
- (vinsn_to_insnbuf): Update renamed tls_reloc references.
- Distinguish extra argument for "FREEREG" from extra TLS argument.
- * config/tc-xtensa.h (struct xtensa_frag_type): Add free_reg field.
- * config/xtensa-istack.h (struct tinsn_struct): Rename tls_reloc
- field to extra_arg.
- * config/xtensa-relax.c (widen_spec_list): Add rules to relax "j.l".
- (build_transition): Handle "FREEREG" operand.
- * config/xtensa-relax.h (enum op_type): Add OP_FREEREG.
-
-2008-10-31 Alan Modra <amodra@bigpond.net.au>
-
- * po/id.po: Update.
-
-2008-10-24 Maciej W. Rozycki <macro@linux-mips.org>
-
- * config/tc-mips.c (mips_cpu_info_table): Move the MIPS64r2
- comment so that Broadcom SB-1 cores are in the MIPS64 section.
-
-2008-10-21 Alan Modra <amodra@bigpond.net.au>
-
- * config/tc-bfin.c (gencode, allocate): Remove unnecessary cast.
- * config/tc-ns32k.c (bit_fix_new): Likewise.
- * config/tc-m68k.c (md_begin): Likewise.
- * hash.c (hash_insert, hash_jam): Likewise.
- * symbols.c (symbol_create, local_symbol_make): Likewise.
- * frags.c (frag_alloc): Likewise.
-
-2008-10-20 Jay Krell <jay.krell@cornell.edu>
-
- * config/bfin-parse.y: Use C style comments.
- * config/tc-bfin.c: Likewise.
- * config/tc-m68k.c: Likewise.
- * config/tc-mips.c: Likewise.
-
-2008-10-12 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (processor_type): Moved to tc-i386.h.
- (cpu_arch_tune): Make it global.
- (cpu_arch_isa): Likewise.
- (cpu_arch_isa_flags): Likewise.
- (i386_align_code): Check fragP->tc_frag_data.isa,
- fragP->tc_frag_data.isa_flags and cpu_arch_tune instead of
- cpu_arch_isa, cpu_arch_isa_flags and cpu_arch_tune,
- respectively.
-
- * config/tc-i386.h (processor_type): Moved from tc-i386.c.
- (cpu_arch_tune): New.
- (cpu_arch_isa): Likewise.
- (cpu_arch_isa_flags): Likewise.
- (i386_tc_frag_data): Likewise.
- (TC_FRAG_TYPE): Likewise.
- (TC_FRAG_INIT): Likewise.
-
-2008-10-09 Bob Wilson <bob.wilson@acm.org>
-
- * doc/as.texinfo (Pseudo Ops): Swap order of Comm and CFI menu entries.
- (Altmacro, Comm, Loc, Loc_mark_labels, List, MRI, PopSection, Sleb128):
- Moved into alphabetical order.
-
-2008-10-09 Bob Wilson <bob.wilson@acm.org>
-
- * doc/as.texinfo (Dot): Expand no-space-dir conditional to include
- a complete sentence.
- (Pseudo Ops): Put conditionals around Skip and Space menu entries.
- (Line): Remove conditional declaration of Ln node and section here.
- Put aout-bout description inside the no-line-dir conditional.
- (Skip, Space): Use a separate conditional for each node.
-
-2008-10-09 Bob Wilson <bob.wilson@acm.org>
-
- * doc/as.texinfo (Pseudo Ops): Remove no-file-dir conditional around
- menu entry for File; remove version-specific .file operands from menu
- description. Replace "LNS directives" menu entry with new entries
- for "Loc" and "Loc_mark_labels".
- (LNS directives): Split into separate nodes for each directive.
- (Loc): New node for .loc directive. Mention that this directive
- is for DWARF2 and add a missing article.
- (Loc_mark_labels): Likewise for .loc_mark_labels.
- (File): Change this node to describe both the default version and
- the DWARF2 version of .file. Move the no-file-dir conditional to
- include only the default version.
-
-2008-10-09 Eric Botcazou <ebotcazou@adacore.com>
-
- * dw2gencfi.c (cfi_finish): Deal with md_fix_up_eh_frame.
- * config/tc-i386.h (md_fix_up_eh_frame): Define on Solaris.
- (i386_solaris_fix_up_eh_frame): Declare.
- * config/tc-i386.c (i386_solaris_fix_up_eh_frame): New function.
-
-2008-10-09 Nick Clifton <nickc@redhat.com>
-
- PR 6944
- * doc/as.texinfo (Dollar Local Labels): Correct description of
- dollar local labels to show that the colon suffix is still
- needed.
-
-2008-10-08 Nick Clifton <nickc@redhat.com>
-
- * configure.in (ALL_LINGUAS): Add "id".
- * configure: Regenerate.
- * po/id.po: New Indonesian translation.
-
-2008-10-07 H.J. Lu <hongjiu.lu@intel.com>
-
- * read.c (pseudo_set): Don't allow global register symbol only
- if TC_GLOBAL_REGISTER_SYMBOL_OK is undefined.
- * symbols.c (S_SET_EXTERNAL): Likewise.
-
- * config/tc-mmix.h (TC_GLOBAL_REGISTER_SYMBOL_OK): Defined.
-
- * doc/internals.texi: Document TC_GLOBAL_REGISTER_SYMBOL_OK.
-
-2008-10-06 Bob Wilson <bob.wilson@acm.org>
-
- * doc/as.texinfo (Local): New description of ELF .local directive.
-
-2008-10-06 Nick Clifton <nickc@redhat.com>
-
- PR 6926
- * read.c (get_line_sb): Renamed to get_non_macro_line_sb.
- (_find_end_of_line): Add extra parameter indicating if the line is
- inside a macro. If it is then do not allow the @ character to be
- treated as a line separator character.
- (read_a_source): Update use of _find_end_of_line.
- (find_end_of_line): Likewise.
- (s_irp): Update use of get_line_sb.
- (s_macro): Likewise.
- (do_repeat): Likewise.
- (get_line_sb): New function. Like the old version of get_line_sb
- except that it takes an extra parameter indicating whether the
- line is inside a macro.
- (get_macro_line_sb): New function.
-
-2008-10-04 Hans-Peter Nilsson <hp@axis.com>
-
- * config/tc-cris.c: Update all comments regarding explicit relocations
- to, besides PIC, also imply TLS or to say "relocation specifier" or
- similar.
- (RELOC_SUFFIX_CHAR): Rename from PIC_SUFFIX_CHAR. Change all callers.
- (cris_get_reloc_suffix): Rename from cris_get_pic_suffix. Change all
- callers. Also handle TLS relocs.
- (cris_get_specified_reloc_size): Rename from cris_get_pic_reloc_size.
- Change all callers. Also handle TLS relocs.
- (tls): New constant.
- (cris_process_instruction): Check for non-PIC TLS relocations and
- adjust message when emitting error message about relocation not
- fitting.
- (get_autoinc_prefix_or_indir_op): Also check for relocation suffix
- when tls is true.
- (get_3op_or_dip_prefix_op): Ditto.
- (cris_number_to_imm, tc_gen_reloc): Handle TLS relocs like PIC relocs.
-
-2008-10-03 Kazu Hirata <kazu@codesourcery.com>
-
- * listing.c (buffer_line): Open the source file with FOPEN_RB.
- Manually process line ends.
-
-2008-09-30 Wesley W. Terpstra <wesley@terpstra.ca>
- Nick Clifton <nickc@redhat.com>
-
- * config/tc-tic4x.c (tic4x_globl): Call S_SET_EXTERNAL as well as
- S_SET_STORAGE_CLASS.
-
-2008-09-30 Wesley W. Terpstra <wesley@terpstra.ca>
- Nick Clifton <nickc@redhat.com>
-
- * coffgen.c (coff_write_symbols): Check to see if a symbol's flags
- do not match it class and if necessary update the class.
- (null_error_handler): New function. Suppresses the generation of
- bfd error messages.
- * coff64-rs6000.c (bfd_xcoff_backend_data): Update comment.
-
-2008-09-30 Alan Modra <amodra@bigpond.net.au>
-
- * Makefile.am: Run "make dep-am".
- * Makefile.in: Regenerate.
-
-2008-09-29 Nick Clifton <nickc@redhat.com>
-
- * dw2gencfi.c (output_cfi_insn): Fix typo in invocation of
- tc_cfi_emit_pcrel_expr macro.
-
-2008-09-29 Peter O'Gorman <pogma@thewrittenword.com>
- Steve Ellcey <sje@cup.hp.com>
-
- * configure: Regenerate for new libtool.
- * aclocal.m4: Ditto.
- * Makefile.in: Ditto.
- * doc/Makefile.in: Ditto.
-
-2008-09-29 Nick Clifton <nickc@redhat.com>
-
- PR 6878
- * app.c (do_scrub_chars): Only issue warnings about tick
- characters detected in symbol strings if hex ticks are supported.
-
-2008-09-29 Nick Clifton <nickc@redhat.com>
-
- * dw2gencfi.c (output_cfi_insn): Fix typo in invocation of
- tc_cfi_emit_pcrel_expr macro.
-
-2008-09-28 Daniel Jacobowitz <dan@codesourcery.com>
-
- * NEWS: Mention .cfi_val_encoded_addr.
-
-2008-09-26 Eric Botcazou <ebotcazou@adacore.com>
-
- * Makefile.am (TARG_ENV_HFILES): Add config/te-solaris.h.
- * Makefile.in (TARG_ENV_HFILES): Likewise.
- * configure.tgt (Solaris targets): Set em=solaris.
- * config/te-solaris.h: New file.
-
-2008-09-26 Jie Zhang <jie.zhang@analog.com>
-
- * config/bfin-parse.y (asm_1): Fix reduce/reduce conflicts.
-
-2008-09-24 Richard Henderson <rth@redhat.com>
-
- * dw2gencfi.c (DWARF2_ADDR_SIZE): Provide default.
- (struct cfi_insn_data): Add ea member.
- (CFI_val_encoded_addr, dot_cfi_val_encoded_addr): New.
- (output_cfi_insn): Handle CFI_val_encoded_addr.
- (select_cie_for_fde): Don't match CFI_val_encoded_addr.
- * doc/as.texinfo (.cfi_val_encoded_addr): Document.
-
-2008-09-25 Alan Modra <amodra@bigpond.net.au>
-
- PR 6913
- * listing.c (print_options): Don't call fprintf without format string.
-
-2008-09-19 Alan Modra <amodra@bigpond.net.au>
-
- * write.c (TC_FORCE_RELOCATION_SUB_LOCAL): Heed md_register_arithmetic.
- (TC_VALIDATE_FIX_SUB): Likewise.
- * config/tc-frv.h (TC_FORCE_RELOCATION_SUB_LOCAL): Likewise.
- * config/tc-hppa.h (TC_FORCE_RELOCATION_SUB_LOCAL): Likewise.
- * config/tc-mn10300.h (TC_VALIDATE_FIX_SUB): Likewise.
- * config/tc-sh.h (TC_VALIDATE_FIX_SUB): Likewise.
- (TC_FORCE_RELOCATION_SUB_LOCAL): Likewise.
- * config/tc-sh64.h (TC_VALIDATE_FIX_SUB): Likewise.
- * config/tc-xtensa.h (TC_VALIDATE_FIX_SUB): Likewise.
- * doc/internals.texi (TC_FORCE_RELOCATION_SUB_ABS,
- TC_FORCE_RELOCATION_SUB_LOCAL, TC_VALIDATE_FIX_SUB): Show new param.
-
- * write.c (md_register_arithmetic): Define.
- (fixup_segment): Adjust TC_FORCE_RELOCATION_SUB_ABS invocation.
- Modify error message when registers involved.
- (TC_FORCE_RELOCATION_SUB_ABS): Heed md_register_arithmetic.
- * config/tc-sh.h (TC_FORCE_RELOCATION_SUB_ABS): Likewise.
-
-2008-09-15 Alan Modra <amodra@bigpond.net.au>
-
- * write.c (install_reloc): Correct EMIT_SECTION_SYMBOLS test.
-
-2008-09-15 Alan Modra <amodra@bigpond.net.au>
-
- * config/tc-frv.c (md_apply_fix): Use abs_section_sym for
- relocs with no symbol.
- * config/tc-mmix.c (md_assemble): Mark fake symbol on
- BFD_RELOC_MMIX_BASE_PLUS_OFFSET as OK for use by relocs.
- (mmix_md_end): Likewise mark mmix reg contents section symbol.
-
-2008-09-14 Chris Smith <chris@zxdesign.info>
-
- * config/tc-z80.c: Opcode generation of ld a,(bc) and ld a,(de) was
- broken, as the opcode of ld a,(de) was being emitted for both.
-
-2008-09-12 Sterling Augustine <sterling@tensilica.com>
-
- * config/tc-xtensa.c (init_op_placement_info_table): Allow number of
- operands equal to MAX_INSN_ARGS.
-
-2008-09-11 Jan Kratochvil <jan.kratochvil@redhat.com>
-
- * configure.in: Call AC_SYS_LARGEFILE.
- * config.in: Regenerate.
- * configure: Regenerate.
-
-2008-09-09 Peter Bergner <bergner@vnet.ibm.com>
-
- * config/tc-ppc.c (ppc_setup_opcodes): Simplify POWER4/NOPOWER4 test.
- Remove POWER5 and POWER6 tests.
-
-2008-09-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
-
- * config/tc-hppa.c (hppa_regname_to_dw2regnum): Add register name to
- number support for 32-bit targets.
-
-2008-09-08 Tristan Gingold <gingold@adacore.com>
-
- * NEWS: Add a marker for the 2.19 features.
-
-2008-09-07 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
-
- * config/tc-hppa.h (DIFF_EXPR_OK): Define for SOM target. Revise
- comment regarding use of difference expressions.
- (TC_FORCE_RELOCATION_SUB_LOCAL): Define to 1.
-
- * dw2gencfi.c (CFI_DIFF_EXPR_OK): Define if not defined.
- (dot_cfi_personality): Use CFI_DIFF_EXPR_OK instead of DIFF_EXPR_OK.
- (dot_cfi_lsda, output_cie, output_fde): Likewise.
- * config/tc-hppa.h (CFI_DIFF_EXPR_OK): Define.
-
-2008-09-06 Richard Sandiford <rdsandiford@googlemail.com>
-
- * config/tc-mips.h (DWARF2_FDE_RELOC_SIZE): Define.
-
-2008-09-03 Nick Clifton <nickc@redhat.com>
-
- * config/tc-i386.c (pe_lcomm_internal): New function. Allows the
- alignment field of the .lcomm directive to be optional.
- (pe_lcomm): New function. Pass pe_lcomm_internal to
- s_comm_internal.
- (md_pseudo_table): Implement .lcomm directive for COFF based
- targets.
- * doc/c-i386.texi (i386-Directives): New node. Used to document
- the .lcomm directive.
-
-2008-08-30 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
-
- * config/tc-hppa.h: Don't define DWARF2_EH_FRAME_READ_ONLY on Linux
- and NetBSD.
-
-2008-08-29 Eric B. Weddington <eric.weddington@atmel.com>
-
- * config/tc-avr.c (mcu_types): Add atmega16u4.
- * doc/c-avr.texi: Likewise.
-
-2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-ia64.c (CR_IIB0): New.
- (CR_IIB1): Likewise.
- (cr): Add cr.iib0 and cr.iib1.
- (specify_resource): Handle IA64_RS_CR_IIB and CR_IIB0/CR_IIB1.
-
-2008-08-28 Jan Beulich <jbeulich@novell.com>
-
- * config/tc-i386.c (md_assemble): Force number of displacement
- operands to zero when processing string instruction.
- (i386_index_check): Special-case string instruction operands. Don't
- fudge address prefix if there already was a memory operand. Fix
- error message to correctly reflect the addressing mode used.
- (i386_att_operand): Fix comment.
- (i386_intel_operand): Snapshot, clear, and restore base and index
- reg for each operand processed. Increment count of memory operands
- later.
-
-2008-08-27 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
-
- * config/tc-hppa.c (is_SB_relative): New macro.
- (fix_new_hppa): Remove $segrel$ marker.
- (cons_fix_new_hppa): Set reloc type R_PARISC_SEGREL32 if expression is
- segment relative.
- * config/tc-hppa.h (tc_frob_symbol): Check for $segrel$.
-
-2008-08-27 Jan Beulich <jbeulich@novell.com>
-
- * config/tc-i386.c (check_string): Use register_prefix for error
- message.
- (process_operands): Likewise.
-
-2008-08-26 Mark Mitchell <mark@codesourcery.com>
-
- * c-arm.texi: Add tutorial on ARM unwinding pseudo ops.
-
-2008-08-26 Jie Zhang <jie.zhang@analog.com>
-
- * config/bfin-parse.y (check_macfunc_option): Fix instruction
- mode checking.
- (asm_1): Check mode for 16-bit multiply instructions.
-
-2008-08-24 Alan Modra <amodra@bigpond.net.au>
-
- * configure.in: Update a number of obsolete autoconf macros.
- * configure: Regenerate.
- * aclocal.m4: Regenerate.
-
-2008-08-22 Nick Clifton <nickc@redhat.com>
-
- * config/tc-mcore.c (md_assemble): Increase length of name array
- to include terminating NUL.
-
-2008-08-22 Jie Zhang <jie.zhang@analog.com>
-
- * config/bfin-lex.l (NUMBER): Protect special `.'.
-
-2008-08-22 Alan Modra <amodra@bigpond.net.au>
-
- * symbols.c (symbol_clone): Ensure clones are not external.
-
-2008-08-22 Alan Modra <amodra@bigpond.net.au>
-
- * config/tc-hppa.c (md_begin): Set BSF_KEEP for "dummy_symbol".
-
-2008-08-21 Richard Henderson <rth@redhat.com>
-
- * dw2gencfi.c (DWARF2_FDE_RELOC_SIZE): New.
- (output_cie, output_fde): Use it.
- (DWARF2_EH_FRAME_READ_ONLY): New.
- (cfi_finish): Use it.
-
- * config/tc-hppa.h (DWARF2_FDE_RELOC_SIZE): Set to 8 for 64-bit.
- (DWARF2_CIE_DATA_ALIGNMENT): Change sign.
- (DWARF2_EH_FRAME_READ_ONLY): New.
- * config/tc-hppa.c (tc_gen_reloc): Generate pc-relative relocations
- from the results of DIFF_EXPR_OK manipulation.
-
-2008-08-21 Sterling Augustine <sterling@tensilica.com>
-
- * config/xtensa-istack.h (MAX_INSN_ARGS): Increase to 64.
-
-2008-08-20 Bob Wilson <bob.wilson@acm.org>
-
- * config/tc-xtensa.c (O_tlsfunc, O_tlsarg, O_tlscall): Define.
- (O_tpoff, O_dtpoff): Define.
- (suffix_relocs): Add entries for TLS suffixes.
- (xtensa_elf_cons): Check for invalid use of TLS relocations.
- (map_operator_to_reloc): Add is_literal parameter and use it to
- control translating TLS instruction relocations to the corresponding
- literal relocations.
- (xg_valid_literal_expression): Allow TLS operators.
- (xg_build_to_insn): Copy TLS operators from pseudo-instruction
- operands to generated literals.
- (xg_assemble_literal): Handle TLS operators. Update call to
- map_operator_to_reloc.
- (md_assemble): Handle CALLXn.TLS pseudo-instruction.
- (md_apply_fix): Handle TLS relocations.
- (emit_single_op): Handle TLS operators.
- (convert_frag_immed): Update call to map_operator_to_reloc.
- (vinsn_to_insnbuf): Emit relocations for TLS-related instructions.
- * config/xtensa-istack.h (tinsn_struct): Add tls_reloc field.
- * config/xtensa-relax.c (append_literal_op): Add src_op parameter
- to initialize the op_data field of the BuildOp.
- (build_transition): Use it here to record the source operand
- corresponding to a generated literal.
- * config/xtensa-relax.h (build_op): Comment op_data use for literals.
-
-2008-08-20 H.J. Lu <hongjiu.lu@intel.com>
-
- AVX Programming Reference (August, 2008)
- * config/tc-i386.c (CPU_FLAGS_AES_MATCH): New.
- (CPU_FLAGS_AVX_MATCH): Likewise.
- (CPU_FLAGS_32BIT_MATCH): Updated.
- (cpu_flags_match): Likewise.
-
-2008-08-20 Alan Modra <amodra@bigpond.net.au>
-
- PR 6848
- * write.c (install_reloc): Check that reloc symbols have been
- written.
- (set_symtab): Mark symbols with BSF_KEEP.
-
-2008-08-18 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (i386_align_code): Fix a comment typo.
-
-2008-08-15 Alan Modra <amodra@bigpond.net.au>
-
- PR 6526
- * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
- * Makefile.in: Regenerate.
- * aclocal.m4: Regenerate.
- * config.in: Regenerate.
- * configure: Regenerate.
- * doc/Makefile.in: Regenerate.
-
-2008-08-14 Alan Modra <amodra@bigpond.net.au>
-
- * config/tc-tic4x.c (tic4x_operands_parse): Make static.
-
-2008-08-13 Ben Elliston <bje@au.ibm.com>
-
- * doc/as.texinfo (Align): Document the PowerPC behaviour.
-
-2008-08-13 Alan Modra <amodra@bigpond.net.au>
-
- * as.c, as.h, ecoff.c, hash.c, macro.c, symbols.c, config/obj-evax.c,
- config/obj-som.c, config/tc-alpha.c, config/tc-arm.c, config/tc-bfin.c,
- config/tc-bfin.h, config/tc-crx.c, config/tc-frv.c, config/tc-frv.h,
- config/tc-hppa.h, config/tc-i386.c, config/tc-i860.c, config/tc-i960.h,
- config/tc-ia64.c, config/tc-ia64.h, config/tc-m32c.c, config/tc-m32c.h,
- config/tc-m68k.c, config/tc-maxq.c, config/tc-s390.c, config/tc-s390.h,
- config/tc-sparc.c, config/tc-sparc.h, config/tc-spu.c, config/tc-spu.h,
- config/tc-tic4x.c, config/tc-tic4x.h, config/tc-tic54x.c,
- config/tc-tic54x.h, config/tc-vax.c, doc/internals.texi: Banish PARAMS
- and PTR. Convert to ISO C. Delete unnecessary forward declarations.
-
-2008-08-12 Alan Modra <amodra@bigpond.net.au>
-
- * config/tc-arm.c (s_unreq): Adjust hash_delete call.
- * config/tc-ia64.c (dot_rot): Likewise.
-
-2008-08-11 Alan Modra <amodra@bigpond.net.au>
-
- PR 6575
- * hash.c: Expand PTR to void *.
- (hash_delete): Add "freeme" parameter. Call obstack_free.
- * hash.h: Expand PTR to void *.
- (hash_delete): Update prototype.
- * macro.c (macro_expand_body): hash_delete LOCALs from formal_hash.
- * config/tc-tic54x.c (tic54x_remove_local_label): Update hash_delete
- call.
- (subsym_substitute): Likewise.
- * doc/internals.texi (hash_delete): Update.
-
-2008-08-08 Anatoly Sokolov <aesok@post.ru>
-
- * config/tc-avr.c (mcu_types): Add avr25, avr31, avr35, and avr51
- architectures. Reorganize list to put mcu types in correct
- architectures and to order list same as in GCC. Use new ISA
- definitions in include/opcode/avr.h.
- * doc/c-avr.texi: Add avr25, avr31, avr35, and avr51 architecture
- descriptions. Reorganize descriptions to put mcu types in correct
- architectures and to order lists same as in GCC.
-
-2008-08-08 Richard Sandiford <rdsandiford@googlemail.com>
- Daniel Jacobowitz <dan@codesourcery.com>
-
- * config/tc-mips.c (OPTION_CALL_NONPIC): New macro.
- (OPTION_NON_SHARED, OPTION_XGOT, OPTION_MABI, OPTION_32)
- (OPTION_N32, OPTION_64, OPTION_MDEBUG, OPTION_NO_MDEBUG)
- (OPTION_PDR, OPTION_NO_PDR, OPTION_MVXWORKS_PIC): Bump by 1.
- (md_longopts): Add -call_nonpic.
- (md_parse_option): Handle OPTION_CALL_NONPIC.
- (md_show_usage): Add -call_nonpic.
-
-2008-08-08 Sterling Augustine <sterling@tensilica.com>
-
- * config/tc-xtensa.c (exclude_section_from_property_tables): New.
- (xtensa_create_property_segments): Use it.
- (xtensa_create_xproperty_segments): Likewise.
-
-2008-08-08 Alan Modra <amodra@bigpond.net.au>
-
- * doc/internals.texi (DWARF2_FORMAT): Update for 2008-08-04 change.
-
-2008-08-06 Richard Sandiford <rdsandiford@googlemail.com>
-
- * config/tc-mips.c (mips16_reloc_p, got16_reloc_p, hi16_reloc_p)
- (lo16_reloc_p): New functions.
- (reloc_needs_lo_p): Use hi16_reloc_p and got16_reloc_p to
- generalize relocation checks.
- (matching_lo_reloc): New function.
- (fixup_has_matching_lo_p): Use it.
- (mips16_mark_labels): Don't clobber a symbol's visibility.
- (append_insn): Use hi16_reloc_p and lo16_reloc_p.
- (mips16_ip): Handle BFD_RELOC_MIPS16_GOT16 and BFD_RELOC_MIPS16_CALL16.
- (md_apply_fix): Likewise.
- (mips16_percent_op): Add %got and %call16.
- (mips_frob_file): Use got16_reloc_p to generalize relocation checks.
- Use matching_lo_reloc.
- (mips_force_relocation): Use hi16_reloc_p and lo16_reloc_p to
- generalize relocation checks.
- (mips_fix_adjustable): Use lo16_reloc_p to generalize relocation
- checks.
-
-2008-08-06 DJ Delorie <dj@redhat.com>
-
- * NEWS: Mention these changes.
-
- * config/tc-h8300.h (H_TICK_HEX): Define.
- * config/tc-h8300.c (OPTION_H_TICK_HEX): New.
- (md_longopts): Add "-h-tick-hex".
- (md_parse_option): Support it.
- * doc/c-h8300.texi (H8/300 Options): Document it.
- * doc/as.texinfo (Overview): Likewise.
-
- * config/tc-sh.h (H_TICK_HEX): Define.
- * config/tc-sh.c (OPTION_H_TICK_HEX): New.
- (md_longopts): Add "-h-tick-hex".
- (md_parse_option): Support it.
- * doc/c-sh.texi (SH Options): Document it.
- * doc/c-sh64.texi (SH64 Options): Document it.
- * doc/as.texinfo (Overview): Likewise.
-
-2008-08-05 Alan Modra <amodra@bigpond.net.au>
-
- PR gas/6656
- * dwarf2dbg.c (dwarf2_directive_file): Disable gas generated
- debug info if we see compiler generated debug info.
- (dwarf2_directive_loc): Likewise. Remove redundant debug_type test.
-
-2008-08-04 Alan Modra <amodra@bigpond.net.au>
-
- * dwarf2dbg.c: Remove superfluous forward function declarations.
- (DWARF2_FORMAT): Add section arg.
- (out_header): New function, split out from..
- (out_debug_line): ..here.
- (out_debug_aranges): Use out_header.
- (out_debug_abbrev): Add info_seg and line_seg args. Use
- DW_FORM_data8 (for DW_AT_stmt_list) if line_seg is 64-bit.
- (out_debug_info): Use out_header. Output 8 byte DW_AT_stmt_list
- if line_seg is 64-bit.
- (dwarf2_finish): Adjust out_debug_abbrev call.
- * config/tc-mips.h (DWARF2_FORMAT, mips_dwarf2_format): Add sec arg.
- * config/tc-mips.c (mips_dwarf2_format): Likewise.
-
-2008-08-04 Alan Modra <amodra@bigpond.net.au>
-
- * Makefile.am (POTFILES.in): Set LC_ALL=C.
- * Makefile.in: Regenerate.
- * po/POTFILES.in: Regenerate.
-
-2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
-
- * config/tc-ppc.c (parse_cpu): Rename altivec_or_spe to retain_flags.
- Handle -mvsx and -mpower7.
- (md_show_usage): Document -mpower7 and -mvsx.
- * doc/as.texinfo (Target PowerPC): Document -mvsx.
- * doc/c-ppc.texi (PowerPC-Opts): Document -mvsx and -mpower7.
-
-2008-07-31 Peter Bergner <bergner@vnet.ibm.com>
-
- * config/tc-ppc.c (parse_cpu) <power6>: Accept Altivec instructions.
- <cell>: Likewise.
-
-2008-07-30 Michael J. Eager <eager@eagercon.com>
-
- * config/tc-ppc.c (parse_cpu): Separate handling of -m403/405.
- (md_show_usage): Likewise.
-
-2008-07-30 Alan Modra <amodra@bigpond.net.au>
-
- * messages.c, symbols.c, write.c: Silence gcc warnings.
-
-2008-07-28 Ineiev <ineiev@yahoo.co.uk>
-
- * config/tc-i386.c (operand_type_check): Warning fix.
-
-2008-07-26 Michael Eager <eager@eagercon.com>
-
- * doc/as.texinfo: Add description of single-precision attribute.
-
-2008-07-24 Jie Zhang <jie.zhang@analog.com>
-
- * config/bfin-parse.y (asm_1): Error if plain symbol is used
- as load/store offset.
-
-2008-07-22 Chao-ying Fu <fu@mips.com>
-
- * config/tc-mips.c (mips_ip): Reset s to argsStart.
-
-2008-07-22 Jie Zhang <jie.zhang@analog.com>
-
- * config/tc-bfin.c (bfin_gen_loop): Remove loop symbol.
-
-2008-07-21 DJ Delorie <dj@redhat.com>
-
- * config/tc-h8300.c (fix_operand_size): Use the default size
- specified by the .lbranch/.sbranch pseudos.
-
-2008-07-18 DJ Delorie <dj@redhat.com>
-
- * config/tc-m32c.h (H_TICK_HEX): Define.
- * config/tc-m32c.c (OPTION_H_TICK_HEX): Define.
- (md_longopts): Add support for it.
- (md_parse_option): Likewise.
- * doc/as.texinfo (Overview): Add new m32c options.
- * doc/c-m32c.texi (M32C-Modifiers): Likewise
-
- * as.h: (enable_h_tick_hex): New.
- * app.c (enable_h_tick_hex): New.
- (LEX_IS_H): New.
- (do_scrub_begin): Mark 'H' and 'h' as special if enable_h_tick_hex.
- (do_scrub_chars): If enable_h_tick_hex and 'h', check for H'00
- style hex constants and convert the input stream to 0x00 style.
- (do_scrub_chars): If a 'X style character constant is found after
- a symbol character (like you're or X'00), warn the user.
-
-2008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
-
- * config/tc-mips.c (mips16_mark_labels): Use ELF_ST_SET_MIPS16.
- (mips_fix_adjustable): Likewise.
- (mips_frob_file_after_relocs): Likewise.
-
-2008-07-08 Nathan Sidwell <nathan@codesourcery.com>
-
- * config/tc-m68k.c (m68k_set_cpu, m68k_set_arch): Don't complain
- about overriding an earlier setting.
-
-2008-07-07 Adam Nemet <anemet@caviumnetworks.com>
-
- * config/tc-mips.c (NO_ISA_COP): New macro.
- (COP_INSN): New macro.
- (is_opcode_valid): Use them.
- (macro) <ld_st>: Use them. Don't accept coprocessor load store
- insns based on the ISA if CPU is NO_ISA_COP.
- <copz>: Likewise for coprocessor operations.
-
-2008-07-07 Paul Brook <paul@codesourcery.com>
-
- * config/tc-arm.c (arm_fix_adjustable): Don't adjust MOVW/MOVT
- relocations.
-
-2008-07-07 Ralf Corsépius <ralf.corsepius@rtems.org>
-
- * configure.tgt: Add bfin-*-rtems*.
-
-2008-07-04 Alan Modra <amodra@bigpond.net.au>
+2009-01-05 H.J. Lu <hongjiu.lu@intel.com>
- * config/tc-spu.c (md_apply_fix): Handle fully resolved
- BFD_RELOC_32_PCREL, BFD_RELOC_SPU_HI16 and BFD_RELOC_SPU_LO16.
+ AVX Programming Reference (December, 2008)
+ * config/tc-i386.c (build_modrm_byte): Remove 5 operand instruction
+ support. Don't swap REG and NDS for FMA.
-2008-06-25 Peter Bergner <bergner@vnet.ibm.com>
-
- * config/tc-ppc.c (parse_cpu): Handle -m464.
- (md_show_usage): Likewise.
-
-2008-06-24 Eric B. Weddington <eric.weddington@atmel.com>
-
- Add support for ATtiny13A.
- * config/tc-avr.c (mcu_types): Add attiny13a.
- * doc/c-avr.texi: Likewise.
-
-2008-06-24 Bob Wilson <bob.wilson@acm.org>
- Alan Modra <amodra@bigpond.net.au>
-
- * write.c (relax_segment <rs_org>): Include current stretch
- value when calculating whether .org is backwards.
-
-2008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
-
- * configure: Regenerate.
-
-2008-06-17 Nick Clifton <nickc@redhat.com>
-
- * app.c (do_scrub_chars): Do not UNGET an EOF value.
-
-2008-06-16 Hans-Peter Nilsson <hp@bitrange.com>
-
- PR gas/6607
- * config/tc-mmix.c (s_loc): Assume "negative" addresses belong to
- text_section. Do the "stepping backwards" test for text_section
- using unsigned operands.
-
-2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
-
- * config/tc-ppc.c (ppc_cpu): Use ppc_cpu_t typedef.
- (ppc_insert_operand): Likewise.
- (ppc_machine): Likewise.
- * config/tc-ppc.h: #include "opcode/ppc.h"
- (struct _ppc_fix_extra <ppc_cpu>): Use ppc_cpu_t typedef.
- (ppc_cpu): Update extern decl.
-
-2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
-
- * config/tc-mips.c (validate_mips_insn): Handle field descriptors
- +x, +X, +p, +P, +s, +S.
- (mips_ip): Likewise.
-
- * config/tc-mips.c (validate_mips_insn): Handle field descriptor +Q.
- (mips_ip): Likewise.
- (macro_build): Likewise.
- (CPU_HAS_SEQ): New macro.
- (macro2) <M_SEQ_I, M_SNE_I>: Use it. Emit seq/sne and seqi/snei.
-
-2008-06-09 Eric B. Weddington <eric.weddington@atmel.com>
-
- * config/tc-avr.c (mcu_types): Remove support for ATmega32HVB device.
- * doc/c-avr.texi: Likewise.
-
-2008-06-04 Nick Clifton <nickc@redhat.com>
-
- * app.c (do_scrub_chars): Do not UNGET an EOF value.
-
-2008-06-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (set_sse_check): New.
- (md_pseudo_table): Add "sse_check".
-
-2008-06-03 Paul Brook <paul@codesourcery.com>
-
- * config/tc-arm.c (do_t_rbit): Populate both rm fields.
-
-2008-05-30 Nick Clifton <nickc@redhat.com>
-
- PR 5523
- * config/tc-avr.c (avr_ldi_expression): Do not warn about unknown
- relocs here.
-
-2008-05-29 Maxim Kuvyrkov <maxim@codesourcery.com>
-
- * config/tc-mips.c (mips_cpu_info_table): Move records for
- ST Loongson-2E/2F processors to a better place.
-
-2008-05-23 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/6518
- * config/tc-i386.c (match_template): Report ambiguous operand
- size, not invalid suffix when there is no match in Intel
- syntax.
-
-2008-05-22 Paul Brook <paul@codesourcery.com>
-
- * config/tc-arm.c (parse_cond): Covert to lowercase before matching.
-
-2008-05-21 I-Jui Sung <ijsung@gmail.com>
-
- * config/tc-arm.c (arm_cpus): Add Faraday ARMv4 and ARMv5TE
- compatible cores: fa526, fa626, fa626te, fa726te.
- * doc/c-arm.texi (ARM Opts): Add -mcpu={fa526, fa626, fa626te,
- fa726te} options.
-
-2008-05-14 Alan Modra <amodra@bigpond.net.au>
-
- * Makefile.am: Run "make dep-am".
- * Makefile.in: Regenerate.
- * doc/Makefile.in: Regenerate.
- * po/POTFILES.in: Regenerate.
-
-2008-05-09 Catherine Moore <clm@codesourcery.com>
-
- * config/tc-mips.c (mips_frob_file): Don't match MIPS16 relocs
- with non-MIPS16 relocs.
-
-2008-05-09 Chao-ying Fu <fu@mips.com>
-
- * config/tc-mips.c (md_begin): Use strncmp to compare TARGET_OS, in
- case that some characters append at the end of the name.
- (mips_ip): Likewise.
- (s_change_sec): Likewise.
- (md_section_align): Likewise.
-
-2008-05-07 Bob Wilson <bob.wilson@acm.org>
-
- * config/tc-xtensa.c (xtensa_create_property_segments): Use
- xtensa_make_property_section instead of xtensa_get_property_section.
- (xtensa_create_xproperty_segments): Likewise.
-
-2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
-
- * NEWS: Mention XSAVE, EPT and MOVBE.
-
- * config/tc-i386.c (cpu_arch): Add .movbe and .ept.
- (md_show_usage): Add .movbe and .ept.
-
- * doc/c-i386.texi: Add movbe and ept to -march=. Document
- .movbe and .ept.
-
-2008-04-29 David S. Miller <davem@davemloft.net>
-
- * config/tc-sparc.c (v9a_asr_table): Fix order of softint entries.
-
-2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
-
- * config/tc-mips.c (file_mips_soft_float, file_mips_single_float):
- New statics.
- (OPTION_ELF_BASE): Make room for new option macros.
- (OPTION_SOFT_FLOAT, OPTION_HARD_FLOAT, OPTION_SINGLE_FLOAT,
- OPTION_DOUBLE_FLOAT): New option macros.
- (md_longopts): Add msoft-float, mhard-float, msingle-float and
- mdouble-float.
- (md_parse_option): Handle OPTION_SINGLE_FLOAT,
- OPTION_DOUBLE_FLOAT, OPTION_SOFT_FLOAT and OPTION_HARD_FLOAT.
- (md_show_usage): Add -msoft-float, -mhard-float, -msingle-float
- and -mdouble-float.
- (struct mips_set_options): New fields soft_float and single_float.
- (mips_opts): Initialized them. Add comment for each field
- initializer.
- (mips_after_parse_args): Set them based on file_mips_soft_float
- and file_mips_single_float.
- (s_mipsset): Add support for `.set softfloat', `.set hardfloat',
- `.set singlefloat' and `.set doublefloat'.
- (is_opcode_valid): New function to invoke OPCODE_IS_MEMBER.
- Handle single-float and soft-float instructions here.
- (macro_build, mips_ip): Use it instead of OPCODE_IS_MEMBER.
- (is_opcode_valid_16): New function.
- (mips16_ip): Use it instead of OPCODE_IS_MEMBER.
- (macro) <M_LDC1_AB, M_SDC1_AB, M_L_DOB, M_L_DAB, M_S_DAB,
- M_S_DOB>: Remove special-casing of r4650.
- * doc/c-mips.texi (-march=): Add Octeon.
- (MIPS Opts): Document -msoft-float and -mhard-float. Document
- -msingle-float and -mdouble-float.
- (MIPS floating-point): New section. Document `.set softfloat' and
- `.set hardfloat'. Document `.set singlefloat' and `.set
- doublefloat'.
-
-2008-04-25 David S. Miller <davem@davemloft.net>
-
- * config/tc-sparc.c: Accept 'softint_clear' and 'softint_set'
- %asr aliases.
-
- * doc/c-sparc.texi: Consistently refer to architecture 'versions',
- rather than occaisionally 'levels'. Consistently refer to Sun's
- UNIX variant as SunOS, every version of Solaris is also SunOS.
- Document new 'softint_clear' and 'softint_set' aliases. Clarify
- which architecture versions support '%dcr', '%cq', and '%gl'. Add
- section on 32-bit/64-bit opcode translations.
-
-2008-04-23 Mike Frysinger <vapier@gentoo.org>
-
- * Makefile.am (OBJ_FORMAT_CFILES): Add config/obj-fdpicelf.c.
- (OBJ_FORMAT_HFILES): Add config/obj-fdpicelf.h.
- (obj-fdpicelf.o): Define.
- * Makefile.in: Regenerate.
- * configure.tgt: Set bfd_gas to yes when fmt is fdpicelf.
- (bfin-*-*): Delete.
- (bfin-*-linux-uclibc): New; set fmt to fdpicelf and em to linux.
- (bfin-*-uclinux*): New; set fmt to elf and em to linux.
- * config/obj-fdpicelf.c: New.
- * config/obj-fdpicelf.h: Likewise.
- * config/tc-bfin.c (bfin_flags, bfin_pic_flag): Set default based on
- the OBJ_FDPIC_ELF define.
- (OPTION_NOPIC): Define.
- (md_longopts): Add mnopic and mno-fdpic.
- (md_parse_option): Handle OPTION_NOPIC.
-
-2008-04-23 Paolo Bonzini <bonzini@gnu.org>
-
- * aclocal.m4: Regenerate.
- * configure: Regenerate.
-
-2008-04-23 David S. Miller <davem@davemloft.net>
-
- * config/tc-sparc.c (v9a_asr_table): Add missing
- 'stick' and 'stick_cmpr', and document ordering rules
- of table.
- (tc_gen_reloc): Accept BFD_RELOC_SPARC_PC22 and
- BFD_RELOC_SPARC_PC10.
- * doc/c-sparc.texi: New section on Sparc constants.
- Add documentation for %stick and %stick_cmpr.
-
-2008-04-22 David S. Miller <davem@davemloft.net>
-
- * config/obj-elf.c (obj_elf_section_type): Add prototype
- before obj_elf_section_word and add 'warn' arg.
- (obj_elf_section_word): Add type pointer arg, and if no #SECTION
- is matched, try checking for #SECTION_TYPE.
- (obj_elf_section): Adjust for new args.
- (obj_elf_type_name): New function.
- (obj_elf_type): Call it, and accept STT_foo number strings
- in .type statements as output by SunPRO compiler.
-
-2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (md_assemble): Don't check SSE instructions
- if noavx is 0.
-
-2008-04-18 David S. Miller <davem@davemloft.net>
-
- * doc/c-sparc.texi: Add syntax section.
-
-2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (build_modrm_byte): Don't check FMA to swap
- REG and NDS for instructions with immediate operand.
-
-2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (build_modrm_byte): Swap REG and NDS for
- FMA.
-
-2008-04-16 David S. Miller <davem@davemloft.net>
-
- * config/tc-sparc.c (sparc_ip): Add support for gotdata mnemonics
- and relocation generation.
- (tc_gen_reloc): Likewise.
-
-2008-04-15 Andrew Stubbs <andrew.stubbs@st.com>
-
- * config/tc-sh.c (md_apply_fix): Make sure BFD_RELOC_SH_PCRELIMM8BY4
- relocations are properly aligned, and not negative.
-
-2008-04-15 Khem Raj <kraj@mvista.com>
-
- * doc/tc-arm.texi: Fix fnstart and fnend directive names.
-
-2008-04-14 Edmar Wienskoski <edmar@freescale.com>
-
- * config/tc-ppc.c (parse_cpu): Handle "e500mc". Extend "e500" to
- accept e500mc instructions.
- (md_show_usage): Document -me500mc.
-
-2008-04-11 Nick Clifton <nickc@redhat.com>
-
- * listing.c (print_timestamp): Use localtime rather than
- localtime_r since not all build environments provide the latter.
-
-2008-04-10 H.J. Lu <hongjiu.lu@intel.com>
-
- * NEWS: Mention -msse-check=[none|error|warning].
-
- * config/tc-i386.c (sse_check): New.
- (OPTION_MSSE_CHECK): Likewise.
- (md_assemble): Check SSE instructions if needed.
- (md_longopts): Add -msse-check.
- (md_parse_option): Handle OPTION_MSSE_CHECK.
- (md_show_usage): Show -msse-check=[none|error|warning].
-
- * doc/c-i386.texi: Document -msse-check=[none|error|warning].
-
-2008-04-10 Santiago Urueña <suruena@gmail.com>
-
- * listing.c: Add -ag listing flag to show general information in
- listings such as gas version, passed options, and time stamp.
- (listing_general_info): New function.
- (print_options): New function.
- (print_single_option): New function.
- (print_timestamp): New function.
- (MAX_DATELEN): Define.
- (listing_print): Add call to listing_general_info.
- * listing.h (LISTING_GENERAL): Define.
- (listing_print): Add new parameter.
- * as.c (show_usage): Print new switch.
- (parse_args): Parse new switch.
- (main): Pass command line on to listing_print.
- * NEWS: Mention this new feature.
- * doc/as.texinfo: Document the new sub-option.
-
-2008-04-08 Alan Modra <amodra@bigpond.net.au>
-
- * dwarf2dbg.c (dwarf2_emit_insn): Simplify test before dwarf2_where
- call. Delete out of date comment.
- (dwarf2_consume_line_info): Always clear dwarf2_loc_directive_seen.
- (dwarf2_emit_label): Don't emit unless there has been a previous
- .file or we are outputting assembler generated debug.
- dwarf2_consume_line_info after emitting line info, not before.
- (out_debug_info): Simplify files_in_use test.
-
-2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (parse_real_register): Return AVX register
- only if AVX is enabled.
-
-2008-04-07 Kaz Kojima <kkojima@rr.iij4u.or.jp>
-
- PR gas/6043
- * config/tc-sh64.c (shmedia_md_pcrel_from_section): Use
- md_pcrel_from_section for BFD_RELOC_64 and BFD_RELOC_64_PCREL.
-
-2008-04-04 Adrian Bunk <bunk@stusta.de>
- Bob Wilson <bob.wilson@acm.org>
-
- * config/tc-xtensa.c (xg_apply_fix_value): Check return code from
- call to decode_reloc.
-
-2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
-
- * NEWS: Mention XSAVE. Change CLMUL to PCLMUL.
-
- * config/tc-i386.c (cpu_arch): Add .pclmul.
- (md_show_usage): Replace clmul with pclmul.
- * doc/c-i386.texi: Likewise.
-
-2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
-
- * doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
- Document -msse2avx, .avx, .aes, .clmul and .fma.
-
- * config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
- (vex_prefix): Likewise.
- (sse2avx): Likewise.
- (CPU_FLAGS_ARCH_MATCH): Likewise.
- (CPU_FLAGS_64BIT_MATCH): Likewise.
- (CPU_FLAGS_32BIT_MATCH): Likewise.
- (CPU_FLAGS_PERFECT_MATCH): Likewise.
- (regymm): Likewise.
- (vex_imm4): Likewise.
- (fits_in_imm4): Likewise.
- (build_vex_prefix): Likewise.
- (VEX_check_operands): Likewise.
- (bad_implicit_operand): Likewise.
- (OPTION_MSSE2AVX): Likewise.
- (T_YMMWORD): Likewise.
- (_i386_insn): Add vex.
- (cpu_arch): Add .avx, .aes, .clmul and .fma.
- (cpu_flags_match): Changed to take a pointer to const template.
- Enable encoding SSE instructions with VEX prefix for -msse2avx.
- (match_mem_size): Also check ymmword.
- (operand_type_match): Clear ymmword.
- (md_begin): Allow '_' in mnemonic.
- (type_names): Add OPERAND_TYPE_VEX_IMM4.
- (process_immext): Update assert.
- (md_assemble): Don't call process_immext if sse2avx and immext
- are true. Call build_vex_prefix if vex is true.
- (parse_insn): Updated for cpu_flags_match.
- (swap_operands): Handle 5 operands.
- (match_template): Handle 5 operands. Updated for cpu_flags_match.
- Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
- (process_suffix): Handle YMMWORD_MNEM_SUFFIX.
- (check_byte_reg): Check regymm.
- (process_operands): Duplicate the destination register for
- -msse2avx if needed.
- (build_modrm_byte): Updated for instructions with VEX encoding.
- (output_insn): Output VEX prefix if needed.
- (md_longopts): Add msse2avx.
- (md_parse_option): Handle OPTION_MSSE2AVX.
- (md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
- (intel_e09): Support YMMWORD.
- (intel_e11): Likewise.
- (intel_get_token): Likewise.
-
-2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
-
- * config/tc-avr.c (mcu_types): Add attiny167.
- * doc/c-avr.texi: Likewise.
-
-2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
-
- * config/tc-avr.c (mcu_types): Add atmega32u4.
- * doc/c-avr.texi: Likewise.
-
-2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
-
- * config/tc-avr.c (mcu_types): Add atmega32c1.
- * doc/c-avr.texi: Likewise.
-
-2008-03-28 Paul Brook <paul@codesourcery.com>
-
- * config/tc-arm.c (parse_neon_mov): Parse register before immediate
- to avoid spurious symbols.
-
-2008-03-28 Nathan Sidwell <nathan@codesourcery.com>
-
- * config/tc-m68k.c (md_convert_frag_1): Replace as_fatal with
- as_bad_where.
-
-2008-03-27 Eric B. Weddington <eric.weddington@atmel.com>
-
- * config/tc-avr.c (mcu_types): Add atmega32m1.
- * doc/c-avr.texi: Likewise.
-
-2008-03-27 Ineiev <ineiev@yahoo.co.uk>
-
- * config/tc-arm.c (do_neon_cvt): Move variable declarations to
- start of block.
- (do_neon_ext): Fix sign of comparison.
-
-2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
-
- From Jie Zhang <jie.zhang@analog.com>
- * config/bfin-parse.y (asm_1): Check AREGS in comparison
- instructions. And call yyerror when comparing PREG with
- DREG.
- (check_macfunc_option): New.
- (check_macfuncs): Check option by calling check_macfunc_option.
- Fix comparison always true warnings. Both scalar instructions
- of vector instruction must share the same mode option. Only allow
- option mode at the end of the second instruction of the vector.
- (asm_1): Check option by calling check_macfunc_option.
-
- * config/bfin-parse.y (check_macfunc_option): Allow (IU)
- option for multiply and multiply-accumulate to data register
- instruction.
- (check_macfuncs): Don't check if accumulator matches the data register
- here.
- (assign_macfunc): Check if accumulator matches the
- data register in each rule that moves to the data
- register.
-
- * config/tc-bfin.c (bfin_start_line_hook): Localize the labels
- generated for LOOP_BEGIN and LOOP_END instructions.
- (bfin_gen_loop): Likewise.
-
-2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
-
- * config/tc-s390.c (md_parse_option): z10 option added.
-
-2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
-
- * aclocal.m4: Regenerate.
- * configure: Likewise.
- * Makefile.in: Likewise.
- * doc/Makefile.in: Likewise.
-
-2008-03-17 Adrian Bunk <bunk@stusta.de>
-
- PR 5946
- * config/tc-hppa.c (is_same_frag): Delete.
-
-2008-03-14 Sterling Augustine <sterling@tensilica.com>
-
- * config/tc-xtensa.h (xtensa_relax_statesE): Update comment for
- RELAX_LOOP_END_ADD_NOP.
-
-2008-03-13 Evandro Menezes <evandro@yahoo.com>
-
- PR gas/5895
- * read.c (s_mexit): Warn if attempting to exit a macro when not
- inside a macro definition.
-
-2008-03-13 Alan Modra <amodra@bigpond.net.au>
-
- * Makefile.am: Run "make dep-am".
- * Makefile.in: Regenerate.
- * configure: Regenerate.
-
-2008-03-09 Paul Brook <paul@codesourcery.com>
-
- * config/tc-arm.c (arm_cpu_option_table): Add cortex-a9.
- * doc/c-arm.texi: Add cortex-a9.
-
-2008-03-09 Paul Brook <paul@codesourcery.com>
-
- * config/tc-arm.c (fpu_vfp_ext_d32): New vairable.
- (parse_vfp_reg_list, encode_arm_vfp_reg): Use it.
- (arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3.
- (aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16.
- * doc/c-arm.texi: Document new ARM FPU variants.
-
-2008-03-07 Paul Brook <paul@codesourcery.com>
-
- * config/tc-arm.c (md_apply_fix): Use correct offset range.
-
-2008-03-07 Alan Modra <amodra@bigpond.net.au>
-
- * config/tc-ppc.c (ppc_setup_opcodes): Tidy. Add code to test
- for strict ordering of powerpc_opcodes, but disable for now.
-
-2008-03-04 Paul Brook <paul@codesourcery.com>
-
- * config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New.
- (arm_ext_v7m): Rename...
- (arm_ext_m): ... to this. Include v6-M.
- (do_t_add_sub): Allow narrow low-reg non flag setting adds.
- (do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m.
- (md_assemble): Allow wide msr instructions.
- (insns): Add classifications for v6-m instructions.
- (arm_cpu_option_table): Add cortex-m1.
- (arm_arch_option_table): Add armv6-m.
- (cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants.
-
-2008-03-03 Sterling Augustine <sterling@tensilica.com>
- Bob Wilson <bob.wilson@acm.org>
-
- * config/tc-xtensa.c (xtensa_num_pipe_stages): New.
- (md_begin): Initialize it.
- (resources_conflict): Use it.
-
-2008-03-03 Sterling Augustine <sterling@tensilica.com>
-
- * config/tc-xtensa.h (RELAX_XTENSA_NONE): New.
-
-2008-03-03 Denys Vlasenko <vda.linux@googlemail.com>
- H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/5543
- * read.c (pseudo_set): Don't allow global register symbol.
-
- * symbols.c (S_SET_EXTERNAL): Don't allow register symbol
- global.
-
-2008-03-03 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/5543
- * write.c (write_object_file): Don't allow symbols which were
- equated to register. Stop if there is an error.
-
-2008-03-01 Alan Modra <amodra@bigpond.net.au>
-
- * config/tc-ppc.h (struct _ppc_fix_extra): New.
- (ppc_cpu): Declare.
- (TC_FIX_TYPE, TC_INIT_FIX_DATA): Define.
- * config/tc-ppc.c (ppu_cpu): Make global.
- (ppc_insert_operand): Add ppu_cpu parameter.
- (md_assemble): Adjust for above change.
- (md_apply_fix): Pass tc_fix_data.ppc_cpu to ppc_insert_operand.
-
-2008-02-22 Nick Clifton <nickc@redhat.com>
-
- * config/tc-arm.c (do_bx): Only test EF_ARM_EABI_VERSION on ELF
- targeted ARM ports, otherwise just skip generating the reloc.
-
-2008-02-18 H.J. Lu <hongjiu.lu@intel.com>
-
- * doc/c-i386.texi: Update -march= and .arch.
-
-2008-02-18 Nick Clifton <nickc@redhat.com>
-
- * config/tc-mn10300.c (has_known_symbol_location): New function.
- Do not regard weak symbols as having a known location.
- (md_estimate_size_before_relax): Use new function.
- (md_pcrel_from): Do not compute a pcrel against a weak symbol.
-
-2008-02-18 Jan Beulich <jbeulich@novell.com>
-
- * config/tc-i386.c (match_template): Disallow 'l' suffix when
- currently selected CPU has no 32-bit support.
- (parse_real_register): Do not return registers not available on
- currently selected CPU.
-
-2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (process_immext): Fix format.
-
-2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (inoutportreg): New.
- (process_immext): New.
- (md_assemble): Use it.
- (update_imm): Use imm16 and imm32s.
- (i386_att_operand): Use inoutportreg.
-
-2008-02-14 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (operand_type_all_zero): New.
- (operand_type_set): Likewise.
- (operand_type_equal): Likewise.
- (cpu_flags_all_zero): Likewise.
- (cpu_flags_set): Likewise.
- (cpu_flags_equal): Likewise.
- (UINTS_ALL_ZERO): Removed.
- (UINTS_SET): Likewise.
- (UINTS_CLEAR): Likewise.
- (UINTS_EQUAL): Likewise.
- (cpu_flags_match): Updated.
- (smallest_imm_type): Likewise.
- (set_cpu_arch): Likewise.
- (md_assemble): Likewise.
- (optimize_imm): Likewise.
- (match_template): Likewise.
- (process_suffix): Likewise.
- (update_imm): Likewise.
- (process_drex): Likewise.
- (process_operands): Likewise.
- (build_modrm_byte): Likewise.
- (i386_immediate): Likewise.
- (i386_displacement): Likewise.
- (i386_att_operand): Likewise.
- (parse_real_register): Likewise.
- (md_parse_option): Likewise.
- (i386_target_format): Likewise.
-
-2008-02-14 Dimitry Andric <dimitry@andric.com>
-
- PR gas/5712
- * config/tc-arm.c (s_arm_unwind_save): Advance the input line
- pointer past the comma after parsing a floating point register
- name.
-
-2008-02-14 Hakan Ardo <hakan@debian.org>
-
- PR gas/2626
- * config/tc-avr.c (mcu_types): Change the ISA tyoe of the attiny26
- to AVR_ISA_2xxe.
- (avr_operand): Disallow post-increment addressing in the lpm
- instruction for the attiny26.
-
-2008-02-13 Jan Beulich <jbeulich@novell.com>
-
- * config/tc-i386.c (parse_real_register): Don't return 'FLAT'
- if not in Intel mode.
- (i386_intel_operand): Ignore segment overrides in immediate and
- offset operands.
- (intel_e11): Range-check i.mem_operands before use as array
- index. Filter out FLAT for uses other than as segment override.
- (intel_get_token): Remove broken promotion of "FLAT:" to mean
- "offset FLAT:".
-
-2008-02-13 Jan Beulich <jbeulich@novell.com>
-
- * config/tc-i386.c (intel_e09): Also special-case 'bound'.
-
-2008-02-13 Jan Beulich <jbeulich@novell.com>
-
- * config/tc-i386.c (allow_pseudo_reg): New.
- (parse_real_register): Check for NULL just once. Allow all
- register table entries when allow_pseudo_reg is non-zero.
- Don't allow any registers without type when allow_pseudo_reg
- is zero.
- (tc_x86_regname_to_dw2regnum): Replace with ...
- (tc_x86_parse_to_dw2regnum): ... this.
- (tc_x86_frame_initial_instructions): Adjust for above change.
- * config/tc-i386.h (tc_regname_to_dw2regnum): Remove.
- (tc_parse_to_dw2regnum): New.
- (tc_x86_regname_to_dw2regnum): Replace with ...
- (tc_x86_parse_to_dw2regnum): ... this.
- * dw2gencfi.c (tc_parse_to_dw2regnum): New, broken out of ...
- (cfi_parse_reg): ... this. Use tc_parse_to_dw2regnum. Adjust
- error handling.
-
-2008-02-12 Nick Clifton <nickc@redhat.com>
-
- * config/tc-tic4x.c (tic4x_insn_insert): Add const qualifier to
- argument.
- (tic4x_insn_add): Likewise.
- (md_begin): Drop cast that was discarding a const qualifier.
- * config/tc-d30v.c (get_reloc): Add const qualifier to op
- argument.
- (build_insn): Drop cast that was discarding a const qualifier.
-
-2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (cpu_arch): Add .xsave.
- (md_show_usage): Add .xsave.
-
- * doc/c-i386.texi: Add xsave to -march=.
-
-2008-02-07 Alan Modra <amodra@bigpond.net.au>
-
- * read.c (s_weakref): Don't pass unadorned NULL to concat.
- * config/tc-i386.c (set_cpu_arch, md_parse_option): Likewise.
-
-2008-02-05 Sterling Augustine <sterling@tensilica.com>
-
- * config/tc-xtensa.c (relax_frag_immed): Change internal consistency
- checks into assertions. When relaxation produces an operation that
- does not fit in the current FLIX instruction, make sure that the
- operation is relaxed as needed to account for being placed following
- the current instruction.
-
-2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
-
- PR 5715
- * configure: Regenerated.
-
-2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
-
- * config/tc-mips.c (mips_cpu_info_table): Add Octeon.
-
-2008-01-31 Marc Gauthier <marc@tensilica.com>
-
- * configure.tgt (xtensa*-*-*): Recognize processor variants.
-
-2008-01-25 Kai Tietz <kai.tietz@onevision.com>
-
- * read.c: (emit_expr): Correct for mingw use of printf size
- specifier.
-
-2008-01-24 Bob Wilson <bob.wilson@acm.org>
-
- * doc/c-xtensa.texi (Xtensa Syntax): Clarify handling of opcodes that
- can only be encoded in FLIX instructions but are not specified as such.
- (Xtensa Automatic Alignment): Remove obsolete comment about debugging
- labels.
-
-2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
-
- * NEWS: Mention new command line options for x86 targets.
-
-2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (md_show_usage): Replace tabs with spaces.
-
-2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
-
- * config/tc-avr.c (mcu_types): Change opcode set for at86rf401.
-
-2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (md_show_usage): Show more processors for
- -march=/-mtune=.
-
-2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (i386_target_format): Remove cpummx2.
-
-2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (XXX_PREFIX): Moved from tc-i386.h.
- (XXX_MNEM_SUFFIX): Likewise.
- (END_OF_INSN): Likewise.
- (templates): Likewise.
- (modrm_byte): Likewise.
- (rex_byte): Likewise.
- (DREX_XXX): Likewise.
- (drex_byte): Likewise.
- (sib_byte): Likewise.
- (processor_type): Likewise.
- (arch_entry): Likewise.
- (cpu_sub_arch_name): Remove const.
- (cpu_arch): Add .vmx and .smx.
- (set_cpu_arch): Append cpu_sub_arch_name.
- (md_parse_option): Support -march=CPU[,+EXTENSION...].
- (md_show_usage): Updated.
-
- * config/tc-i386.h (XXX_PREFIX): Moved to tc-i386.c.
- (XXX_MNEM_SUFFIX): Likewise.
- (END_OF_INSN): Likewise.
- (templates): Likewise.
- (modrm_byte): Likewise.
- (rex_byte): Likewise.
- (DREX_XXX): Likewise.
- (drex_byte): Likewise.
- (sib_byte): Likewise.
- (processor_type): Likewise.
- (arch_entry): Likewise.
-
- * doc/as.texinfo: Update i386 -march option.
-
- * doc/c-i386.texi: Update -march= for ISA.
-
-2008-01-18 Bob Wilson <bob.wilson@acm.org>
-
- * config/tc-xtensa.c (xtensa_leb128): New function.
- (md_pseudo_table): Use it for sleb128 and uleb128.
- (is_leb128_expr): New internal flag.
- (xtensa_symbol_new_hook): Check new flag.
-
-2008-01-16 Eric B. Weddington <eric.weddington@atmel.com>
-
- * config/tc-avr.c (mcu_types): Change opcode set for avr3,
- at90usb82, at90usb162.
- * doc/c-avr.texi: Change architecture grouping for at90usb82,
- at90usb162.
- These changes support the new avr35 architecture group in gcc.
-
-2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (md_assemble): Also zap movzx and movsx
- suffix for AT&T syntax.
-
-2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (match_reg_size): New.
- (match_mem_size): Likewise.
- (operand_size_match): Likewise.
- (operand_type_match): Also clear all size fields.
- (match_template): Skip Intel syntax when in AT&T syntax.
- Call operand_size_match to check operand size.
- (i386_att_operand): Set the mem field to 1 for memory
- operand.
- (i386_intel_operand): Likewise.
-
-2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/5534
- * config/tc-i386.c (_i386_insn): Update comment.
- (operand_type_match): Also clear unspecified.
- (operand_type_register_match): Likewise.
- (parse_operands): Initialize unspecified.
- (i386_intel_operand): Likewise.
- (match_template): Check memory and accumulator operand size.
- (i386_att_operand): Clear unspecified on register operand.
- (intel_e11): Likewise.
- (intel_e09): Set operand size and clean unspecified for
- "XXX PTR".
-
-2008-01-11 Andreas Schwab <schwab@suse.de>
-
- * read.c (s_space): Declare `repeat' as offsetT.
-
-2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (match_template): Check processor support
- first.
-
-2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (match_template): Continue if processor
- doesn't match.
-
-2008-01-09 Alexandre Oliva <aoliva@redhat.com>
-
- * config/tc-ia64.c (ia64_convert_frag): Zero-initialize room for
- unwind personality function address.
-
-2008-01-09 Bob Wilson <bob.wilson@acm.org>
-
- * dwarf2dbg.c (out_sleb128): Delete.
- (size_fixed_inc_line_addr, emit_fixed_inc_line_addr): New.
- (out_fixed_inc_line_addr): Delete.
- (relax_inc_line_addr, dwarf2dbg_estimate_size_before_relax): Call new
- size_fixed_inc_line_addr if DWARF2_USE_FIXED_ADVANCE_PC is set.
- (dwarf2dbg_convert_frag): Likewise for emit_fixed_inc_line_addr.
- (process_entries): Remove calls to out_fixed_inc_line_addr. When
- DWARF2_USE_FIXED_ADVANCE_PC is set, call relax_inc_line_addr.
- * read.h (emit_expr_fix): New prototype.
- * read.c (emit_expr): Move code to emit_expr_fix and use it here.
- (emit_expr_fix): New.
-
-2008-01-09 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (match_template): Check register size
- only when size of operands can be encoded the canonical way.
-
-2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (i386_operand): Renamed to ...
- (i386_att_operand): This.
- (parse_operands): Updated.
-
-2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
-
- * doc/c-i386.texi: Update .att_mnemonic and .intel_mnemonic.
-
- * config/tc-i386.c (set_intel_mnemonic): Set intel_mnemonic
- only.
- (md_assemble): Remove Intel mode workaround.
- (match_template): Check support for old gcc, AT&T mnemonic
- and Intel Syntax.
- (md_parse_option): Don't set intel_mnemonic to 0 for
- OPTION_MOLD_GCC.
-
-2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.h: Update copyright to 2008.
-
-2008-01-04 Nick Clifton <nickc@redhat.com>
-
- * config/tc-ppc.c (parse_cpu): Preserve the settings of the
- PPC_OPCODE_ALTIVEC and PPC_OPCODE_SPE flags.
-
-2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (md_assemble): Use !intel_mnemonic instead
- of SYSV386_COMPAT.
-
-2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/config/tc-i386.c (cpu_arch_flags_not): Removed.
- (cpu_flags_not): Likewise.
- (cpu_flags_match): Updated to check 64bit and arch.
- (set_code_flag): Remove cpu_arch_flags_not.
- (set_16bit_gcc_code_flag): Likewise.
- (set_cpu_arch): Likewise.
- (md_begin): Likewise.
- (parse_insn): Call cpu_flags_match to check 64bit and arch.
- (match_template): Likewise.
-
-2008-01-03 Jakub Jelinek <jakub@redhat.com>
-
- * config/tc-i386.c (process_drex): Initialize modrm_reg and
- modrm_regmem to 0 instead of None.
-
-2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (match_template): Use the xmmword field
- instead of no_xsuf.
-
-2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
-
- * config/tc-i386.c (process_suffix): Fix a typo.
-
-2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/5534
- * config/tc-i386.c (match_template): Handle XMMWORD_MNEM_SUFFIX.
- Check memory size in Intel mode.
- (process_suffix): Handle XMMWORD_MNEM_SUFFIX.
- (intel_e09): Likewise.
-
- * config/tc-i386.h (XMMWORD_MNEM_SUFFIX): New.
-
-2008-01-02 Catherine Moore <clm@codesourcery.com>
+2009-01-02 Matthias Klose <doko@ubuntu.com>
- * config/tc-mips.c (mips_ip): Check operands on jalr instruction.
+ * itbl-ops.c (itbl_disassemble): Don't rely on undefined sprintf
+ behaviour.
-For older changes see ChangeLog-2007
+For older changes see ChangeLog-2008
\f
Local Variables:
mode: change-log
--- /dev/null
+2008-12-23 Jon Beniston <jon@beniston.com>
+
+ * NEWS: Record that support for LM32 has been added.
+ * Makefile.am: Add LM32 object files and dependencies.
+ * Makefile.in: Regenerate.
+ * configure.in: Indicate LM32 uses cgen.
+ * configure: Regenerate.
+ * configure.tgt: Add LM32 target.
+ * config/tc-lm32.c: New file.
+ * config/tc-lm32.h: New file.
+ * doc/Makefile.am: Add c-lm32.texi to CPU_DOCS.
+ * doc/Makefile.in: Regenerate.
+ * doc/all.texi: Add LM32 as CPU of interest.
+ * doc/as.texinfo: Add LM32 dependent features link.
+ * doc/c-lm32.texi: New file.
+
+2008-12-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (match_template): Changed to return
+ const template *. Handle i.swap_operand for 3 operands.
+ (build_vex_prefix): Take const template *. Swap operand for
+ 2-byte VEX prefix if possible.
+ (md_assemble): Updated.
+ (build_modrm_byte): Handle RegMem bit for SSE2AVX.
+
+2008-12-23 Anatoly Sokolov <aesok@post.ru>
+
+ * config/tc-avr.c (mcu_types): Add attiny87, attiny327, atmega4hvd,
+ atmega8hvd, atmega16hvb, atmega32hvb, atmega64c1, atmega16m1,
+ atmega64m1, atmega32u6, atmega128rfa1, at90pwm81, at90scr100,
+ m3000f, m3000s and m3001b devices.
+ * doc/c-avr.texi: Likewise.
+
+2008-12-23 Nick Clifton <nickc@redhat.com>
+
+ * NEWS :Remove mention of STT_IFUNC support.
+ * config/obj-elf.c (obj_elf_type): Remove STT_IFUNC support.
+ * doc/as.texinfo: Remove mention of STT_IFUNC support.
+
+2008-12-21 Hans-Peter Nilsson <hp@axis.com>
+
+ * config/tc-cris.c (s_cris_dtpoff): New function.
+ (md_pseudo_table): Add "dtpoffd".
+
+2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (parse_insn): Optimize ".s" handling.
+
+2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (_i386_insn): Add swap_operand.
+ (parse_insn): Handle ".s".
+ (match_template): Handle swap_operand.
+
+ * doc/c-i386.texi: Document .s suffix.
+
+2008-12-20 Hans-Peter Nilsson <hp@axis.com>
+
+ * config/tc-cris.c (cris_process_instruction): Handle
+ BFD_RELOC_CRIS_32_IE, in the test whether the relocation fits.
+ (get_3op_or_dip_prefix_op): Handle TLS/PIC decoration for the
+ "double indirect" addressing mode.
+ (cris_get_reloc_suffix): Add entry for :IE for BFD_RELOC_CRIS_32_IE.
+ (cris_number_to_imm, tc_gen_reloc): Handle BFD_RELOC_CRIS_32_IE.
+
+2008-12-18 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
+
+ * configure: Regenerate.
+
+2008-12-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (build_modrm_byte): Remove an extra blank
+ line.
+
+2008-12-04 Ben Elliston <bje@au.ibm.com>
+
+ * config/tc-ppc.c (parse_cpu): Remove booke64 support. Update
+ usage strings.
+ (ppc_setup_opcodes): Likewise, remove booke64 support.
+ * doc/c-ppc.texi (PowerPC-Opts): Remove -mbooke32 and -mbooke64.
+ * doc/as.texinfo (Overview): Likewise.
+
+2008-12-04 Nick Clifton <nickc@redhat.com>
+
+ * doc/as.texinfo (Type): Reword description of STT_IFUNC type.
+
+2008-12-03 Nick Clifton <nickc@redhat.com>
+
+ * config/obj-elf.c (obj_elf_type): Add support for STT_IFUNC type.
+ * doc/as.texinfo: Document new feature.
+ * NEWS: Mention new feature.
+
+2008-11-29 Kai Tietz <kai.tietz@onevision.com>
+
+ * config/tc-i386.c (i386_target_format): For coff flavour in TE_PEP
+ use "pe-i386" for 32-bit.
+
+2008-11-28 Jakub Jelinek <jakub@redhat.com>
+
+ * Makefile.am (ehopt.o): Add struc-symbol.h.
+ * Makefile.in: Regenerated.
+ * ehopt.c: Include struc-symbol.h.
+ (check_eh_frame): For very small O_constant DW_CFA_advance_loc4
+ create correct DW_CFA_advance_loc. Handle O_subtract only
+ for code alignment factor 1, otherwise handle O_divide or
+ O_right_shift of O_subtract and O_constant.
+ (eh_frame_estimate_size_before_relax): Always divide by ca.
+ (eh_frame_convert_frag): Likewise.
+
+2008-11-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * dw2gencfi.c (output_cfi_insn): Scale DW_CFA_advance_loc1,
+ DW_CFA_advance_loc2 and DW_CFA_advance_loc4 outputs.
+
+2008-11-28 Joshua Kinard <kumba@gentoo.org>
+
+ * config/tc-mips.c (hilo_interlocks): Handle CPU_R14000, CPU_R16000.
+ (mips_cpu_info_table): Add r14000, r16000.
+ * doc/c-mips.texi: Add entries for 14000, 16000.
+
+2008-11-27 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+ * config/tc-cr16.h (GLOBAL_OFFSET_TABLE_NAME): Defined
+ * config/tc-cr16.c (md_pseudo_table): Add "4byte" directive to
+ md_pseudo_table and accept @c prefix, same as long directive.
+ (cr16_cons_fix_new): Initialize rtype to BFD_RELOC_UNUSED.
+ (tc_gen_reloc): Declare a variable of type bfd_reloc_code_real_type
+ and set it for GOT related relocations.
+ (md_undefined_symbol): Defined
+ (process_label_constant): Added checks for GOT/got and cGOT/cGOT
+ prefixes with constant label and set the appropriate relocation type.
+ * doc/c-cr16.texi (cr16-operand specifiers): Add got/GOT and cgot/cGOT.
+
+2008-11-26 DJ Delorie <dj@redhat.com>
+
+ * config/tc-m32c.c (md_pseudo_table): Add support for .loc et al.
+
+2008-11-25 DJ Delorie <dj@redhat.com>
+
+ * config/tc-m32c.c (md_convert_frag): Fix ADJNZ reloc math.
+
+2008-11-21 Sterling Augustine <sterling@tensilica.com>
+
+ * config/tc-xtensa.c (check_t1_t2_reads_and_writes): Call
+ xtensa_state_is_shared_or to allow multiple opcodes within a
+ single FLIX bundle to write to these special states.
+
+2008-11-19 Hans-Peter Nilsson <hp@axis.com>
+
+ * config/tc-cris.c (cris_number_to_imm): Apply S_SET_THREAD_LOCAL
+ on symbols in TLS relocs.
+
+2008-11-19 Nick Clifton <nickc@redhat.com>
+
+ * doc/fdl.texi: Update to v1.3
+ * doc/as.texinfo: Change license to v1.3.
+
+2008-11-18 Catherine Moore <clm@cm00re.com>
+
+ * config/tc-arm.c (neon_type_mask): Renumber.
+ (type_chk_of_el_type): Handle F_F16.
+ (neon_cvt_flavour): Recognize half-precision conversions.
+ (do_neon_cvt): New shapes NS_QD and
+ NS_DQ. Encode half-precision conversions.
+ (do_neon_cvtt): Encode the T bit.
+ (asm_opcode_insns): vcvt, vcvtt support.
+ (arm_option_cpu_value): Add neon-fp16 support.
+
+2008-11-17 Nick Clifton <nickc@redhat.com>
+
+ * as.c (parse_args): Update copyright year.
+
+2008-11-14 Mat Hostetter <mat@lcs.mit.edu>
+
+ * read.c (emit_expr): Grow frag before filling it so that
+ dot_value remains valid.
+
+2008-11-14 Peter Jansen <pwjansen@yahoo.com>
+
+ PR 7026
+ * config/tc-arm.c: Ensure that all uses of as_bad have a
+ formatting string.
+
+2008-11-12 Hans-Peter Nilsson <hp@axis.com>
+
+ * config/tc-cris.c (cris_number_to_imm): Except for
+ BFD_RELOC_NONE, always set contents. Where previously this was
+ skipped, set contents to 0.
+
+ PR gas/7025
+ * input-scrub.c (input_scrub_include_sb): Make the position
+ after the input have defined contents, a 0 character.
+
+ * config/tc-cris.c (cris_relax_frag): Add missing case for
+ ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD).
+
+ PR gas/7020
+ * read.c (read_a_source_file): Rearrange evaluation order when
+ looking for '=' to avoid conditional on undefined contents of
+ input_line_pointer[1].
+
+2008-11-06 Adam Nemet <anemet@caviumnetworks.com>
+
+ * config/tc-mips.c (COP_INSN): Change logic to always return false
+ for FP instructions.
+
+2008-11-06 Chao-ying Fu <fu@mips.com>
+
+ * config/tc-mips.c (validate_mips_insn): Add case '1'.
+ (mips_ip): Add case '1' to process sync type.
+
+2008-11-06 Joel Sherrill <joel.sherrill@oarcorp.com>
+
+ * configure.tgt: Add m32c-*-rtems* and m32r-*-rtems*.
+
+2008-11-04 Sterling Augustine <sterling@tensilica.com>
+
+ * config/tc-xtensa.c (tinsn_check_arguments): Check for multiple
+ writes to the same register.
+
+2008-11-04 Sterling Augustine <sterling@tensilica.com>
+
+ * config/tc-xtensa.c (xtensa_j_opcode): New.
+ (xg_instruction_matches_option_term): Handle "FREEREG" option.
+ (xg_build_to_insn): Likewise. Update renamed tls_reloc reference.
+ (md_begin): Initialize xtensa_j_opcode.
+ (md_assemble): Update renamed tls_reloc reference. Handle "j.l".
+ (xg_assemble_vliw_tokens): Save free_reg info in the frag.
+ (tinsn_immed_from_frag): Get free_reg info back out of the frag.
+ (vinsn_to_insnbuf): Update renamed tls_reloc references.
+ Distinguish extra argument for "FREEREG" from extra TLS argument.
+ * config/tc-xtensa.h (struct xtensa_frag_type): Add free_reg field.
+ * config/xtensa-istack.h (struct tinsn_struct): Rename tls_reloc
+ field to extra_arg.
+ * config/xtensa-relax.c (widen_spec_list): Add rules to relax "j.l".
+ (build_transition): Handle "FREEREG" operand.
+ * config/xtensa-relax.h (enum op_type): Add OP_FREEREG.
+
+2008-10-31 Alan Modra <amodra@bigpond.net.au>
+
+ * po/id.po: Update.
+
+2008-10-24 Maciej W. Rozycki <macro@linux-mips.org>
+
+ * config/tc-mips.c (mips_cpu_info_table): Move the MIPS64r2
+ comment so that Broadcom SB-1 cores are in the MIPS64 section.
+
+2008-10-21 Alan Modra <amodra@bigpond.net.au>
+
+ * config/tc-bfin.c (gencode, allocate): Remove unnecessary cast.
+ * config/tc-ns32k.c (bit_fix_new): Likewise.
+ * config/tc-m68k.c (md_begin): Likewise.
+ * hash.c (hash_insert, hash_jam): Likewise.
+ * symbols.c (symbol_create, local_symbol_make): Likewise.
+ * frags.c (frag_alloc): Likewise.
+
+2008-10-20 Jay Krell <jay.krell@cornell.edu>
+
+ * config/bfin-parse.y: Use C style comments.
+ * config/tc-bfin.c: Likewise.
+ * config/tc-m68k.c: Likewise.
+ * config/tc-mips.c: Likewise.
+
+2008-10-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (processor_type): Moved to tc-i386.h.
+ (cpu_arch_tune): Make it global.
+ (cpu_arch_isa): Likewise.
+ (cpu_arch_isa_flags): Likewise.
+ (i386_align_code): Check fragP->tc_frag_data.isa,
+ fragP->tc_frag_data.isa_flags and cpu_arch_tune instead of
+ cpu_arch_isa, cpu_arch_isa_flags and cpu_arch_tune,
+ respectively.
+
+ * config/tc-i386.h (processor_type): Moved from tc-i386.c.
+ (cpu_arch_tune): New.
+ (cpu_arch_isa): Likewise.
+ (cpu_arch_isa_flags): Likewise.
+ (i386_tc_frag_data): Likewise.
+ (TC_FRAG_TYPE): Likewise.
+ (TC_FRAG_INIT): Likewise.
+
+2008-10-09 Bob Wilson <bob.wilson@acm.org>
+
+ * doc/as.texinfo (Pseudo Ops): Swap order of Comm and CFI menu entries.
+ (Altmacro, Comm, Loc, Loc_mark_labels, List, MRI, PopSection, Sleb128):
+ Moved into alphabetical order.
+
+2008-10-09 Bob Wilson <bob.wilson@acm.org>
+
+ * doc/as.texinfo (Dot): Expand no-space-dir conditional to include
+ a complete sentence.
+ (Pseudo Ops): Put conditionals around Skip and Space menu entries.
+ (Line): Remove conditional declaration of Ln node and section here.
+ Put aout-bout description inside the no-line-dir conditional.
+ (Skip, Space): Use a separate conditional for each node.
+
+2008-10-09 Bob Wilson <bob.wilson@acm.org>
+
+ * doc/as.texinfo (Pseudo Ops): Remove no-file-dir conditional around
+ menu entry for File; remove version-specific .file operands from menu
+ description. Replace "LNS directives" menu entry with new entries
+ for "Loc" and "Loc_mark_labels".
+ (LNS directives): Split into separate nodes for each directive.
+ (Loc): New node for .loc directive. Mention that this directive
+ is for DWARF2 and add a missing article.
+ (Loc_mark_labels): Likewise for .loc_mark_labels.
+ (File): Change this node to describe both the default version and
+ the DWARF2 version of .file. Move the no-file-dir conditional to
+ include only the default version.
+
+2008-10-09 Eric Botcazou <ebotcazou@adacore.com>
+
+ * dw2gencfi.c (cfi_finish): Deal with md_fix_up_eh_frame.
+ * config/tc-i386.h (md_fix_up_eh_frame): Define on Solaris.
+ (i386_solaris_fix_up_eh_frame): Declare.
+ * config/tc-i386.c (i386_solaris_fix_up_eh_frame): New function.
+
+2008-10-09 Nick Clifton <nickc@redhat.com>
+
+ PR 6944
+ * doc/as.texinfo (Dollar Local Labels): Correct description of
+ dollar local labels to show that the colon suffix is still
+ needed.
+
+2008-10-08 Nick Clifton <nickc@redhat.com>
+
+ * configure.in (ALL_LINGUAS): Add "id".
+ * configure: Regenerate.
+ * po/id.po: New Indonesian translation.
+
+2008-10-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * read.c (pseudo_set): Don't allow global register symbol only
+ if TC_GLOBAL_REGISTER_SYMBOL_OK is undefined.
+ * symbols.c (S_SET_EXTERNAL): Likewise.
+
+ * config/tc-mmix.h (TC_GLOBAL_REGISTER_SYMBOL_OK): Defined.
+
+ * doc/internals.texi: Document TC_GLOBAL_REGISTER_SYMBOL_OK.
+
+2008-10-06 Bob Wilson <bob.wilson@acm.org>
+
+ * doc/as.texinfo (Local): New description of ELF .local directive.
+
+2008-10-06 Nick Clifton <nickc@redhat.com>
+
+ PR 6926
+ * read.c (get_line_sb): Renamed to get_non_macro_line_sb.
+ (_find_end_of_line): Add extra parameter indicating if the line is
+ inside a macro. If it is then do not allow the @ character to be
+ treated as a line separator character.
+ (read_a_source): Update use of _find_end_of_line.
+ (find_end_of_line): Likewise.
+ (s_irp): Update use of get_line_sb.
+ (s_macro): Likewise.
+ (do_repeat): Likewise.
+ (get_line_sb): New function. Like the old version of get_line_sb
+ except that it takes an extra parameter indicating whether the
+ line is inside a macro.
+ (get_macro_line_sb): New function.
+
+2008-10-04 Hans-Peter Nilsson <hp@axis.com>
+
+ * config/tc-cris.c: Update all comments regarding explicit relocations
+ to, besides PIC, also imply TLS or to say "relocation specifier" or
+ similar.
+ (RELOC_SUFFIX_CHAR): Rename from PIC_SUFFIX_CHAR. Change all callers.
+ (cris_get_reloc_suffix): Rename from cris_get_pic_suffix. Change all
+ callers. Also handle TLS relocs.
+ (cris_get_specified_reloc_size): Rename from cris_get_pic_reloc_size.
+ Change all callers. Also handle TLS relocs.
+ (tls): New constant.
+ (cris_process_instruction): Check for non-PIC TLS relocations and
+ adjust message when emitting error message about relocation not
+ fitting.
+ (get_autoinc_prefix_or_indir_op): Also check for relocation suffix
+ when tls is true.
+ (get_3op_or_dip_prefix_op): Ditto.
+ (cris_number_to_imm, tc_gen_reloc): Handle TLS relocs like PIC relocs.
+
+2008-10-03 Kazu Hirata <kazu@codesourcery.com>
+
+ * listing.c (buffer_line): Open the source file with FOPEN_RB.
+ Manually process line ends.
+
+2008-09-30 Wesley W. Terpstra <wesley@terpstra.ca>
+ Nick Clifton <nickc@redhat.com>
+
+ * config/tc-tic4x.c (tic4x_globl): Call S_SET_EXTERNAL as well as
+ S_SET_STORAGE_CLASS.
+
+2008-09-30 Wesley W. Terpstra <wesley@terpstra.ca>
+ Nick Clifton <nickc@redhat.com>
+
+ * coffgen.c (coff_write_symbols): Check to see if a symbol's flags
+ do not match it class and if necessary update the class.
+ (null_error_handler): New function. Suppresses the generation of
+ bfd error messages.
+ * coff64-rs6000.c (bfd_xcoff_backend_data): Update comment.
+
+2008-09-30 Alan Modra <amodra@bigpond.net.au>
+
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+
+2008-09-29 Nick Clifton <nickc@redhat.com>
+
+ * dw2gencfi.c (output_cfi_insn): Fix typo in invocation of
+ tc_cfi_emit_pcrel_expr macro.
+
+2008-09-29 Peter O'Gorman <pogma@thewrittenword.com>
+ Steve Ellcey <sje@cup.hp.com>
+
+ * configure: Regenerate for new libtool.
+ * aclocal.m4: Ditto.
+ * Makefile.in: Ditto.
+ * doc/Makefile.in: Ditto.
+
+2008-09-29 Nick Clifton <nickc@redhat.com>
+
+ PR 6878
+ * app.c (do_scrub_chars): Only issue warnings about tick
+ characters detected in symbol strings if hex ticks are supported.
+
+2008-09-29 Nick Clifton <nickc@redhat.com>
+
+ * dw2gencfi.c (output_cfi_insn): Fix typo in invocation of
+ tc_cfi_emit_pcrel_expr macro.
+
+2008-09-28 Daniel Jacobowitz <dan@codesourcery.com>
+
+ * NEWS: Mention .cfi_val_encoded_addr.
+
+2008-09-26 Eric Botcazou <ebotcazou@adacore.com>
+
+ * Makefile.am (TARG_ENV_HFILES): Add config/te-solaris.h.
+ * Makefile.in (TARG_ENV_HFILES): Likewise.
+ * configure.tgt (Solaris targets): Set em=solaris.
+ * config/te-solaris.h: New file.
+
+2008-09-26 Jie Zhang <jie.zhang@analog.com>
+
+ * config/bfin-parse.y (asm_1): Fix reduce/reduce conflicts.
+
+2008-09-24 Richard Henderson <rth@redhat.com>
+
+ * dw2gencfi.c (DWARF2_ADDR_SIZE): Provide default.
+ (struct cfi_insn_data): Add ea member.
+ (CFI_val_encoded_addr, dot_cfi_val_encoded_addr): New.
+ (output_cfi_insn): Handle CFI_val_encoded_addr.
+ (select_cie_for_fde): Don't match CFI_val_encoded_addr.
+ * doc/as.texinfo (.cfi_val_encoded_addr): Document.
+
+2008-09-25 Alan Modra <amodra@bigpond.net.au>
+
+ PR 6913
+ * listing.c (print_options): Don't call fprintf without format string.
+
+2008-09-19 Alan Modra <amodra@bigpond.net.au>
+
+ * write.c (TC_FORCE_RELOCATION_SUB_LOCAL): Heed md_register_arithmetic.
+ (TC_VALIDATE_FIX_SUB): Likewise.
+ * config/tc-frv.h (TC_FORCE_RELOCATION_SUB_LOCAL): Likewise.
+ * config/tc-hppa.h (TC_FORCE_RELOCATION_SUB_LOCAL): Likewise.
+ * config/tc-mn10300.h (TC_VALIDATE_FIX_SUB): Likewise.
+ * config/tc-sh.h (TC_VALIDATE_FIX_SUB): Likewise.
+ (TC_FORCE_RELOCATION_SUB_LOCAL): Likewise.
+ * config/tc-sh64.h (TC_VALIDATE_FIX_SUB): Likewise.
+ * config/tc-xtensa.h (TC_VALIDATE_FIX_SUB): Likewise.
+ * doc/internals.texi (TC_FORCE_RELOCATION_SUB_ABS,
+ TC_FORCE_RELOCATION_SUB_LOCAL, TC_VALIDATE_FIX_SUB): Show new param.
+
+ * write.c (md_register_arithmetic): Define.
+ (fixup_segment): Adjust TC_FORCE_RELOCATION_SUB_ABS invocation.
+ Modify error message when registers involved.
+ (TC_FORCE_RELOCATION_SUB_ABS): Heed md_register_arithmetic.
+ * config/tc-sh.h (TC_FORCE_RELOCATION_SUB_ABS): Likewise.
+
+2008-09-15 Alan Modra <amodra@bigpond.net.au>
+
+ * write.c (install_reloc): Correct EMIT_SECTION_SYMBOLS test.
+
+2008-09-15 Alan Modra <amodra@bigpond.net.au>
+
+ * config/tc-frv.c (md_apply_fix): Use abs_section_sym for
+ relocs with no symbol.
+ * config/tc-mmix.c (md_assemble): Mark fake symbol on
+ BFD_RELOC_MMIX_BASE_PLUS_OFFSET as OK for use by relocs.
+ (mmix_md_end): Likewise mark mmix reg contents section symbol.
+
+2008-09-14 Chris Smith <chris@zxdesign.info>
+
+ * config/tc-z80.c: Opcode generation of ld a,(bc) and ld a,(de) was
+ broken, as the opcode of ld a,(de) was being emitted for both.
+
+2008-09-12 Sterling Augustine <sterling@tensilica.com>
+
+ * config/tc-xtensa.c (init_op_placement_info_table): Allow number of
+ operands equal to MAX_INSN_ARGS.
+
+2008-09-11 Jan Kratochvil <jan.kratochvil@redhat.com>
+
+ * configure.in: Call AC_SYS_LARGEFILE.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+
+2008-09-09 Peter Bergner <bergner@vnet.ibm.com>
+
+ * config/tc-ppc.c (ppc_setup_opcodes): Simplify POWER4/NOPOWER4 test.
+ Remove POWER5 and POWER6 tests.
+
+2008-09-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * config/tc-hppa.c (hppa_regname_to_dw2regnum): Add register name to
+ number support for 32-bit targets.
+
+2008-09-08 Tristan Gingold <gingold@adacore.com>
+
+ * NEWS: Add a marker for the 2.19 features.
+
+2008-09-07 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * config/tc-hppa.h (DIFF_EXPR_OK): Define for SOM target. Revise
+ comment regarding use of difference expressions.
+ (TC_FORCE_RELOCATION_SUB_LOCAL): Define to 1.
+
+ * dw2gencfi.c (CFI_DIFF_EXPR_OK): Define if not defined.
+ (dot_cfi_personality): Use CFI_DIFF_EXPR_OK instead of DIFF_EXPR_OK.
+ (dot_cfi_lsda, output_cie, output_fde): Likewise.
+ * config/tc-hppa.h (CFI_DIFF_EXPR_OK): Define.
+
+2008-09-06 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.h (DWARF2_FDE_RELOC_SIZE): Define.
+
+2008-09-03 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-i386.c (pe_lcomm_internal): New function. Allows the
+ alignment field of the .lcomm directive to be optional.
+ (pe_lcomm): New function. Pass pe_lcomm_internal to
+ s_comm_internal.
+ (md_pseudo_table): Implement .lcomm directive for COFF based
+ targets.
+ * doc/c-i386.texi (i386-Directives): New node. Used to document
+ the .lcomm directive.
+
+2008-08-30 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * config/tc-hppa.h: Don't define DWARF2_EH_FRAME_READ_ONLY on Linux
+ and NetBSD.
+
+2008-08-29 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * config/tc-avr.c (mcu_types): Add atmega16u4.
+ * doc/c-avr.texi: Likewise.
+
+2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-ia64.c (CR_IIB0): New.
+ (CR_IIB1): Likewise.
+ (cr): Add cr.iib0 and cr.iib1.
+ (specify_resource): Handle IA64_RS_CR_IIB and CR_IIB0/CR_IIB1.
+
+2008-08-28 Jan Beulich <jbeulich@novell.com>
+
+ * config/tc-i386.c (md_assemble): Force number of displacement
+ operands to zero when processing string instruction.
+ (i386_index_check): Special-case string instruction operands. Don't
+ fudge address prefix if there already was a memory operand. Fix
+ error message to correctly reflect the addressing mode used.
+ (i386_att_operand): Fix comment.
+ (i386_intel_operand): Snapshot, clear, and restore base and index
+ reg for each operand processed. Increment count of memory operands
+ later.
+
+2008-08-27 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * config/tc-hppa.c (is_SB_relative): New macro.
+ (fix_new_hppa): Remove $segrel$ marker.
+ (cons_fix_new_hppa): Set reloc type R_PARISC_SEGREL32 if expression is
+ segment relative.
+ * config/tc-hppa.h (tc_frob_symbol): Check for $segrel$.
+
+2008-08-27 Jan Beulich <jbeulich@novell.com>
+
+ * config/tc-i386.c (check_string): Use register_prefix for error
+ message.
+ (process_operands): Likewise.
+
+2008-08-26 Mark Mitchell <mark@codesourcery.com>
+
+ * c-arm.texi: Add tutorial on ARM unwinding pseudo ops.
+
+2008-08-26 Jie Zhang <jie.zhang@analog.com>
+
+ * config/bfin-parse.y (check_macfunc_option): Fix instruction
+ mode checking.
+ (asm_1): Check mode for 16-bit multiply instructions.
+
+2008-08-24 Alan Modra <amodra@bigpond.net.au>
+
+ * configure.in: Update a number of obsolete autoconf macros.
+ * configure: Regenerate.
+ * aclocal.m4: Regenerate.
+
+2008-08-22 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-mcore.c (md_assemble): Increase length of name array
+ to include terminating NUL.
+
+2008-08-22 Jie Zhang <jie.zhang@analog.com>
+
+ * config/bfin-lex.l (NUMBER): Protect special `.'.
+
+2008-08-22 Alan Modra <amodra@bigpond.net.au>
+
+ * symbols.c (symbol_clone): Ensure clones are not external.
+
+2008-08-22 Alan Modra <amodra@bigpond.net.au>
+
+ * config/tc-hppa.c (md_begin): Set BSF_KEEP for "dummy_symbol".
+
+2008-08-21 Richard Henderson <rth@redhat.com>
+
+ * dw2gencfi.c (DWARF2_FDE_RELOC_SIZE): New.
+ (output_cie, output_fde): Use it.
+ (DWARF2_EH_FRAME_READ_ONLY): New.
+ (cfi_finish): Use it.
+
+ * config/tc-hppa.h (DWARF2_FDE_RELOC_SIZE): Set to 8 for 64-bit.
+ (DWARF2_CIE_DATA_ALIGNMENT): Change sign.
+ (DWARF2_EH_FRAME_READ_ONLY): New.
+ * config/tc-hppa.c (tc_gen_reloc): Generate pc-relative relocations
+ from the results of DIFF_EXPR_OK manipulation.
+
+2008-08-21 Sterling Augustine <sterling@tensilica.com>
+
+ * config/xtensa-istack.h (MAX_INSN_ARGS): Increase to 64.
+
+2008-08-20 Bob Wilson <bob.wilson@acm.org>
+
+ * config/tc-xtensa.c (O_tlsfunc, O_tlsarg, O_tlscall): Define.
+ (O_tpoff, O_dtpoff): Define.
+ (suffix_relocs): Add entries for TLS suffixes.
+ (xtensa_elf_cons): Check for invalid use of TLS relocations.
+ (map_operator_to_reloc): Add is_literal parameter and use it to
+ control translating TLS instruction relocations to the corresponding
+ literal relocations.
+ (xg_valid_literal_expression): Allow TLS operators.
+ (xg_build_to_insn): Copy TLS operators from pseudo-instruction
+ operands to generated literals.
+ (xg_assemble_literal): Handle TLS operators. Update call to
+ map_operator_to_reloc.
+ (md_assemble): Handle CALLXn.TLS pseudo-instruction.
+ (md_apply_fix): Handle TLS relocations.
+ (emit_single_op): Handle TLS operators.
+ (convert_frag_immed): Update call to map_operator_to_reloc.
+ (vinsn_to_insnbuf): Emit relocations for TLS-related instructions.
+ * config/xtensa-istack.h (tinsn_struct): Add tls_reloc field.
+ * config/xtensa-relax.c (append_literal_op): Add src_op parameter
+ to initialize the op_data field of the BuildOp.
+ (build_transition): Use it here to record the source operand
+ corresponding to a generated literal.
+ * config/xtensa-relax.h (build_op): Comment op_data use for literals.
+
+2008-08-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ AVX Programming Reference (August, 2008)
+ * config/tc-i386.c (CPU_FLAGS_AES_MATCH): New.
+ (CPU_FLAGS_AVX_MATCH): Likewise.
+ (CPU_FLAGS_32BIT_MATCH): Updated.
+ (cpu_flags_match): Likewise.
+
+2008-08-20 Alan Modra <amodra@bigpond.net.au>
+
+ PR 6848
+ * write.c (install_reloc): Check that reloc symbols have been
+ written.
+ (set_symtab): Mark symbols with BSF_KEEP.
+
+2008-08-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (i386_align_code): Fix a comment typo.
+
+2008-08-15 Alan Modra <amodra@bigpond.net.au>
+
+ PR 6526
+ * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
+ * Makefile.in: Regenerate.
+ * aclocal.m4: Regenerate.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+ * doc/Makefile.in: Regenerate.
+
+2008-08-14 Alan Modra <amodra@bigpond.net.au>
+
+ * config/tc-tic4x.c (tic4x_operands_parse): Make static.
+
+2008-08-13 Ben Elliston <bje@au.ibm.com>
+
+ * doc/as.texinfo (Align): Document the PowerPC behaviour.
+
+2008-08-13 Alan Modra <amodra@bigpond.net.au>
+
+ * as.c, as.h, ecoff.c, hash.c, macro.c, symbols.c, config/obj-evax.c,
+ config/obj-som.c, config/tc-alpha.c, config/tc-arm.c, config/tc-bfin.c,
+ config/tc-bfin.h, config/tc-crx.c, config/tc-frv.c, config/tc-frv.h,
+ config/tc-hppa.h, config/tc-i386.c, config/tc-i860.c, config/tc-i960.h,
+ config/tc-ia64.c, config/tc-ia64.h, config/tc-m32c.c, config/tc-m32c.h,
+ config/tc-m68k.c, config/tc-maxq.c, config/tc-s390.c, config/tc-s390.h,
+ config/tc-sparc.c, config/tc-sparc.h, config/tc-spu.c, config/tc-spu.h,
+ config/tc-tic4x.c, config/tc-tic4x.h, config/tc-tic54x.c,
+ config/tc-tic54x.h, config/tc-vax.c, doc/internals.texi: Banish PARAMS
+ and PTR. Convert to ISO C. Delete unnecessary forward declarations.
+
+2008-08-12 Alan Modra <amodra@bigpond.net.au>
+
+ * config/tc-arm.c (s_unreq): Adjust hash_delete call.
+ * config/tc-ia64.c (dot_rot): Likewise.
+
+2008-08-11 Alan Modra <amodra@bigpond.net.au>
+
+ PR 6575
+ * hash.c: Expand PTR to void *.
+ (hash_delete): Add "freeme" parameter. Call obstack_free.
+ * hash.h: Expand PTR to void *.
+ (hash_delete): Update prototype.
+ * macro.c (macro_expand_body): hash_delete LOCALs from formal_hash.
+ * config/tc-tic54x.c (tic54x_remove_local_label): Update hash_delete
+ call.
+ (subsym_substitute): Likewise.
+ * doc/internals.texi (hash_delete): Update.
+
+2008-08-08 Anatoly Sokolov <aesok@post.ru>
+
+ * config/tc-avr.c (mcu_types): Add avr25, avr31, avr35, and avr51
+ architectures. Reorganize list to put mcu types in correct
+ architectures and to order list same as in GCC. Use new ISA
+ definitions in include/opcode/avr.h.
+ * doc/c-avr.texi: Add avr25, avr31, avr35, and avr51 architecture
+ descriptions. Reorganize descriptions to put mcu types in correct
+ architectures and to order lists same as in GCC.
+
+2008-08-08 Richard Sandiford <rdsandiford@googlemail.com>
+ Daniel Jacobowitz <dan@codesourcery.com>
+
+ * config/tc-mips.c (OPTION_CALL_NONPIC): New macro.
+ (OPTION_NON_SHARED, OPTION_XGOT, OPTION_MABI, OPTION_32)
+ (OPTION_N32, OPTION_64, OPTION_MDEBUG, OPTION_NO_MDEBUG)
+ (OPTION_PDR, OPTION_NO_PDR, OPTION_MVXWORKS_PIC): Bump by 1.
+ (md_longopts): Add -call_nonpic.
+ (md_parse_option): Handle OPTION_CALL_NONPIC.
+ (md_show_usage): Add -call_nonpic.
+
+2008-08-08 Sterling Augustine <sterling@tensilica.com>
+
+ * config/tc-xtensa.c (exclude_section_from_property_tables): New.
+ (xtensa_create_property_segments): Use it.
+ (xtensa_create_xproperty_segments): Likewise.
+
+2008-08-08 Alan Modra <amodra@bigpond.net.au>
+
+ * doc/internals.texi (DWARF2_FORMAT): Update for 2008-08-04 change.
+
+2008-08-06 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips16_reloc_p, got16_reloc_p, hi16_reloc_p)
+ (lo16_reloc_p): New functions.
+ (reloc_needs_lo_p): Use hi16_reloc_p and got16_reloc_p to
+ generalize relocation checks.
+ (matching_lo_reloc): New function.
+ (fixup_has_matching_lo_p): Use it.
+ (mips16_mark_labels): Don't clobber a symbol's visibility.
+ (append_insn): Use hi16_reloc_p and lo16_reloc_p.
+ (mips16_ip): Handle BFD_RELOC_MIPS16_GOT16 and BFD_RELOC_MIPS16_CALL16.
+ (md_apply_fix): Likewise.
+ (mips16_percent_op): Add %got and %call16.
+ (mips_frob_file): Use got16_reloc_p to generalize relocation checks.
+ Use matching_lo_reloc.
+ (mips_force_relocation): Use hi16_reloc_p and lo16_reloc_p to
+ generalize relocation checks.
+ (mips_fix_adjustable): Use lo16_reloc_p to generalize relocation
+ checks.
+
+2008-08-06 DJ Delorie <dj@redhat.com>
+
+ * NEWS: Mention these changes.
+
+ * config/tc-h8300.h (H_TICK_HEX): Define.
+ * config/tc-h8300.c (OPTION_H_TICK_HEX): New.
+ (md_longopts): Add "-h-tick-hex".
+ (md_parse_option): Support it.
+ * doc/c-h8300.texi (H8/300 Options): Document it.
+ * doc/as.texinfo (Overview): Likewise.
+
+ * config/tc-sh.h (H_TICK_HEX): Define.
+ * config/tc-sh.c (OPTION_H_TICK_HEX): New.
+ (md_longopts): Add "-h-tick-hex".
+ (md_parse_option): Support it.
+ * doc/c-sh.texi (SH Options): Document it.
+ * doc/c-sh64.texi (SH64 Options): Document it.
+ * doc/as.texinfo (Overview): Likewise.
+
+2008-08-05 Alan Modra <amodra@bigpond.net.au>
+
+ PR gas/6656
+ * dwarf2dbg.c (dwarf2_directive_file): Disable gas generated
+ debug info if we see compiler generated debug info.
+ (dwarf2_directive_loc): Likewise. Remove redundant debug_type test.
+
+2008-08-04 Alan Modra <amodra@bigpond.net.au>
+
+ * dwarf2dbg.c: Remove superfluous forward function declarations.
+ (DWARF2_FORMAT): Add section arg.
+ (out_header): New function, split out from..
+ (out_debug_line): ..here.
+ (out_debug_aranges): Use out_header.
+ (out_debug_abbrev): Add info_seg and line_seg args. Use
+ DW_FORM_data8 (for DW_AT_stmt_list) if line_seg is 64-bit.
+ (out_debug_info): Use out_header. Output 8 byte DW_AT_stmt_list
+ if line_seg is 64-bit.
+ (dwarf2_finish): Adjust out_debug_abbrev call.
+ * config/tc-mips.h (DWARF2_FORMAT, mips_dwarf2_format): Add sec arg.
+ * config/tc-mips.c (mips_dwarf2_format): Likewise.
+
+2008-08-04 Alan Modra <amodra@bigpond.net.au>
+
+ * Makefile.am (POTFILES.in): Set LC_ALL=C.
+ * Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ * config/tc-ppc.c (parse_cpu): Rename altivec_or_spe to retain_flags.
+ Handle -mvsx and -mpower7.
+ (md_show_usage): Document -mpower7 and -mvsx.
+ * doc/as.texinfo (Target PowerPC): Document -mvsx.
+ * doc/c-ppc.texi (PowerPC-Opts): Document -mvsx and -mpower7.
+
+2008-07-31 Peter Bergner <bergner@vnet.ibm.com>
+
+ * config/tc-ppc.c (parse_cpu) <power6>: Accept Altivec instructions.
+ <cell>: Likewise.
+
+2008-07-30 Michael J. Eager <eager@eagercon.com>
+
+ * config/tc-ppc.c (parse_cpu): Separate handling of -m403/405.
+ (md_show_usage): Likewise.
+
+2008-07-30 Alan Modra <amodra@bigpond.net.au>
+
+ * messages.c, symbols.c, write.c: Silence gcc warnings.
+
+2008-07-28 Ineiev <ineiev@yahoo.co.uk>
+
+ * config/tc-i386.c (operand_type_check): Warning fix.
+
+2008-07-26 Michael Eager <eager@eagercon.com>
+
+ * doc/as.texinfo: Add description of single-precision attribute.
+
+2008-07-24 Jie Zhang <jie.zhang@analog.com>
+
+ * config/bfin-parse.y (asm_1): Error if plain symbol is used
+ as load/store offset.
+
+2008-07-22 Chao-ying Fu <fu@mips.com>
+
+ * config/tc-mips.c (mips_ip): Reset s to argsStart.
+
+2008-07-22 Jie Zhang <jie.zhang@analog.com>
+
+ * config/tc-bfin.c (bfin_gen_loop): Remove loop symbol.
+
+2008-07-21 DJ Delorie <dj@redhat.com>
+
+ * config/tc-h8300.c (fix_operand_size): Use the default size
+ specified by the .lbranch/.sbranch pseudos.
+
+2008-07-18 DJ Delorie <dj@redhat.com>
+
+ * config/tc-m32c.h (H_TICK_HEX): Define.
+ * config/tc-m32c.c (OPTION_H_TICK_HEX): Define.
+ (md_longopts): Add support for it.
+ (md_parse_option): Likewise.
+ * doc/as.texinfo (Overview): Add new m32c options.
+ * doc/c-m32c.texi (M32C-Modifiers): Likewise
+
+ * as.h: (enable_h_tick_hex): New.
+ * app.c (enable_h_tick_hex): New.
+ (LEX_IS_H): New.
+ (do_scrub_begin): Mark 'H' and 'h' as special if enable_h_tick_hex.
+ (do_scrub_chars): If enable_h_tick_hex and 'h', check for H'00
+ style hex constants and convert the input stream to 0x00 style.
+ (do_scrub_chars): If a 'X style character constant is found after
+ a symbol character (like you're or X'00), warn the user.
+
+2008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/tc-mips.c (mips16_mark_labels): Use ELF_ST_SET_MIPS16.
+ (mips_fix_adjustable): Likewise.
+ (mips_frob_file_after_relocs): Likewise.
+
+2008-07-08 Nathan Sidwell <nathan@codesourcery.com>
+
+ * config/tc-m68k.c (m68k_set_cpu, m68k_set_arch): Don't complain
+ about overriding an earlier setting.
+
+2008-07-07 Adam Nemet <anemet@caviumnetworks.com>
+
+ * config/tc-mips.c (NO_ISA_COP): New macro.
+ (COP_INSN): New macro.
+ (is_opcode_valid): Use them.
+ (macro) <ld_st>: Use them. Don't accept coprocessor load store
+ insns based on the ISA if CPU is NO_ISA_COP.
+ <copz>: Likewise for coprocessor operations.
+
+2008-07-07 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (arm_fix_adjustable): Don't adjust MOVW/MOVT
+ relocations.
+
+2008-07-07 Ralf Corsépius <ralf.corsepius@rtems.org>
+
+ * configure.tgt: Add bfin-*-rtems*.
+
+2008-07-04 Alan Modra <amodra@bigpond.net.au>
+
+ * config/tc-spu.c (md_apply_fix): Handle fully resolved
+ BFD_RELOC_32_PCREL, BFD_RELOC_SPU_HI16 and BFD_RELOC_SPU_LO16.
+
+2008-06-25 Peter Bergner <bergner@vnet.ibm.com>
+
+ * config/tc-ppc.c (parse_cpu): Handle -m464.
+ (md_show_usage): Likewise.
+
+2008-06-24 Eric B. Weddington <eric.weddington@atmel.com>
+
+ Add support for ATtiny13A.
+ * config/tc-avr.c (mcu_types): Add attiny13a.
+ * doc/c-avr.texi: Likewise.
+
+2008-06-24 Bob Wilson <bob.wilson@acm.org>
+ Alan Modra <amodra@bigpond.net.au>
+
+ * write.c (relax_segment <rs_org>): Include current stretch
+ value when calculating whether .org is backwards.
+
+2008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
+
+ * configure: Regenerate.
+
+2008-06-17 Nick Clifton <nickc@redhat.com>
+
+ * app.c (do_scrub_chars): Do not UNGET an EOF value.
+
+2008-06-16 Hans-Peter Nilsson <hp@bitrange.com>
+
+ PR gas/6607
+ * config/tc-mmix.c (s_loc): Assume "negative" addresses belong to
+ text_section. Do the "stepping backwards" test for text_section
+ using unsigned operands.
+
+2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
+
+ * config/tc-ppc.c (ppc_cpu): Use ppc_cpu_t typedef.
+ (ppc_insert_operand): Likewise.
+ (ppc_machine): Likewise.
+ * config/tc-ppc.h: #include "opcode/ppc.h"
+ (struct _ppc_fix_extra <ppc_cpu>): Use ppc_cpu_t typedef.
+ (ppc_cpu): Update extern decl.
+
+2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
+
+ * config/tc-mips.c (validate_mips_insn): Handle field descriptors
+ +x, +X, +p, +P, +s, +S.
+ (mips_ip): Likewise.
+
+ * config/tc-mips.c (validate_mips_insn): Handle field descriptor +Q.
+ (mips_ip): Likewise.
+ (macro_build): Likewise.
+ (CPU_HAS_SEQ): New macro.
+ (macro2) <M_SEQ_I, M_SNE_I>: Use it. Emit seq/sne and seqi/snei.
+
+2008-06-09 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * config/tc-avr.c (mcu_types): Remove support for ATmega32HVB device.
+ * doc/c-avr.texi: Likewise.
+
+2008-06-04 Nick Clifton <nickc@redhat.com>
+
+ * app.c (do_scrub_chars): Do not UNGET an EOF value.
+
+2008-06-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (set_sse_check): New.
+ (md_pseudo_table): Add "sse_check".
+
+2008-06-03 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (do_t_rbit): Populate both rm fields.
+
+2008-05-30 Nick Clifton <nickc@redhat.com>
+
+ PR 5523
+ * config/tc-avr.c (avr_ldi_expression): Do not warn about unknown
+ relocs here.
+
+2008-05-29 Maxim Kuvyrkov <maxim@codesourcery.com>
+
+ * config/tc-mips.c (mips_cpu_info_table): Move records for
+ ST Loongson-2E/2F processors to a better place.
+
+2008-05-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/6518
+ * config/tc-i386.c (match_template): Report ambiguous operand
+ size, not invalid suffix when there is no match in Intel
+ syntax.
+
+2008-05-22 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (parse_cond): Covert to lowercase before matching.
+
+2008-05-21 I-Jui Sung <ijsung@gmail.com>
+
+ * config/tc-arm.c (arm_cpus): Add Faraday ARMv4 and ARMv5TE
+ compatible cores: fa526, fa626, fa626te, fa726te.
+ * doc/c-arm.texi (ARM Opts): Add -mcpu={fa526, fa626, fa626te,
+ fa726te} options.
+
+2008-05-14 Alan Modra <amodra@bigpond.net.au>
+
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+ * doc/Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2008-05-09 Catherine Moore <clm@codesourcery.com>
+
+ * config/tc-mips.c (mips_frob_file): Don't match MIPS16 relocs
+ with non-MIPS16 relocs.
+
+2008-05-09 Chao-ying Fu <fu@mips.com>
+
+ * config/tc-mips.c (md_begin): Use strncmp to compare TARGET_OS, in
+ case that some characters append at the end of the name.
+ (mips_ip): Likewise.
+ (s_change_sec): Likewise.
+ (md_section_align): Likewise.
+
+2008-05-07 Bob Wilson <bob.wilson@acm.org>
+
+ * config/tc-xtensa.c (xtensa_create_property_segments): Use
+ xtensa_make_property_section instead of xtensa_get_property_section.
+ (xtensa_create_xproperty_segments): Likewise.
+
+2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * NEWS: Mention XSAVE, EPT and MOVBE.
+
+ * config/tc-i386.c (cpu_arch): Add .movbe and .ept.
+ (md_show_usage): Add .movbe and .ept.
+
+ * doc/c-i386.texi: Add movbe and ept to -march=. Document
+ .movbe and .ept.
+
+2008-04-29 David S. Miller <davem@davemloft.net>
+
+ * config/tc-sparc.c (v9a_asr_table): Fix order of softint entries.
+
+2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
+
+ * config/tc-mips.c (file_mips_soft_float, file_mips_single_float):
+ New statics.
+ (OPTION_ELF_BASE): Make room for new option macros.
+ (OPTION_SOFT_FLOAT, OPTION_HARD_FLOAT, OPTION_SINGLE_FLOAT,
+ OPTION_DOUBLE_FLOAT): New option macros.
+ (md_longopts): Add msoft-float, mhard-float, msingle-float and
+ mdouble-float.
+ (md_parse_option): Handle OPTION_SINGLE_FLOAT,
+ OPTION_DOUBLE_FLOAT, OPTION_SOFT_FLOAT and OPTION_HARD_FLOAT.
+ (md_show_usage): Add -msoft-float, -mhard-float, -msingle-float
+ and -mdouble-float.
+ (struct mips_set_options): New fields soft_float and single_float.
+ (mips_opts): Initialized them. Add comment for each field
+ initializer.
+ (mips_after_parse_args): Set them based on file_mips_soft_float
+ and file_mips_single_float.
+ (s_mipsset): Add support for `.set softfloat', `.set hardfloat',
+ `.set singlefloat' and `.set doublefloat'.
+ (is_opcode_valid): New function to invoke OPCODE_IS_MEMBER.
+ Handle single-float and soft-float instructions here.
+ (macro_build, mips_ip): Use it instead of OPCODE_IS_MEMBER.
+ (is_opcode_valid_16): New function.
+ (mips16_ip): Use it instead of OPCODE_IS_MEMBER.
+ (macro) <M_LDC1_AB, M_SDC1_AB, M_L_DOB, M_L_DAB, M_S_DAB,
+ M_S_DOB>: Remove special-casing of r4650.
+ * doc/c-mips.texi (-march=): Add Octeon.
+ (MIPS Opts): Document -msoft-float and -mhard-float. Document
+ -msingle-float and -mdouble-float.
+ (MIPS floating-point): New section. Document `.set softfloat' and
+ `.set hardfloat'. Document `.set singlefloat' and `.set
+ doublefloat'.
+
+2008-04-25 David S. Miller <davem@davemloft.net>
+
+ * config/tc-sparc.c: Accept 'softint_clear' and 'softint_set'
+ %asr aliases.
+
+ * doc/c-sparc.texi: Consistently refer to architecture 'versions',
+ rather than occaisionally 'levels'. Consistently refer to Sun's
+ UNIX variant as SunOS, every version of Solaris is also SunOS.
+ Document new 'softint_clear' and 'softint_set' aliases. Clarify
+ which architecture versions support '%dcr', '%cq', and '%gl'. Add
+ section on 32-bit/64-bit opcode translations.
+
+2008-04-23 Mike Frysinger <vapier@gentoo.org>
+
+ * Makefile.am (OBJ_FORMAT_CFILES): Add config/obj-fdpicelf.c.
+ (OBJ_FORMAT_HFILES): Add config/obj-fdpicelf.h.
+ (obj-fdpicelf.o): Define.
+ * Makefile.in: Regenerate.
+ * configure.tgt: Set bfd_gas to yes when fmt is fdpicelf.
+ (bfin-*-*): Delete.
+ (bfin-*-linux-uclibc): New; set fmt to fdpicelf and em to linux.
+ (bfin-*-uclinux*): New; set fmt to elf and em to linux.
+ * config/obj-fdpicelf.c: New.
+ * config/obj-fdpicelf.h: Likewise.
+ * config/tc-bfin.c (bfin_flags, bfin_pic_flag): Set default based on
+ the OBJ_FDPIC_ELF define.
+ (OPTION_NOPIC): Define.
+ (md_longopts): Add mnopic and mno-fdpic.
+ (md_parse_option): Handle OPTION_NOPIC.
+
+2008-04-23 Paolo Bonzini <bonzini@gnu.org>
+
+ * aclocal.m4: Regenerate.
+ * configure: Regenerate.
+
+2008-04-23 David S. Miller <davem@davemloft.net>
+
+ * config/tc-sparc.c (v9a_asr_table): Add missing
+ 'stick' and 'stick_cmpr', and document ordering rules
+ of table.
+ (tc_gen_reloc): Accept BFD_RELOC_SPARC_PC22 and
+ BFD_RELOC_SPARC_PC10.
+ * doc/c-sparc.texi: New section on Sparc constants.
+ Add documentation for %stick and %stick_cmpr.
+
+2008-04-22 David S. Miller <davem@davemloft.net>
+
+ * config/obj-elf.c (obj_elf_section_type): Add prototype
+ before obj_elf_section_word and add 'warn' arg.
+ (obj_elf_section_word): Add type pointer arg, and if no #SECTION
+ is matched, try checking for #SECTION_TYPE.
+ (obj_elf_section): Adjust for new args.
+ (obj_elf_type_name): New function.
+ (obj_elf_type): Call it, and accept STT_foo number strings
+ in .type statements as output by SunPRO compiler.
+
+2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (md_assemble): Don't check SSE instructions
+ if noavx is 0.
+
+2008-04-18 David S. Miller <davem@davemloft.net>
+
+ * doc/c-sparc.texi: Add syntax section.
+
+2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (build_modrm_byte): Don't check FMA to swap
+ REG and NDS for instructions with immediate operand.
+
+2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (build_modrm_byte): Swap REG and NDS for
+ FMA.
+
+2008-04-16 David S. Miller <davem@davemloft.net>
+
+ * config/tc-sparc.c (sparc_ip): Add support for gotdata mnemonics
+ and relocation generation.
+ (tc_gen_reloc): Likewise.
+
+2008-04-15 Andrew Stubbs <andrew.stubbs@st.com>
+
+ * config/tc-sh.c (md_apply_fix): Make sure BFD_RELOC_SH_PCRELIMM8BY4
+ relocations are properly aligned, and not negative.
+
+2008-04-15 Khem Raj <kraj@mvista.com>
+
+ * doc/tc-arm.texi: Fix fnstart and fnend directive names.
+
+2008-04-14 Edmar Wienskoski <edmar@freescale.com>
+
+ * config/tc-ppc.c (parse_cpu): Handle "e500mc". Extend "e500" to
+ accept e500mc instructions.
+ (md_show_usage): Document -me500mc.
+
+2008-04-11 Nick Clifton <nickc@redhat.com>
+
+ * listing.c (print_timestamp): Use localtime rather than
+ localtime_r since not all build environments provide the latter.
+
+2008-04-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ * NEWS: Mention -msse-check=[none|error|warning].
+
+ * config/tc-i386.c (sse_check): New.
+ (OPTION_MSSE_CHECK): Likewise.
+ (md_assemble): Check SSE instructions if needed.
+ (md_longopts): Add -msse-check.
+ (md_parse_option): Handle OPTION_MSSE_CHECK.
+ (md_show_usage): Show -msse-check=[none|error|warning].
+
+ * doc/c-i386.texi: Document -msse-check=[none|error|warning].
+
+2008-04-10 Santiago Urueña <suruena@gmail.com>
+
+ * listing.c: Add -ag listing flag to show general information in
+ listings such as gas version, passed options, and time stamp.
+ (listing_general_info): New function.
+ (print_options): New function.
+ (print_single_option): New function.
+ (print_timestamp): New function.
+ (MAX_DATELEN): Define.
+ (listing_print): Add call to listing_general_info.
+ * listing.h (LISTING_GENERAL): Define.
+ (listing_print): Add new parameter.
+ * as.c (show_usage): Print new switch.
+ (parse_args): Parse new switch.
+ (main): Pass command line on to listing_print.
+ * NEWS: Mention this new feature.
+ * doc/as.texinfo: Document the new sub-option.
+
+2008-04-08 Alan Modra <amodra@bigpond.net.au>
+
+ * dwarf2dbg.c (dwarf2_emit_insn): Simplify test before dwarf2_where
+ call. Delete out of date comment.
+ (dwarf2_consume_line_info): Always clear dwarf2_loc_directive_seen.
+ (dwarf2_emit_label): Don't emit unless there has been a previous
+ .file or we are outputting assembler generated debug.
+ dwarf2_consume_line_info after emitting line info, not before.
+ (out_debug_info): Simplify files_in_use test.
+
+2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (parse_real_register): Return AVX register
+ only if AVX is enabled.
+
+2008-04-07 Kaz Kojima <kkojima@rr.iij4u.or.jp>
+
+ PR gas/6043
+ * config/tc-sh64.c (shmedia_md_pcrel_from_section): Use
+ md_pcrel_from_section for BFD_RELOC_64 and BFD_RELOC_64_PCREL.
+
+2008-04-04 Adrian Bunk <bunk@stusta.de>
+ Bob Wilson <bob.wilson@acm.org>
+
+ * config/tc-xtensa.c (xg_apply_fix_value): Check return code from
+ call to decode_reloc.
+
+2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ * NEWS: Mention XSAVE. Change CLMUL to PCLMUL.
+
+ * config/tc-i386.c (cpu_arch): Add .pclmul.
+ (md_show_usage): Replace clmul with pclmul.
+ * doc/c-i386.texi: Likewise.
+
+2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
+
+ * doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
+ Document -msse2avx, .avx, .aes, .clmul and .fma.
+
+ * config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
+ (vex_prefix): Likewise.
+ (sse2avx): Likewise.
+ (CPU_FLAGS_ARCH_MATCH): Likewise.
+ (CPU_FLAGS_64BIT_MATCH): Likewise.
+ (CPU_FLAGS_32BIT_MATCH): Likewise.
+ (CPU_FLAGS_PERFECT_MATCH): Likewise.
+ (regymm): Likewise.
+ (vex_imm4): Likewise.
+ (fits_in_imm4): Likewise.
+ (build_vex_prefix): Likewise.
+ (VEX_check_operands): Likewise.
+ (bad_implicit_operand): Likewise.
+ (OPTION_MSSE2AVX): Likewise.
+ (T_YMMWORD): Likewise.
+ (_i386_insn): Add vex.
+ (cpu_arch): Add .avx, .aes, .clmul and .fma.
+ (cpu_flags_match): Changed to take a pointer to const template.
+ Enable encoding SSE instructions with VEX prefix for -msse2avx.
+ (match_mem_size): Also check ymmword.
+ (operand_type_match): Clear ymmword.
+ (md_begin): Allow '_' in mnemonic.
+ (type_names): Add OPERAND_TYPE_VEX_IMM4.
+ (process_immext): Update assert.
+ (md_assemble): Don't call process_immext if sse2avx and immext
+ are true. Call build_vex_prefix if vex is true.
+ (parse_insn): Updated for cpu_flags_match.
+ (swap_operands): Handle 5 operands.
+ (match_template): Handle 5 operands. Updated for cpu_flags_match.
+ Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
+ (process_suffix): Handle YMMWORD_MNEM_SUFFIX.
+ (check_byte_reg): Check regymm.
+ (process_operands): Duplicate the destination register for
+ -msse2avx if needed.
+ (build_modrm_byte): Updated for instructions with VEX encoding.
+ (output_insn): Output VEX prefix if needed.
+ (md_longopts): Add msse2avx.
+ (md_parse_option): Handle OPTION_MSSE2AVX.
+ (md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
+ (intel_e09): Support YMMWORD.
+ (intel_e11): Likewise.
+ (intel_get_token): Likewise.
+
+2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * config/tc-avr.c (mcu_types): Add attiny167.
+ * doc/c-avr.texi: Likewise.
+
+2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * config/tc-avr.c (mcu_types): Add atmega32u4.
+ * doc/c-avr.texi: Likewise.
+
+2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * config/tc-avr.c (mcu_types): Add atmega32c1.
+ * doc/c-avr.texi: Likewise.
+
+2008-03-28 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (parse_neon_mov): Parse register before immediate
+ to avoid spurious symbols.
+
+2008-03-28 Nathan Sidwell <nathan@codesourcery.com>
+
+ * config/tc-m68k.c (md_convert_frag_1): Replace as_fatal with
+ as_bad_where.
+
+2008-03-27 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * config/tc-avr.c (mcu_types): Add atmega32m1.
+ * doc/c-avr.texi: Likewise.
+
+2008-03-27 Ineiev <ineiev@yahoo.co.uk>
+
+ * config/tc-arm.c (do_neon_cvt): Move variable declarations to
+ start of block.
+ (do_neon_ext): Fix sign of comparison.
+
+2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
+
+ From Jie Zhang <jie.zhang@analog.com>
+ * config/bfin-parse.y (asm_1): Check AREGS in comparison
+ instructions. And call yyerror when comparing PREG with
+ DREG.
+ (check_macfunc_option): New.
+ (check_macfuncs): Check option by calling check_macfunc_option.
+ Fix comparison always true warnings. Both scalar instructions
+ of vector instruction must share the same mode option. Only allow
+ option mode at the end of the second instruction of the vector.
+ (asm_1): Check option by calling check_macfunc_option.
+
+ * config/bfin-parse.y (check_macfunc_option): Allow (IU)
+ option for multiply and multiply-accumulate to data register
+ instruction.
+ (check_macfuncs): Don't check if accumulator matches the data register
+ here.
+ (assign_macfunc): Check if accumulator matches the
+ data register in each rule that moves to the data
+ register.
+
+ * config/tc-bfin.c (bfin_start_line_hook): Localize the labels
+ generated for LOOP_BEGIN and LOOP_END instructions.
+ (bfin_gen_loop): Likewise.
+
+2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * config/tc-s390.c (md_parse_option): z10 option added.
+
+2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
+
+ * aclocal.m4: Regenerate.
+ * configure: Likewise.
+ * Makefile.in: Likewise.
+ * doc/Makefile.in: Likewise.
+
+2008-03-17 Adrian Bunk <bunk@stusta.de>
+
+ PR 5946
+ * config/tc-hppa.c (is_same_frag): Delete.
+
+2008-03-14 Sterling Augustine <sterling@tensilica.com>
+
+ * config/tc-xtensa.h (xtensa_relax_statesE): Update comment for
+ RELAX_LOOP_END_ADD_NOP.
+
+2008-03-13 Evandro Menezes <evandro@yahoo.com>
+
+ PR gas/5895
+ * read.c (s_mexit): Warn if attempting to exit a macro when not
+ inside a macro definition.
+
+2008-03-13 Alan Modra <amodra@bigpond.net.au>
+
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+
+2008-03-09 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (arm_cpu_option_table): Add cortex-a9.
+ * doc/c-arm.texi: Add cortex-a9.
+
+2008-03-09 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (fpu_vfp_ext_d32): New vairable.
+ (parse_vfp_reg_list, encode_arm_vfp_reg): Use it.
+ (arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3.
+ (aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16.
+ * doc/c-arm.texi: Document new ARM FPU variants.
+
+2008-03-07 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (md_apply_fix): Use correct offset range.
+
+2008-03-07 Alan Modra <amodra@bigpond.net.au>
+
+ * config/tc-ppc.c (ppc_setup_opcodes): Tidy. Add code to test
+ for strict ordering of powerpc_opcodes, but disable for now.
+
+2008-03-04 Paul Brook <paul@codesourcery.com>
+
+ * config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New.
+ (arm_ext_v7m): Rename...
+ (arm_ext_m): ... to this. Include v6-M.
+ (do_t_add_sub): Allow narrow low-reg non flag setting adds.
+ (do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m.
+ (md_assemble): Allow wide msr instructions.
+ (insns): Add classifications for v6-m instructions.
+ (arm_cpu_option_table): Add cortex-m1.
+ (arm_arch_option_table): Add armv6-m.
+ (cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants.
+
+2008-03-03 Sterling Augustine <sterling@tensilica.com>
+ Bob Wilson <bob.wilson@acm.org>
+
+ * config/tc-xtensa.c (xtensa_num_pipe_stages): New.
+ (md_begin): Initialize it.
+ (resources_conflict): Use it.
+
+2008-03-03 Sterling Augustine <sterling@tensilica.com>
+
+ * config/tc-xtensa.h (RELAX_XTENSA_NONE): New.
+
+2008-03-03 Denys Vlasenko <vda.linux@googlemail.com>
+ H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/5543
+ * read.c (pseudo_set): Don't allow global register symbol.
+
+ * symbols.c (S_SET_EXTERNAL): Don't allow register symbol
+ global.
+
+2008-03-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/5543
+ * write.c (write_object_file): Don't allow symbols which were
+ equated to register. Stop if there is an error.
+
+2008-03-01 Alan Modra <amodra@bigpond.net.au>
+
+ * config/tc-ppc.h (struct _ppc_fix_extra): New.
+ (ppc_cpu): Declare.
+ (TC_FIX_TYPE, TC_INIT_FIX_DATA): Define.
+ * config/tc-ppc.c (ppu_cpu): Make global.
+ (ppc_insert_operand): Add ppu_cpu parameter.
+ (md_assemble): Adjust for above change.
+ (md_apply_fix): Pass tc_fix_data.ppc_cpu to ppc_insert_operand.
+
+2008-02-22 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-arm.c (do_bx): Only test EF_ARM_EABI_VERSION on ELF
+ targeted ARM ports, otherwise just skip generating the reloc.
+
+2008-02-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * doc/c-i386.texi: Update -march= and .arch.
+
+2008-02-18 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-mn10300.c (has_known_symbol_location): New function.
+ Do not regard weak symbols as having a known location.
+ (md_estimate_size_before_relax): Use new function.
+ (md_pcrel_from): Do not compute a pcrel against a weak symbol.
+
+2008-02-18 Jan Beulich <jbeulich@novell.com>
+
+ * config/tc-i386.c (match_template): Disallow 'l' suffix when
+ currently selected CPU has no 32-bit support.
+ (parse_real_register): Do not return registers not available on
+ currently selected CPU.
+
+2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (process_immext): Fix format.
+
+2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (inoutportreg): New.
+ (process_immext): New.
+ (md_assemble): Use it.
+ (update_imm): Use imm16 and imm32s.
+ (i386_att_operand): Use inoutportreg.
+
+2008-02-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (operand_type_all_zero): New.
+ (operand_type_set): Likewise.
+ (operand_type_equal): Likewise.
+ (cpu_flags_all_zero): Likewise.
+ (cpu_flags_set): Likewise.
+ (cpu_flags_equal): Likewise.
+ (UINTS_ALL_ZERO): Removed.
+ (UINTS_SET): Likewise.
+ (UINTS_CLEAR): Likewise.
+ (UINTS_EQUAL): Likewise.
+ (cpu_flags_match): Updated.
+ (smallest_imm_type): Likewise.
+ (set_cpu_arch): Likewise.
+ (md_assemble): Likewise.
+ (optimize_imm): Likewise.
+ (match_template): Likewise.
+ (process_suffix): Likewise.
+ (update_imm): Likewise.
+ (process_drex): Likewise.
+ (process_operands): Likewise.
+ (build_modrm_byte): Likewise.
+ (i386_immediate): Likewise.
+ (i386_displacement): Likewise.
+ (i386_att_operand): Likewise.
+ (parse_real_register): Likewise.
+ (md_parse_option): Likewise.
+ (i386_target_format): Likewise.
+
+2008-02-14 Dimitry Andric <dimitry@andric.com>
+
+ PR gas/5712
+ * config/tc-arm.c (s_arm_unwind_save): Advance the input line
+ pointer past the comma after parsing a floating point register
+ name.
+
+2008-02-14 Hakan Ardo <hakan@debian.org>
+
+ PR gas/2626
+ * config/tc-avr.c (mcu_types): Change the ISA tyoe of the attiny26
+ to AVR_ISA_2xxe.
+ (avr_operand): Disallow post-increment addressing in the lpm
+ instruction for the attiny26.
+
+2008-02-13 Jan Beulich <jbeulich@novell.com>
+
+ * config/tc-i386.c (parse_real_register): Don't return 'FLAT'
+ if not in Intel mode.
+ (i386_intel_operand): Ignore segment overrides in immediate and
+ offset operands.
+ (intel_e11): Range-check i.mem_operands before use as array
+ index. Filter out FLAT for uses other than as segment override.
+ (intel_get_token): Remove broken promotion of "FLAT:" to mean
+ "offset FLAT:".
+
+2008-02-13 Jan Beulich <jbeulich@novell.com>
+
+ * config/tc-i386.c (intel_e09): Also special-case 'bound'.
+
+2008-02-13 Jan Beulich <jbeulich@novell.com>
+
+ * config/tc-i386.c (allow_pseudo_reg): New.
+ (parse_real_register): Check for NULL just once. Allow all
+ register table entries when allow_pseudo_reg is non-zero.
+ Don't allow any registers without type when allow_pseudo_reg
+ is zero.
+ (tc_x86_regname_to_dw2regnum): Replace with ...
+ (tc_x86_parse_to_dw2regnum): ... this.
+ (tc_x86_frame_initial_instructions): Adjust for above change.
+ * config/tc-i386.h (tc_regname_to_dw2regnum): Remove.
+ (tc_parse_to_dw2regnum): New.
+ (tc_x86_regname_to_dw2regnum): Replace with ...
+ (tc_x86_parse_to_dw2regnum): ... this.
+ * dw2gencfi.c (tc_parse_to_dw2regnum): New, broken out of ...
+ (cfi_parse_reg): ... this. Use tc_parse_to_dw2regnum. Adjust
+ error handling.
+
+2008-02-12 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-tic4x.c (tic4x_insn_insert): Add const qualifier to
+ argument.
+ (tic4x_insn_add): Likewise.
+ (md_begin): Drop cast that was discarding a const qualifier.
+ * config/tc-d30v.c (get_reloc): Add const qualifier to op
+ argument.
+ (build_insn): Drop cast that was discarding a const qualifier.
+
+2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Add .xsave.
+ (md_show_usage): Add .xsave.
+
+ * doc/c-i386.texi: Add xsave to -march=.
+
+2008-02-07 Alan Modra <amodra@bigpond.net.au>
+
+ * read.c (s_weakref): Don't pass unadorned NULL to concat.
+ * config/tc-i386.c (set_cpu_arch, md_parse_option): Likewise.
+
+2008-02-05 Sterling Augustine <sterling@tensilica.com>
+
+ * config/tc-xtensa.c (relax_frag_immed): Change internal consistency
+ checks into assertions. When relaxation produces an operation that
+ does not fit in the current FLIX instruction, make sure that the
+ operation is relaxed as needed to account for being placed following
+ the current instruction.
+
+2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR 5715
+ * configure: Regenerated.
+
+2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
+
+ * config/tc-mips.c (mips_cpu_info_table): Add Octeon.
+
+2008-01-31 Marc Gauthier <marc@tensilica.com>
+
+ * configure.tgt (xtensa*-*-*): Recognize processor variants.
+
+2008-01-25 Kai Tietz <kai.tietz@onevision.com>
+
+ * read.c: (emit_expr): Correct for mingw use of printf size
+ specifier.
+
+2008-01-24 Bob Wilson <bob.wilson@acm.org>
+
+ * doc/c-xtensa.texi (Xtensa Syntax): Clarify handling of opcodes that
+ can only be encoded in FLIX instructions but are not specified as such.
+ (Xtensa Automatic Alignment): Remove obsolete comment about debugging
+ labels.
+
+2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
+
+ * NEWS: Mention new command line options for x86 targets.
+
+2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (md_show_usage): Replace tabs with spaces.
+
+2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * config/tc-avr.c (mcu_types): Change opcode set for at86rf401.
+
+2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (md_show_usage): Show more processors for
+ -march=/-mtune=.
+
+2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (i386_target_format): Remove cpummx2.
+
+2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (XXX_PREFIX): Moved from tc-i386.h.
+ (XXX_MNEM_SUFFIX): Likewise.
+ (END_OF_INSN): Likewise.
+ (templates): Likewise.
+ (modrm_byte): Likewise.
+ (rex_byte): Likewise.
+ (DREX_XXX): Likewise.
+ (drex_byte): Likewise.
+ (sib_byte): Likewise.
+ (processor_type): Likewise.
+ (arch_entry): Likewise.
+ (cpu_sub_arch_name): Remove const.
+ (cpu_arch): Add .vmx and .smx.
+ (set_cpu_arch): Append cpu_sub_arch_name.
+ (md_parse_option): Support -march=CPU[,+EXTENSION...].
+ (md_show_usage): Updated.
+
+ * config/tc-i386.h (XXX_PREFIX): Moved to tc-i386.c.
+ (XXX_MNEM_SUFFIX): Likewise.
+ (END_OF_INSN): Likewise.
+ (templates): Likewise.
+ (modrm_byte): Likewise.
+ (rex_byte): Likewise.
+ (DREX_XXX): Likewise.
+ (drex_byte): Likewise.
+ (sib_byte): Likewise.
+ (processor_type): Likewise.
+ (arch_entry): Likewise.
+
+ * doc/as.texinfo: Update i386 -march option.
+
+ * doc/c-i386.texi: Update -march= for ISA.
+
+2008-01-18 Bob Wilson <bob.wilson@acm.org>
+
+ * config/tc-xtensa.c (xtensa_leb128): New function.
+ (md_pseudo_table): Use it for sleb128 and uleb128.
+ (is_leb128_expr): New internal flag.
+ (xtensa_symbol_new_hook): Check new flag.
+
+2008-01-16 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * config/tc-avr.c (mcu_types): Change opcode set for avr3,
+ at90usb82, at90usb162.
+ * doc/c-avr.texi: Change architecture grouping for at90usb82,
+ at90usb162.
+ These changes support the new avr35 architecture group in gcc.
+
+2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (md_assemble): Also zap movzx and movsx
+ suffix for AT&T syntax.
+
+2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (match_reg_size): New.
+ (match_mem_size): Likewise.
+ (operand_size_match): Likewise.
+ (operand_type_match): Also clear all size fields.
+ (match_template): Skip Intel syntax when in AT&T syntax.
+ Call operand_size_match to check operand size.
+ (i386_att_operand): Set the mem field to 1 for memory
+ operand.
+ (i386_intel_operand): Likewise.
+
+2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/5534
+ * config/tc-i386.c (_i386_insn): Update comment.
+ (operand_type_match): Also clear unspecified.
+ (operand_type_register_match): Likewise.
+ (parse_operands): Initialize unspecified.
+ (i386_intel_operand): Likewise.
+ (match_template): Check memory and accumulator operand size.
+ (i386_att_operand): Clear unspecified on register operand.
+ (intel_e11): Likewise.
+ (intel_e09): Set operand size and clean unspecified for
+ "XXX PTR".
+
+2008-01-11 Andreas Schwab <schwab@suse.de>
+
+ * read.c (s_space): Declare `repeat' as offsetT.
+
+2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (match_template): Check processor support
+ first.
+
+2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (match_template): Continue if processor
+ doesn't match.
+
+2008-01-09 Alexandre Oliva <aoliva@redhat.com>
+
+ * config/tc-ia64.c (ia64_convert_frag): Zero-initialize room for
+ unwind personality function address.
+
+2008-01-09 Bob Wilson <bob.wilson@acm.org>
+
+ * dwarf2dbg.c (out_sleb128): Delete.
+ (size_fixed_inc_line_addr, emit_fixed_inc_line_addr): New.
+ (out_fixed_inc_line_addr): Delete.
+ (relax_inc_line_addr, dwarf2dbg_estimate_size_before_relax): Call new
+ size_fixed_inc_line_addr if DWARF2_USE_FIXED_ADVANCE_PC is set.
+ (dwarf2dbg_convert_frag): Likewise for emit_fixed_inc_line_addr.
+ (process_entries): Remove calls to out_fixed_inc_line_addr. When
+ DWARF2_USE_FIXED_ADVANCE_PC is set, call relax_inc_line_addr.
+ * read.h (emit_expr_fix): New prototype.
+ * read.c (emit_expr): Move code to emit_expr_fix and use it here.
+ (emit_expr_fix): New.
+
+2008-01-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (match_template): Check register size
+ only when size of operands can be encoded the canonical way.
+
+2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (i386_operand): Renamed to ...
+ (i386_att_operand): This.
+ (parse_operands): Updated.
+
+2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ * doc/c-i386.texi: Update .att_mnemonic and .intel_mnemonic.
+
+ * config/tc-i386.c (set_intel_mnemonic): Set intel_mnemonic
+ only.
+ (md_assemble): Remove Intel mode workaround.
+ (match_template): Check support for old gcc, AT&T mnemonic
+ and Intel Syntax.
+ (md_parse_option): Don't set intel_mnemonic to 0 for
+ OPTION_MOLD_GCC.
+
+2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.h: Update copyright to 2008.
+
+2008-01-04 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-ppc.c (parse_cpu): Preserve the settings of the
+ PPC_OPCODE_ALTIVEC and PPC_OPCODE_SPE flags.
+
+2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (md_assemble): Use !intel_mnemonic instead
+ of SYSV386_COMPAT.
+
+2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/config/tc-i386.c (cpu_arch_flags_not): Removed.
+ (cpu_flags_not): Likewise.
+ (cpu_flags_match): Updated to check 64bit and arch.
+ (set_code_flag): Remove cpu_arch_flags_not.
+ (set_16bit_gcc_code_flag): Likewise.
+ (set_cpu_arch): Likewise.
+ (md_begin): Likewise.
+ (parse_insn): Call cpu_flags_match to check 64bit and arch.
+ (match_template): Likewise.
+
+2008-01-03 Jakub Jelinek <jakub@redhat.com>
+
+ * config/tc-i386.c (process_drex): Initialize modrm_reg and
+ modrm_regmem to 0 instead of None.
+
+2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (match_template): Use the xmmword field
+ instead of no_xsuf.
+
+2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (process_suffix): Fix a typo.
+
+2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/5534
+ * config/tc-i386.c (match_template): Handle XMMWORD_MNEM_SUFFIX.
+ Check memory size in Intel mode.
+ (process_suffix): Handle XMMWORD_MNEM_SUFFIX.
+ (intel_e09): Likewise.
+
+ * config/tc-i386.h (XMMWORD_MNEM_SUFFIX): New.
+
+2008-01-02 Catherine Moore <clm@codesourcery.com>
+
+ * config/tc-mips.c (mips_ip): Check operands on jalr instruction.
+
+For older changes see ChangeLog-2007
+\f
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
/* tc-i386.c -- Assemble code for the Intel 80386
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
{
unsigned int nds, reg;
- if (i.tm.opcode_modifier.veximmext
- && i.tm.opcode_modifier.immext)
- {
- dest = i.operands - 2;
- assert (dest == 3);
- }
- else
- dest = i.operands - 1;
+ dest = i.operands - 1;
nds = dest - 1;
-
- /* There are 2 kinds of instructions:
- 1. 5 operands: one immediate operand and 4 register
- operands or 3 register operands plus 1 memory operand.
- It must have VexNDS and VexW0 or VexW1. The destination
- must be either XMM or YMM register.
- 2. 4 operands: 4 register operands or 3 register operands
- plus 1 memory operand. It must have VexNDS and VexImmExt. */
- if (!((i.reg_operands == 4
- || (i.reg_operands == 3 && i.mem_operands == 1))
- && i.tm.opcode_modifier.vexnds
- && (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
- || operand_type_equal (&i.tm.operand_types[dest], ®ymm))
- && ((dest == 4
- && i.imm_operands == 1
- && i.types[0].bitfield.vex_imm4
- && (i.tm.opcode_modifier.vexw0
- || i.tm.opcode_modifier.vexw1))
- || (dest == 3
- && (i.imm_operands == 0
- || (i.imm_operands == 1
- && i.tm.opcode_modifier.immext))
- && i.tm.opcode_modifier.veximmext))))
- abort ();
-
- if (i.imm_operands == 0)
- {
- /* When there is no immediate operand, generate an 8bit
- immediate operand to encode the first operand. */
- expressionS *exp = &im_expressions[i.imm_operands++];
- i.op[i.operands].imms = exp;
- i.types[i.operands] = imm8;
- i.operands++;
- /* If VexW1 is set, the first operand is the source and
- the second operand is encoded in the immediate operand. */
- if (i.tm.opcode_modifier.vexw1)
- {
- source = 0;
- reg = 1;
- }
- else
- {
- source = 1;
- reg = 0;
- }
-
- /* FMA swaps REG and NDS. */
- if (i.tm.cpu_flags.bitfield.cpufma)
- {
- unsigned int tmp;
- tmp = reg;
- reg = nds;
- nds = tmp;
- }
-
- assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm)
+ source = 1;
+ reg = 0;
+
+ /* This instruction must have 4 operands: 4 register operands
+ or 3 register operands plus 1 memory operand. It must have
+ VexNDS and VexImmExt. */
+ assert (i.operands == 4
+ && (i.reg_operands == 4
+ || (i.reg_operands == 3 && i.mem_operands == 1))
+ && i.tm.opcode_modifier.vexnds
+ && i.tm.opcode_modifier.veximmext
+ && (operand_type_equal (&i.tm.operand_types[dest],
+ ®xmm)
+ || operand_type_equal (&i.tm.operand_types[dest],
+ ®ymm))
+ && (operand_type_equal (&i.tm.operand_types[nds],
+ ®xmm)
+ || operand_type_equal (&i.tm.operand_types[nds],
+ ®ymm))
+ && (operand_type_equal (&i.tm.operand_types[reg],
+ ®xmm)
|| operand_type_equal (&i.tm.operand_types[reg],
- ®ymm));
- exp->X_op = O_constant;
- exp->X_add_number
- = ((i.op[reg].regs->reg_num
- + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
- }
- else
- {
- unsigned int imm;
-
- if (i.tm.opcode_modifier.vexw0)
- {
- /* If VexW0 is set, the third operand is the source and
- the second operand is encoded in the immediate
- operand. */
- source = 2;
- reg = 1;
- }
- else
- {
- /* VexW1 is set, the second operand is the source and
- the third operand is encoded in the immediate
- operand. */
- source = 1;
- reg = 2;
- }
+ ®ymm)));
- if (i.tm.opcode_modifier.immext)
- {
- /* When ImmExt is set, the immdiate byte is the last
- operand. */
- imm = i.operands - 1;
- source--;
- reg--;
- }
- else
- {
- imm = 0;
-
- /* Turn on Imm8 so that output_imm will generate it. */
- i.types[imm].bitfield.imm8 = 1;
- }
-
- assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm)
- || operand_type_equal (&i.tm.operand_types[reg],
- ®ymm));
- i.op[imm].imms->X_add_number
- |= ((i.op[reg].regs->reg_num
- + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
- }
+ /* Generate an 8bit immediate operand to encode the register
+ operand. */
+ expressionS *exp = &im_expressions[i.imm_operands++];
+ i.op[i.operands].imms = exp;
+ i.types[i.operands] = imm8;
+ i.operands++;
+ exp->X_op = O_constant;
+ exp->X_add_number
+ = ((i.op[0].regs->reg_num
+ + ((i.op[0].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
- assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
- || operand_type_equal (&i.tm.operand_types[nds], ®ymm));
i.vex.register_specifier = i.op[nds].regs;
}
else
-2008-12-30 Nick Clifton <nickc@redhat.com>
+2009-01-05 H.J. Lu <hongjiu.lu@intel.com>
- * gas/ppc/ppc.exp: Do not run the booke_xcoff64 test.
- * gas/ppc/booke_xcoff64.s: Delete.
- * gas/ppc/booke_xcoff64.d: Delete.
-
-2008-12-23 Jon Beniston <jon@beniston.com>
-
- * gas/lm32: New directory.
- * gas/lm32/all.exp: New file.
- * gas/lm32/csr.d: New file.
- * gas/lm32/csr.s: New file.
- * gas/lm32/insn.d: New file.
- * gas/lm32/insn.s: New file.
-
-2008-12-23 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/i386.exp: Run x86-64-avx-swap and x86-64-avx-swap-intel.
-
- * gas/i386/opts.s: Add tests for movsd, movss, vmovsd and
- vmovss.
- * gas/i386/x86-64-opts.s: Likewise.
-
- * gas/i386/opts.d: Updated.
- * gas/i386/opts-intel.d: Likewise.
- * gas/i386/sse2avx-opts.d: Likewise.
- * gas/i386/sse2avx-opts-intel.d: Likewise.
- * gas/i386/x86-64-opts.d: Likewise.
- * gas/i386/x86-64-opts-intel.d: Likewise.
- * gas/i386/x86-64-sse2avx-opts.d: Likewise.
- * gas/i386/x86-64-sse2avx-opts-intel.d: Likewise.
-
- * gas/i386/x86-64-avx-swap.d: New.
- * gas/i386/x86-64-avx-swap.s: Likewise.
- * gas/i386/x86-64-avx-swap-intel.d: Likewise.
-
-2008-12-23 Nick Clifton <nickc@redhat.com>
-
- * gas/elf/type.s: Remove test of STT_IFUNC support.
- * gas/elf/type.e: Update expected output.
-
-2008-12-21 Hans-Peter Nilsson <hp@axis.com>
-
- * gas/cris/rd-dtpoffd1.d, gas/cris/rd-dtpoffd1.s: New test.
-
-2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/i386.exp: Run opts, opts-intel, sse2avx-opts,
- sse2avx-opts-intel, x86-64-opts, x86-64-opts-intel,
- x86-64-sse2avx-opts and x86-64-sse2avx-opts-intel.
-
- * gas/i386/opts.d: New.
- * gas/i386/opts-intel.d: Likewise.
- * gas/i386/opts.s: Likewise.
- * gas/i386/sse2avx-opts.d: Likewise.
- * gas/i386/sse2avx-opts-intel.d: Likewise.
- * gas/i386/x86-64-opts.d: Likewise.
- * gas/i386/x86-64-opts-intel.d: Likewise.
- * gas/i386/x86-64-opts.s: Likewise.
- * gas/i386/x86-64-sse2avx-opts.d: Likewise.
- * gas/i386/x86-64-sse2avx-opts-intel.d: Likewise.
-
-2008-12-20 Hans-Peter Nilsson <hp@axis.com>
-
- * gas/cris/rd-tls-1.s, gas/cris/rd-tls-1.d: Test :IE and
- decoration on double-indirect.
- * gas/cris/tls-err-1.s: Test :IE on wrong-size operand.
-
-2008-12-18 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/intel.d: Remove trailing white spaces after nop.
- * gas/i386/intelpic.d: Likewise.
- * gas/i386/nops16-1.d: Likewise.
- * gas/i386/nops-1-i686.d: Likewise.
- * gas/i386/nops-3.d: Likewise.
- * gas/i386/nops-3-i386.d: Likewise.
- * gas/i386/nops-3-i686.d: Likewise.
- * gas/i386/nops-4.d: Likewise.
- * gas/i386/nops-4-i386.d: Likewise.
- * gas/i386/nops-4-i686.d: Likewise.
- * gas/i386/opcode.d: Likewise.
- * gas/i386/opcode-suffix.d: Likewise.
- * gas/i386/reloc.d: Likewise.
- * gas/i386/tlsnopic.d: Likewise.
- * gas/i386/x86-64-nops-1.d: Likewise.
- * gas/i386/x86-64-nops-1-nocona.d: Likewise.
- * gas/i386/x86-64-nops-2.d: Likewise.
- * gas/i386/x86-64-nops-3.d: Likewise.
- * gas/i386/x86-64-nops-4-core2.d: Likewise.
- * gas/i386/x86-64-nops-4.d: Likewise.
- * gas/i386/x86-64-nops-4-k8.d: Likewise.
- * gas/i386/x86-64-opcode.d: Likewise.
-
-2008-12-15 Richard Earnshaw <rearnsha@arm.com>
-
- * gas/arm/group-reloc-ldc.d: Disassembly of VFP instructions now uses
- unified syntax.
- * gas/arm/vfp-non-overlap.d: Likewise.
- * gas/arm/vfp-neon-syntax.d: Likewise.
- * gas/arm/vfp-neon-syntax_t2.d: Likewise.
- * gas/arm/vfp1.d: Likewise.
- * gas/arm/vfp1_t2.d: Likewise.
- * gas/arm/vfp1xD.d: Likewise.
- * gas/arm/vfp1xD_t2.d: Likewise.
- * gas/arm/vfp2.d: Likewise.
- * gas/arm/vfp2_t2.d: Likewise.
- * gas/arm/vfpv3-32drs.d: Likewise.
- * gas/arm/vfpv3-const-conv.d: Likewise.
-
-2008-12-04 Ben Elliston <bje@au.ibm.com>
-
- * gas/ppc/booke.s: Remove booke64 instructions.
- * gas/ppc/booke.d: Update expected disassembly output.
- * gas/ppc/booke_xcoff.s: Use -mbooke/-Mbooke.
- * gas/ppc/booke_xcoff.d: Likewise.
- * gas/ppc/booke_xcoff64.d: Likewise.
- * gas/ppc/booke_xcoff64.s: Likewise.
-
-2008-12-03 Nick Clifton <nickc@redhat.com>
-
- * gas/elf/type.s: Add test of STT_IFUNC symbol type.
- * gas/elf/type.e: Update expected disassembly.
- * gas/elf/elf.exp: Update grep of symbol types.
-
-2008-11-27 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
-
- * gas/cr16/pic-1.s: New.
- * gas/cr16/pic-1.d: New.
- * gas/cr16/pic-2.s: New.
- * gas/cr16/pic-2.d: New.
- * gas/cr16/pic.exp: Run pic tests.
-
-2008-11-19 Hans-Peter Nilsson <hp@axis.com>
-
- * gas/cris/rd-tls-1.d, gas/cris/rd-tls-1.s: Use a local thread
- variable instead of .text location for :GD decoration test.
-
-2008-11-18 Catherine Moore <clm@codesourcery.com>
-
- * gas/arm/half-prec-neon.d: New.
- * gas/arm/half-prec-neon.s: New.
- * gas/arm/half-prec-vfp3.d: New.
- * gas/arm/half-prec-vfp3.s: New.
- * gas/arm/half-prec-psyntax.d: New.
- * gas/arm/half-prec-psyntax.s: New.
-
-2008-11-12 Hans-Peter Nilsson <hp@axis.com>
-
- * gas/cris/rd-bcnst2-pic.d, gas/cris/rd-bcnst2.d,
- gas/cris/rd-bcnst2.s: New tests.
-
-2008-11-06 Adam Nemet <anemet@caviumnetworks.com>
-
- * gas/mips/mips1-fp.s, testsuite/gas/mips/mips1-fp.d,
- testsuite/gas/mips/mips1-fp.l: New tests.
- * gas/mips/mips.exp: Run them.
-
-2008-11-06 Chao-ying Fu <fu@mips.com>
-
- * gas/mips/mips32-sync.d, gas/mip/mips32-sync.s: New tests.
- * gas/mips/mips.exp: Run them.
-
-2008-11-04 Bob Wilson <bob.wilson@acm.org>
-
- * gas/xtensa/all.exp: Run jlong test.
- * gas/xtensa/jlong.d: New.
- * gas/xtensa/jlong.s: New.
-
-2008-11-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/intel.s: Add tests for cmovpe and cmovpo.
- * gas/i386/opcode.s: Likewise.
-
- * gas/i386/intel.d: Updated.
- * gas/i386/opcode.d: Likewise.
- * gas/i386/opcode-intel.d: Likewise.
- * gas/i386/opcode-suffix.d: Likewise.
-
-2008-10-12 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/i386.exp: Run nops-5, nops-5-i686, x86-64-nops-5 and
- x86-64-nops-5-k8.
-
- * gas/i386/nops-5.d: New.
- * gas/i386/nops-5.s: Likewise.
- * gas/i386/nops-5-i686.d: Likewise.
- * gas/i386/x86-64-nops-5.d: Likewise.
- * gas/i386/x86-64-nops-5-k8.d: Likewise.
-
-2008-10-06 Tom Tromey <tromey@redhat.com>
-
- * gas/cfi/cfi-alpha-1.d, gas/cfi/cfi-alpha-3.d,
- gas/cfi/cfi-arm-1.d, gas/cfi/cfi-common-1.d,
- gas/cfi/cfi-common-2.d, gas/cfi/cfi-common-3.d,
- gas/cfi/cfi-common-4.d, gas/cfi/cfi-common-5.d,
- gas/cfi/cfi-common-6.d, gas/cfi/cfi-hppa-1.d,
- gas/cfi/cfi-i386-2.d, gas/cfi/cfi-i386.d, gas/cfi/cfi-m68k.d,
- gas/cfi/cfi-mips-1.d, gas/cfi/cfi-ppc-1.d, gas/cfi/cfi-s390-1.d,
- gas/cfi/cfi-s390x-1.d, gas/cfi/cfi-sh-1.d, gas/cfi/cfi-sparc-1.d,
- gas/cfi/cfi-sparc64-1.d, gas/cfi/cfi-x86_64.d: Update for readelf
- change.
-
-2008-10-04 Hans-Peter Nilsson <hp@axis.com>
-
- * gas/cris/rd-tls-1.s, gas/cris/rd-tls-1.d, gas/cris/rd-tls-2.s,
- gas/cris/rd-tls-2.d, gas/cris/tls-err-1.s, gas/cris/tls-err-2.s,
- gas/cris/tls-err-3.s: New tests.
-
-2008-09-26 Andreas Krebbel <krebbel1@de.ibm.com>
-
- * gas/s390/esa-g5.d: Adjust according to the s390-opc changes.
- * gas/s390/esa-g5.s: Likewise.
- * gas/s390/esa-z990.d: Likewise.
- * gas/s390/esa-z990.s: Likewise.
- * gas/s390/zarch-z900.d: Likewise.
- * gas/s390/zarch-z900.s: Likewise.
- * gas/s390/zarch-z990.d: Likewise.
- * gas/s390/zarch-z990.s: Likewise.
-
-2008-09-15 Alan Modra <amodra@bigpond.net.au>
-
- * gas/all/gas.exp: Don't run redef tests on a bunch of targets.
- * gas/elf/elf.exp: Likewise.
-
-2008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
-
- * gas/z80/ld-group.s, gas/z80/ld-group.d: New test.
- * gas/z80/block.s, gas/z80/block.d: New test
- * gas/z80/arith.s, gas/z80/arith.d: New test
- * gas/z80/rotate.s, gas/z80/rotate.d: New test
- * gas/z80/bit.s, gas/z80/bit.d: New test
- * gas/z80/branch.s, gas/z80/branch.d: New test
- * gas/z80/inout.s, gas/z80/inout.d: New test
- * gas/z80/misc.s, gas/z80/misc.d: New test
- * gas/z80/z80.exp: Run them.
-
-2008-09-11 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/sse2avx.s: Remove pclmulXXX tests. Add tests for
- Intel syntax.
- * gas/i386/x86-64-sse2avx.s: Likewise.
-
- * gas/i386/sse2avx.d: Updated.
- * gas/i386/x86-64-sse2avx.d: Likewise.
-
-2008-09-09 Peter Bergner <bergner@vnet.ibm.com>
-
- * gas/ppc/common.s: New test.
- * gas/ppc/common.d: Likewise.
- * gas/ppc/power4_32.s: Likewise.
- * gas/ppc/power4_32.d: Likewise.
- * gas/ppc/power6.s: Add attn, mtcr, mtcrf, mfcr, dcbz.
- * gas/ppc/power6.d: Likewise.
- * gas/ppc/ppc.exp: Run power4_32 test.
-
-2008-09-06 Richard Sandiford <rdsandiford@googlemail.com>
-
- * gas/mips/cfi-n64-1.s, gas/mips/cfi-n64-1.d: New test.
- * gas/mips/mips.exp: Run it.
-
-2008-09-05 Nick Clifton <nickc@redhat.com>
-
- * gas/arm/abs12.d: Update expected disassembly.
- * gas/arm/tls_vxworks.d: Likewise.
- * gas/arm/unwind_vxworks.d: Likewise.
- * gas/arm/group-reloc-alu-encoding-bad.d: Skip for vxworks
- targets.
- * gas/arm/group-reloc-alu.d: Likewise.
- * gas/arm/group-reloc-ldc-encoding-bad.d: Likewise.
- * gas/arm/group-reloc-ldc.d: Likewise.
- * gas/arm/group-reloc-ldr-encoding-bad.d: Likewise.
- * gas/arm/group-reloc-ldr.d: Likewise.
- * gas/arm/group-reloc-ldrs-encoding-bad.d: Likewise.
- * gas/arm/group-reloc-ldrs.d: Likewise.
- * gas/arm/local_function.d: Likewise.
- * gas/arm/mapshort-elf.d: Likewise.
- * gas/arm/undefined.d: Likewise.
-
-2008-09-04 Christian Groessler <chris@groessler.org>
-
- * lib/gas-defs.exp (run_dump_test): If the test expects an error,
- fail the test if gas doesn't report an error.
-
-2008-08-28 Jan Beulich <jbeulich@novell.com>
-
- * gas/i386/intel.s: Add retf.
- * gas/i386/intel.{d,e}: Adjust.
- * gas/i386/opcode-intel.d: Replace lret with retf.
-
-2008-08-28 Jan Beulich <jbeulich@novell.com>
-
- * gas/i386/gas/i386/opcode-suffix.d: Add suffixes to cmovXX.
-
-2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/ia64/dv-raw-err.s: Add tests for cr.iib0 and cr.iib1.
- * gas/ia64/dv-waw-err.s: Likewise.
- * gas/ia64/regs.s: Likewise.
-
- * gas/ia64/dv-raw-err.l: Updated.
- * gas/ia64/dv-waw-err.l: Likewise.
- * gas/ia64/regs.d: Likewise.
-
-2008-08-28 Jan Beulich <jbeulich@novell.com>
-
- * gas/i386/string-bad.{l,s}, gas/i386/string-ok.{d,e,s}: New.
- * gas/i386/i386.exp: Run new tests.
-
-2008-08-27 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/intel.s: Add tests for fidivr.
-
- * gas/i386/intel.d: Updated.
-
-2008-08-26 Jie Zhang <jie.zhang@analog.com>
-
- * gas/bfin/arith_mode.d: New test.
- * gas/bfin/arith_mode.s: New test.
- * gas/bfin/invalid_arith_mode.l: New test.
- * gas/bfin/invalid_arith_mode.s: New test.
- * gas/bfin/bfin.exp: Add arith_mode and invalid_arith_mode.
-
-2008-08-22 Jie Zhang <jie.zhang@analog.com>
-
- * gas/bfin/misc.s: New test.
- * gas/bfin/misc.d: New test.
- * gas/bfin/bfin.exp: Add misc test.
-
-2008-08-21 Richard Henderson <rth@redhat.com>
-
- * gas/cfi/cfi-common-1.d: Allow for differing offsets, and
- for DW_CFA_offset_extended_sf results. Allow for differing nops.
- * gas/cfi/cfi-hppa-1.d: Invert data alignment sign. Change
- offsets to match 64-bit offsets.
- * gas/cfi/cfi.exp: Don't run common tests on hppa64.
-
-2008-08-20 Bob Wilson <bob.wilson@acm.org>
-
- * gas/all/gas.exp: Expect the redef test to fail on Xtensa.
-
-2008-08-20 H.J. Lu <hongjiu.lu@intel.com>
-
- AVX Programming Reference (August, 2008)
- * gas/i386/avx.s: Add AES + AVX tests.
- * gas/i386/arch-10.s: Likewise.
- * gas/i386/sse2avx.s: Likewise.
+ AVX Programming Reference (December, 2008)
+ * gas/i386/arch-10.s: Replace vfmaddpd with vfmadd132pd.
* gas/i386/x86-64-arch-2.s: Likewise.
- * gas/i386/x86-64-avx.s: Likewise.
- * gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx-intel.d: Likewise.
- * gas/i386/sse2avx.d: Likewise.
- * gas/i386/x86-64-arch-2.d: Likewise.
- * gas/i386/x86-64-avx.d: Likewise.
- * gas/i386/x86-64-avx-intel.d: Likewise.
- * gas/i386/x86-64-sse2avx.d: Likewise.
-
- * gas/i386/i386.exp: Run arch-avx-1, arch-avx-1-1 and
- arch-avx-1-2.
-
- * gas/i386/arch-avx-1.d: New.
- * gas/i386/arch-avx-1.s: Likewise.
- * gas/i386/arch-avx-1-1.l: Likewise.
- * gas/i386/arch-avx-1-1.s: Likewise.
- * gas/i386/arch-avx-1-2.l: Likewise.
- * gas/i386/arch-avx-1-2.s: Likewise.
-
-2008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-
- * gas/s390/esa-g5.d: lxr operands are floating point.
- * gas/s390/esa-g5.s: Likewise.
- * gas/testsuite/gas/s390/zarch-z9-ec.d: rrdtr, rrxtr third
- operands is gpr.
- * gas/testsuite/gas/s390/zarch-z9-ec.s: Likewise.
-
-2008-08-12 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/amd.s: Add syscall and sysret. Remove padding.
-
- * gas/i386/amd.d: Updated.
- * gas/i386/x86-64-opcode.d: Likewise.
-
- * gas/i386/i386.exp: Run x86-64-intel64.
-
- * gas/i386/x86-64-intel64.d: New.
- * gas/i386/x86-64-intel64.s: Likewise.
-
- * gas/i386/x86-64-opcode.s: Add syscall and sysret.
-
-2008-08-08 Richard Sandiford <rdsandiford@googlemail.com>
-
- * gas/mips/call-nonpic-1.s, gas/mips/call-nonpic-1.d: New test.
- * gas/mips/mips.exp: Run it.
-
-2008-08-06 Richard Sandiford <rdsandiford@googlemail.com>
-
- * gas/mips/elf-rel8-mips16.d, gas/mips/elf-rel8-mips16.s,
- * gas/mips/elf-rel9-mips16.d, gas/mips/elf-rel9-mips16.s,
- * gas/mips/elf-rel13-mips16.d, gas/mips/elf-rel13-mips16.s: New tests.
- * gas/mips/mips.exp: Run them.
-
-2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
-
- * gas/ppc/power7.d: New.
- * gas/ppc/power7.s: Likewise.
- * gas/ppc/ppc.exp: Run power7 test.
-
-2008-08-01 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/cfi/cfi-i386.s: Remove tests for AVX register maps.
- * gas/cfi/cfi-x86_64.s: Likewise.
-
- * gas/cfi/cfi-i386.d: Updated.
- * gas/cfi/cfi-x86_64.d: Likewise.
-
-2008-07-31 Peter Bergner <bergner@vnet.ibm.com>
-
- * gas/ppc/cell.s: Add altivec instructions.
- * gas/ppc/cell.d: Update expected output.
- * gas/ppc/power6.d: New.
- * gas/ppc/power6.s: Likewise.
- * gas/ppc/ppc.exp (powerpc64*-*-*): Move cell from here to...
- (powerpc*-*-*): Here. Run power6 test.
-
-2008-07-24 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/nops-1.d: Add -mtune=generic32.
- * gas/i386/nops-2.d: Likewise.
- * gas/i386/nops-3.d: Likewise.
-
- * gas/i386/x86-64-nops-1.d: Add -mtune=generic64.
- * gas/i386/x86-64-nops-2.d: Likewise.
- * gas/i386/x86-64-nops-3.d: Likewise.
- * gas/i386/x86-64-nops-4.d: Likewise.
-
-2008-07-22 Chao-ying Fu <fu@mips.com>
-
- * gas/mips/tls-ill.l: Update error message.
- * gas/mips/octeon-ill.l: Likewise.
-
-2008-07-14 Jie Zhang <jie.zhang@analog.com>
-
- * gas/bfin/{bit2.s, cache2.s, control_code2.s, event2.s,
- logical2.s, move2.s, parallel.s, parallel2.s, parallel3.s,
- parallel4.s, shift2.s, stack2.s, video2.s}: Remove DOS line
- endings.
-
-2008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
-
- * gas/mips/mips16-vis-1.d, gas/mips/mips16-vis-1.s: New tests.
- * gas/mips/mips.exp: Run them.
-
-2008-07-09 Kai Tietz <kai.tietz@onevision.com>
-
- * gas/i386/i386.exp (x86-64-pcrel): Disable for w64.
- (x86-64-sse5): Likewise.
- (x86-64-opcode-inval): Likewise.
- (x86-64-opcode-inval-intel): Likewise.
- (x86-64-w64-pcrel): New.
- * gas/i386/x86-64-w64-pcrel.d: New.
-
-2008-07-07 Adam Nemet <anemet@caviumnetworks.com>
-
- * gas/mips/mips32.s: Move out coprocessor2 insns from here ...
- * gas/mips/mips32-cp2.s: ... to here.
- * gas/mips/mips32.d: Update.
- * gas/mips/mips32-cp2.d: New file.
- * gas/mips/mips32r2.s: Move out coprocessor2 insns from here ...
- * gas/mips/mips32r2-cp2.s: ... to here.
- * gas/mips/mips32r2.d: Update.
- * gas/mips/mips32r2-cp2.d: New file.
- * gas/mips/mips64.s: Move out coprocessor2 insns from here ...
- * gas/mips/mips64-cp2.s: ... to here.
- * gas/mips/mips64.d: Update.
- * gas/mips/mips64-cp2.d: New file.
- * gas/mips/mips.exp: Run mips32-cp2, mips32r2-cp2 and mips64-cp
- except for Octeon.
- * gas/mips/octeon.s: Add supported coprocessor insns. Move pop
- down to keep alphabetical order.
- * gas/mips/octeon.d: Update.
- * gas/mips/octeon-ill.s: Add unsupported coprocessor insns.
- * gas/mips/octeon-ill.l: Update.
-
-2008-07-07 Paul Brook <paul@codesourcery.com>
-
- * gas/arm/movw-local.d: New test.
- * gas/arm/movw-local.s: New test.
-
-2008-06-27 Chao-ying Fu <fu@mips.com>
-
- * gas/mips/odd-float.d: Replace ... with #pass.
- * gas/mips/ldstla-32-shared.d: Add -march=mips1 for as.
- * gas/mips/ldstla-32.d: Likewise.
- * gas/mips/mips16-hilo-match.d: Add -mabi=32 -march=mips1 for as.
-
-2008-06-19 Chao-ying Fu <fu@mips.com>
-
- * gas/mips/e32-rel2.d: Add -march=mips1 for as.
-
-2008-06-16 Hans-Peter Nilsson <hp@bitrange.com>
-
- PR gas/6607
- * gas/mmix/err-loc-10.s, gas/mmix/err-loc-9.s, gas/mmix/loc-6.d,
- gas/mmix/loc-6.s, gas/mmix/loc-7.d, gas/mmix/loc-7.s: New tests.
-
-2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
-
- * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for baddu,
- bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, syncw,
- syncws, vm3mulu, vm0 and vmulu.
- * gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: New test.
- * gas/mips/mips.exp: Run it. Run octeon test with
- run_dump_test_arches.
-
- * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for seq* and sne*.
- * gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: Add tests for seqi
- and snei.
-
-2008-06-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/i386.exp: Run sse-check-none and
- x86-64-sse-check-none.
-
- * gas/i386/sse-check-none.d: New.
- * gas/i386/sse-check-none.s: Likewise.
- * gas/i386/x86-64-sse-check-none.d: Likewise.
-
-2008-06-03 Paul Brook <paul@codesourcery.com>
-
- * gas/arm/thumb32.d: Update expected output.
-
-2008-05-30 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/x86-64-avx.s: Add tests for vmovd on 64bit operands.
-
- * gas/i386/x86-64-sse2avx.s: Add tests for movd on 64bit
- operands.
-
- * gas/testsuite/gas/i386/x86-64-avx.d: Updated.
- * gas/testsuite/gas/i386/x86-64-avx-intel.d: Likewise.
- * gas/testsuite/gas/i386/x86-64-sse2avx.d: Likewise.
-
-2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
-
- * gas/s390/zarch-z990.d (idte): Fix operand format.
-
-2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/sse-noavx.s: Add tests for cvtpd2pi, cvtpi2pd and
- cvttpd2pi.
- * gas/i386/x86-64-sse-noavx.s: Likewise.
-
- * gas/i386/sse-noavx.d: Updated.
- * gas/i386/x86-64-sse-noavx.d: Likewise.
-
-2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/6517
- * gas/i386/avx.s: Add tests for unspecified memory operand
- size in Intel syntax.
- * gas/i386/x86-64-avx.s: Likewise.
-
- * gas/i386/simd.s: Add tests for cvtsi2ss and cvtsi2sd with
- unspecified memory operand size in Intel syntax.
-
- * gas/i386/avx.d: Updated.
- * gas/i386/avx-intel.d: Likewise.
- * gas/i386/simd.d: Likewise.
- * gas/i386/simd-intel.d: Likewise.
- * gas/i386/simd-suffix.d: Likewise.
- * gas/i386/x86-64-avx.d: Likewise.
- * gas/i386/x86-64-avx-intel.d: Likewise.
-
-2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/sse-noavx.s: Add tests for movdq2q and movq2dq.
- * gas/i386/x86-64-sse-noavx.s: Likewise.
-
- * gas/i386/sse-noavx.d: Updated.
- * gas/i386/x86-64-sse-noavx.d: Likewise.
-
-2008-05-09 Catherine Moore <clm@codesourcery.com>
-
- * gas/mips/mips16-hilo-match.s: New test.
- * gas/mips/mip16-hilo-match.d: New test output.
-
-2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/i386.exp: Run movbe, movbe-intel, inval-movbe, ept,
- ept-intel, inval-ept, x86-64-movbe, x86-64-movbe-intel,
- x86-64-inval-movbe. x86-64-ept, x86-64-ept-intel and
- x86-64-inval-ept.
-
- * gas/i386/arch-10.s: Add movbe and invept.
- * gas/i386/x86-64-arch-2.s: Likewise.
-
- * gas/i386/ept.d: New file
- * gas/i386/ept-intel.d: Likewise.
- * gas/i386/ept.s: Likewise.
- * gas/i386/inval-ept.l: Likewise.
- * gas/i386/inval-ept.s: Likewise.
- * gas/i386/inval-movbe.l: Likewise.
- * gas/i386/inval-movbe.s: Likewise.
- * gas/i386/movbe.d: Likewise.
- * gas/i386/movbe-intel.d: Likewise.
- * gas/i386/movbe.s: Likewise.
- * gas/i386/x86-64-inval-ept.l: Likewise.
- * gas/i386/x86-64-inval-ept.s: Likewise.
- * gas/i386/x86-64-inval-movbe.l: Likewise.
- * gas/i386/x86-64-inval-movbe.s: Likewise.
- * gas/i386/x86-64-ept.d: Likewise.
- * gas/i386/x86-64-ept-intel.d: Likewise.
- * gas/i386/x86-64-ept.s: Likewise.
- * gas/i386/x86-64-movbe.d: Likewise.
- * gas/i386/x86-64-movbe-intel.d: Likewise.
- * gas/i386/x86-64-movbe.s: Likewise.
-
- * gas/i386/arch-10.d: Updated.
- * gas/i386/arch-10-1.l: Likewise.
- * gas/i386/arch-10-2.l: Likewise.
- * gas/i386/arch-10-3.l: Likewise.
- * gas/i386/arch-10-4.l: Likewise.
- * gas/i386/x86-64-arch-2.d: Likewise.
-
-2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
-
- * gas/mips/mips4.s: Split out fp instruction from here ...
- * gas/mips/mips4-fp.s: ... to here.
- * gas/mips/mips4.d: Update.
- * gas/mips/mips4-fp.l: New file. Check error messages with
- -msoft-float.
- * gas/mips/mips4-fp.d: New file. Check disassembly with
- hard-float.
-
- * gas/mips/mips32r2.s: Split out fp instructions from here ...
- * gas/mips/mips32r2-fp32.s: ... to here.
- * gas/mips/mips32r2.d: Update.
- * gas/mips/mips32r2-fp32.l: New file. Check error messages with
- -msoft-float.
- * gas/mips/mips32r2-fp32.d: New file. Check disassembly with
- hard-float.
-
- * gas/mips/mips32r2-ill-nofp.s, gas/mips/mips32r2-ill-nofp.l: New
- test derived from mips32r2-ill.
-
- * gas/mips/mips32-sf32.l: New list test for mips32-sf32.s to check
- error messages for soft-float targets.
-
- * gas/mips/mips-macro-ill-sfp.s, gas/mips/mips-macro-ill-sfp.l:
- New test for -msingle-float.
- * gas/mips/mips-macro-ill-nofp.s, gas/mips/mips-macro-ill-nofp.l:
- New test for -msoft-float.
- * gas/mips/mips-hard-float-flag.s,
- gas/mips/mips-hard-float-flag.l: New test for -mhard-float.
- * gas/mips/mips-double-float-flag.s,
- gas/mips/mips-double-float-flag.l: New test for -mdouble-float.
-
- * gas/mips/mips.exp: Run new mips4-fp and mips32r2-fp dump tests.
- Run mips4-fp and mips32r2-fp list tests with -msoft-float. Run
- new mips32r2-ill-nofp with -msoft-float. Run new mips32-sf32 list
- test with -msoft-float. Run new mips-macro-ill-sfp test with
- -msingle-float. Run new mips-macro-ill-nofp test with
- -msoft-float. Run new mips-hard-float-flag and
- mips-double-float-flag tests.
-
-2008-04-23 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/i386.exp: Run sse-noavx and x86-64-sse-noavx.
-
- * gas/i386/sse-noavx.d: New.
- * gas/i386/sse-noavx.s: Likewise.
- * gas/i386/x86-64-sse-noavx.d: Likewise.
- * gas/i386/x86-64-sse-noavx.s: Likewise.
-
-2008-04-23 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/sse2.s: Add tests for pmuludq, paddq and psubq.
- * gas/i386/x86-64-simd.s: Likewise.
-
- * gas/i386/sse2.d: Updated.
- * gas/i386/x86-64-simd.d: Likewise.
- * gas/i386/x86-64-simd-intel.d: Likewise.
- * gas/i386/x86-64-simd-suffix.d: Likewise.
-
-2008-04-23 David S. Miller <davem@davemloft.net>
-
- * gas/sparc/pc2210.d: New file.
- * gas/sparc/pc2210.d: Likewise.
- * gas/sparc/sparc.exp: Run new %pc22/%pc10 relocation test.
-
-2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/arch-10.d: Updated.
- * gas/i386/avx.d: Likewise.
- * gas/i386/avx-intel.d: Likewise.
+ * gas/i386/inval-avx.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
+ * gas/i386/x86-64-inval-avx.l: Likewise.
-2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
- Michael Meissner <michael.meissner@amd.com>
-
- * gas/i386/x86-64-sse5.s: Add protX tests to allow memory in the
- middle operand.
- * gas/i386/x86-64-sse5.d: Likewise.
-
-2008-04-16 David S. Miller <davem@davemloft.net>
-
- * gas/sparc/gotops32.d: New.
- * gas/sparc/gotops32.s: Likewise.
- * gas/sparc/gotops64.d: Likewise.
- * gas/sparc/gotops64.s: Likewise.
- * gas/sparc/sparc.exp: Run new gotdata tests.
-
-2008-04-15 Andrew Stubbs <andrew.stubbs@st.com>
-
- * gas/sh/arch/arch.exp: Align PC-relative instructions in the gererated
- assembly files.
- * gas/sh/arch/sh-dsp.s: Regenerate.
- * gas/sh/arch/sh.s: Regenerate.
- * gas/sh/arch/sh2.s: Regenerate.
- * gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s: Regenerate.
- * gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Regenerate.
- * gas/sh/arch/sh2a-nofpu.s: Regenerate.
- * gas/sh/arch/sh2a-or-sh3e.s: Regenerate.: Regenerate.
- * gas/sh/arch/sh2a-or-sh4.s: Regenerate.
- * gas/sh/arch/sh2a.s: Regenerate.
- * gas/sh/arch/sh2e.s: Regenerate.
- * gas/sh/arch/sh3-dsp.s: Regenerate.
- * gas/sh/arch/sh3-nommu.s: Regenerate.
- * gas/sh/arch/sh3.s: Regenerate.
- * gas/sh/arch/sh3e.s: Regenerate.
- * gas/sh/arch/sh4-nofpu.s: Regenerate.
- * gas/sh/arch/sh4-nommu-nofpu.s: Regenerate.
- * gas/sh/arch/sh4.s: Regenerate.
- * gas/sh/arch/sh4a-nofpu.s: Regenerate.
- * gas/sh/arch/sh4a.s: Regenerate.
- * gas/sh/arch/sh4al-dsp.s: Regenerate.
- * gas/sh/err-mova.s: New test.
-
-2008-04-14 Edmar Wienskoski <edmar@freescale.com>
-
- * gas/ppc/e500mc.s, gas/ppc/e500mc.d: New test.
- * gas/ppc/ppc.exp: Run the new test
-
-2008-04-11 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/lns/lns-big-delta.d: Updated.
- * gas/lns/lns-common-1.d: Likewise.
- * gas/lns/lns-common-1-alt.d: Likewise.
- * gas/lns/lns-duplicate.d: Likewise.
-
-2008-04-10 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/i386.exp: Run sse-check, sse-check-warn,
- sse-check-error, x86-64-sse-check, x86-64-sse-check-warn and
- x86-64-sse-check-error.
-
- * gas/i386/sse-check.d: New.
- * gas/i386/sse-check.s: Likewise.
- * gas/i386/sse-check-error.l: Likewise.
- * gas/i386/sse-check-error.s: Likewise.
- * gas/i386/sse-check-warn.d: Likewise.
- * gas/i386/sse-check-warn.e: Likewise.
- * gas/i386/x86-64-sse-check.d: Likewise.
- * gas/i386/x86-64-sse-check-error.l: Likewise.
- * gas/i386/x86-64-sse-check-error.s: Likewise.
- * gas/i386/x86-64-sse-check-warn.d: Likewise.
-
-2008-04-10 Santiago Urueña <suruena@gmail.com>
-
- * gas/all/gas.exp: Check the performance of the -ag command line
- switch.
-
-2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
-
- * gas/s390/zarch-z10.d: Map the compare and branch variants
- with odd condition code mask to version with an even mask.
-
-2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/att-regs.s: Add AVX register test.
- * gas/i386/intel-regs.s: Likewise.
-
- * gas/i386/att-regs.d: Updated.
- * gas/i386/intel-regs.d: Likewise.
-
-2008-04-07 Kaz Kojima <kkojima@rr.iij4u.or.jp>
-
- PR gas/6043
- * gas/sh/sh64/eh-1.d: New.
- * gas/sh/sh64/eh-1.d: Likewise.
-
-2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL.
- * gas/i386/arch-10-2.l: Likewise.
- * gas/i386/arch-10-3.l: Likewise.
- * gas/i386/arch-10-4.l: Likewise.
- * gas/i386/arch-10.s: Likewise.
- * gas/i386/clmul-intel.d: Likewise.
- * gas/i386/clmul.d: Likewise.
- * gas/i386/clmul.s: Likewise.
- * gas/i386/x86-64-arch-2.s: Likewise.
- * gas/i386/x86-64-clmul-intel.d: Likewise.
- * gas/i386/x86-64-clmul.d: Likewise.
- * gas/i386/x86-64-clmul.s: Likewise.
-
- * gas/i386/arch-10.d: Replace clmul with pclmul.
- * gas/i386/x86-64-arch-2.d: Likewise.
-
-2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
- x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
- x86-64-avx-intel and x86-64-inval-avx.
-
- * gas/cfi/cfi-i386.s: Add tests for AVX register maps.
- * gas/cfi/cfi-x86_64.s: Likewise.
-
- * gas/i386/aes.d: New.
- * gas/i386/aes.s: Likewise.
- * gas/i386/aes-intel.d: Likewise.
- * gas/i386/avx.d: Likewise.
- * gas/i386/avx.s: Likewise.
- * gas/i386/avx-intel.d: Likewise.
- * gas/i386/clmul.d: Likewise.
- * gas/i386/clmul-intel.d: Likewise.
- * gas/i386/clmul.s: Likewise.
- * gas/i386/i386.exp: Likewise.
- * gas/i386/inval-avx.l: Likewise.
+ * gas/i386/avx.s: Remove vpermil2ps/vpermil2pd and FMA
+ instructions. Update tests.
* gas/i386/inval-avx.s: Likewise.
- * gas/i386/sse2avx.d: Likewise.
- * gas/i386/sse2avx.s: Likewise.
- * gas/i386/x86-64-aes.d: Likewise.
- * gas/i386/x86-64-aes.s: Likewise.
- * gas/i386/x86-64-aes-intel.d: Likewise.
- * gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
- * gas/i386/x86-64-avx-intel.d: Likewise.
- * gas/i386/x86-64-clmul.d: Likewise.
- * gas/i386/x86-64-clmul-intel.d: Likewise.
- * gas/i386/x86-64-clmul.s: Likewise.
- * gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
- * gas/i386/x86-64-sse2avx.d: Likewise.
- * gas/i386/x86-64-sse2avx.s: Likewise.
-
- * gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
- * gas/i386/x86-64-arch-2.s: Likewise.
-
- * gas/i386/rexw.s: Add AVX tests.
-
- * gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
-
- * gas/cfi/cfi-i386.d: Updated.
- * gas/cfi/cfi-x86_64.d: Likewise.
- * gas/i386/arch-10.d: Likewise.
- * gas/i386/arch-10-1.l: Likewise.
- * gas/i386/arch-10-2.l: Likewise.
- * gas/i386/arch-10-3.l: Likewise.
- * gas/i386/arch-10-4.l: Likewise.
- * gas/i386/rexw.d: Likewise.
- * gas/i386/x86-64-arch-2.d: Likewise.
- * gas/i386/x86-64-opcode-inval.d: Likewise.
- * gas/i386/x86-64-opcode-inval-intel.d: Likewise.
-
-2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
-
- From Jie Zhang <jie.zhang@analog.com>
- * gas/bfin/load.d: Update.
- * gas/bfin/expected_comparison_errors.l: New test.
- * gas/bfin/expected_comparison_errors.s: New test.
- * gas/bfin/bfin.exp: Add expected_comparison_errors.
- * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add
- tests for bad options of "multiply and multipy-accumulate to
- accumulator" instructions. Add new vector instruction option
- mode tests.
- * gas/bfin/vector2.s: Add new vector instruction option mode test.
- * gas/bfin/vector2.d: Adjust accordingly.
- * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s:
- Add check for mismatch of accumulator and data register.
- * gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check
- for IU option.
-
- * gas/bfin/flow.d: Adjust since the generated labels for LOOP_BEGIN
- and LOOP_END instruction are local now.
- * gas/bfin/flow2.d: Likewise.
-
- From Mike Frysinger <michael.frysinger@analog.com>
- * gas/bfin/expected_errors.s, gas/bfin/expected_errors.l: Add test
- for mismatched half registers in vector multipy-accumulate
- instructions.
-
- From Robin Getz <rgetz@blackfin.uclinux.org>
- * gas/bfin/arithmetic.d: Update to reflect spaces/capitalization in
- recent changes in opcodes/bfin-dis.c.
- gas/bfin/arithmetic.s: Likewise.
- gas/bfin/bit.d: Likewise.
- gas/bfin/bit2.d: Likewise.
- gas/bfin/control_code.d: Likewise.
- gas/bfin/control_code2.d: Likewise.
- gas/bfin/event.d: Likewise.
- gas/bfin/event2.d: Likewise.
- gas/bfin/flow.d: Likewise.
- gas/bfin/flow2.d: Likewise.
- gas/bfin/load.d: Likewise.
- gas/bfin/logical.d: Likewise.
- gas/bfin/logical2.d: Likewise.
- gas/bfin/move.d: Likewise.
- gas/bfin/move2.d: Likewise.
- gas/bfin/parallel.d: Likewise.
- gas/bfin/parallel2.d: Likewise.
- gas/bfin/parallel3.d: Likewise.
- gas/bfin/parallel4.d: Likewise.
- gas/bfin/shift.d: Likewise.
- gas/bfin/shift2.d: Likewise.
- gas/bfin/stack.d: Likewise.
- gas/bfin/stack2.d: Likewise.
- gas/bfin/store.d: Likewise.
- gas/bfin/vector.d: Likewise.
- gas/bfin/vector2.d: Likewise.
- gas/bfin/video.d: Likewise.
- gas/bfin/video2.d: Likewise.
-
-2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
-
- * gas/s390/zarch-z10.d: New file.
- * gas/s390/zarch-z10.s: New file.
- * gas/s390/s390.exp: Run the z10 testcases.
-
-2008-03-17 Richard Sandiford <rsandifo@nildram.co.uk>
-
- * gas/mips/elf-rel26.d: Add -32.
- * gas/mips/mips16-intermix.d: Likewise.
-
-2008-03-13 Nick Clifton <nickc@redhat.com>
-
- PR gas/5895
- * gas/macros/exit.s: New test case.
- * gas/macros/macros.exp: Run the new test, expect it to produce an
- error result.
-
-2008-03-09 Paul Brook <paul@codesourcery.com>
-
- * gas/arm/vfpv3-d16-bad.d: New test.
- * gas/arm/vfpv3-d16-bad.l: New test.
-
-2008-03-06 Andreas Krebbel <krebbel1@de.ibm.com>
-
- * gas/s390/esa-g5.d (cdfbr, cdfr, cefbr, cefr, cxfbr, cxfr,
- dxr, fidr, fier, fixr, lzdr, lzer, lzxr, sqdr, sqer, tp): Fix
- operand format.
- * gas/s390/esa-g5.s: Likewise.
- * gas/s390/zarch-z900.d (cdgbr, cdgr, cegbr, cegr, cxgbr,
- cxgr): Likewise.
- * gas/s390/zarch-z900.s: Likewise.
- * gas/s390/zarch-z9-109.d (cu41, cu42): Remove mask operand.
- * gas/s390/zarch-z9-109.s: Likewise.
-
-2008-03-04 Paul Brook <paul@codesourcery.com>
-
- * gas/arm/archv6m.d: New test.
- * gas/arm/archv6m.s: New test.
- * gas/arm/t16-bad.s: Test low register non flag setting add.
- * gas/arm/t16-bad.l: Update expected output.
-
-2008-03-03 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/5543
- * gas/i386/i386.exp: Run inval-equ-1 and inval-equ-2.
-
- * gas/i386/inval-equ-1.l: New.
- * gas/i386/inval-equ-1.s: Likewise.
- * gas/i386/inval-equ-2.l: Likewise.
- * gas/i386/inval-equ-2.s: Likewise.
-
-2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/x86-64-branch.s: Add tests for 16-bit near indirect
- branches.
-
- * gas/i386/x86-64-inval.s: Remove tests for 16-bit near indirect
- branches.
-
- * gas/i386/x86-64-branch.d: Updated.
- * gas/i386/x86-64-inval.l: Likewise.
-
-2008-02-27 Nick Clifton <nickc@redhat.com>
-
- PR 3134
- * gas/h8300/pr3134.s: New test.
- * gas/h8300/pr3134.d: Expected disassembly
- * gas/h8300/h8300.exp: Run the new test.
-
- * gas/h8300/h8300-coff.exp: Fix test for COFF based ports to
- accept h8300-rtemscoff not just h8300-rtems.
-
-2008-02-26 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/jump.d: Updated for COFF.
-
-2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/jump.s: Add tests for far branches.
- * gas/i386/jump16.s: Likewise.
-
- * gas/i386/jump.d: Updated.
- * gas/i386/jump16.d: Likewise.
- * gas/i386/x86-64-inval.l: Likewise.
-
- * gas/i386/x86-64-inval.s: Add tests for 16-bit near indirect
- branches.
-
-2008-02-22 Nick Clifton <nickc@redhat.com>
-
- * gas/m68hc11/bug-1825.d: Update to match changes in the
- information generated with source-in-disassembly listings.
- * gas/m68hc11/indexed12.d: Likewise.
- * gas/m68hc11/insns-dwarf2.d: Likewise.
- * gas/m68hc11/lbranch-dwarf2.d: Likewise.
-
-2008-02-18 H.J. Lu <hongjiu.lu@intel.com>
-
- * cfi/cfi.exp (gas_x86_64_check): New.
- (gas_x86_32_check): Likewise.
- Run 32bit and 64bit tests for x86 targets if they are supportd.
-
-2008-02-18 Jan Beulich <jbeulich@novell.com>
-
- * gas/i386/att-regs.s, gas/i386/att-regs.d,
- gas/i386/intel-regs.s, gas/i386/intel-regs.d: New.
- * gas/i386/i386.exp: Run new tests.
-
-2008-02-14 Nick Clifton <nickc@redhat.com>
-
- PR gas/5712
- * gas/arm/fp-save.s: New test.
- * gas/arm/fp-save.d: Expected disassembly.
-
-2008-02-13 Adam Nemet <anemet@caviumnetworks.com>
-
- * gas/mips/branch-misc-2pic-64.d (#name): Have a unique name
- different from the branch-misc-2-64.d test.
-
-2008-02-13 Jan Beulich <jbeulich@novell.com>
-
- * gas/i386/intelok.s: Replace invalid offset expression with
- valid ones.
- * gas/i386/x86_64.s: Likewise.
-
-2008-02-13 Jan Beulich <jbeulich@novell.com>
-
- * gas/i386/intelbad.s, gas/i386/intelok.s: Add 'bound' tests.
- * gas/i386/intelbad.l, gas/i386/intelok.l, gas/i386/intelok.e,
- gas/i386/opcode-intel.d: Adjust.
-
-2008-02-13 Jan Beulich <jbeulich@novell.com>
-
- * gas/cfi/cfi-i386.s: Add code testing use of all registers.
- Fix a few comments.
- * gas/cfi/cfi-x86_64.s: Likewise.
- * gas/cfi/cfi-i386.d, gas/cfi/cfi-x86_64.d: Adjust.
-
-2008-02-12 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/i386.exp: Run x86-64-arch-2 instead of
- x86-64-arch-10.
-
- * gas/i386/x86-64-arch-10.d: Removed.
-
- * gas/i386/x86-64-arch-2.d: New.
- * gas/i386/x86-64-arch-2.s: Likewise.
-
-2008-02-12 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/x86-64-xsave.d: Remove prefix.
-
-2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/arch-10.s: Add xgetbv.
-
- * gas/i386/arch-10.d: Updated.
- * gas/i386/arch-10-1.l: Likewise.
- * gas/i386/arch-10-2.l: Likewise.
- * gas/i386/arch-10-3.l: Likewise.
- * gas/i386/arch-10-4.l: Likewise.
- * gas/i386/x86-64-arch-10.d: Likewise.
-
-2002-02-11 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/i386.exp: Run xsave, xsave-intel, x86-64-xsave
- and x86-64-xsave-intel.
-
- * gas/i386/x86-64-xsave-intel.d: New file.
- * gas/i386/x86-64-xsave.d: Likewise.
- * gas/i386/x86-64-xsave.s: Likewise.
- * gas/i386/xsave-intel.d: Likewise.
- * gas/i386/xsave.d: Likewise.
- * gas/i386/xsave.s: Likewise.
-
-2008-02-05 Adam Nemet <anemet@caviumnetworks.com>
-
- * gas/mips/mips.exp: Invoke the tests smartmips, mips32-dsp,
- mips32-dspr2, mips64-dsp and mips32-mt with run_dump_test instead
- of run_dump_test_arches.
- * gas/mips/smartmips.d: Pass -mips32.
- * gas/mips/mips64-dsp.d: Pass -mips64r2.
- * gas/mips/mips32-dsp.d: Pass -mips32r2.
- * gas/mips/mips32-dspr2.d: Likewise.
- * gas/mips/mips32-mt.d: Likewise.
-
-2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
-
- * gas/mips/mips.exp: Call mips_arch_create for Octeon. Invoke
- Octeon tests.
- * gas/mips/octeon.s, gas/mips/octeon.d: New test.
-
-2008-01-31 Marc Gauthier <marc@tensilica.com>
-
- * gas/all/gas.exp: Recognize Xtensa processor variants.
- * gas/elf/elf.exp: Likewise.
- * gas/lns/lns.exp: Likewise.
-
-2008-01-28 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/cfi/cfi-alpha-1.d: Replace DW_CFA_def_cfa_reg with
- DW_CFA_def_cfa_register.
- * gas/cfi/cfi-alpha-3.d: Likewise.
- * gas/cfi/cfi-hppa-1.d: Likewise.
- * gas/cfi/cfi-i386.d: Likewise.
- * gas/cfi/cfi-m68k.d: Likewise.
- * gas/cfi/cfi-mips-1.d: Likewise.
- * gas/cfi/cfi-sh-1.d: Likewise.
- * gas/cfi/cfi-sparc-1.d: Likewise.
- * gas/cfi/cfi-sparc64-1.d: Likewise.
- * gas/cfi/cfi-x86_64.d: Likewise.
-
- * gas/cfi/cfi-common-1.d: Updated for i386/x86-64 register
- names.
- * gas/cfi/cfi-common-2.d: Likewise.
- * gas/cfi/cfi-common-5.d: Likewise.
- * gas/cfi/cfi-i386.d: Likewise.
- * gas/cfi/cfi-x86_64.d: Likewise.
-
-2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/x86-64-sib.s: Add tests for r12.
-
- * gas/i386/x86-64-sib-intel.d: Updated.
- * gas/i386/x86-64-sib.d: Likewise.
-
-2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/i386.exp : Run x86-64-arch-1 and x86-64-arch-10.
-
- * gas/i386/x86-64-arch-1.d: New.
- * gas/i386/x86-64-arch-1.s: Likewise.
- * gas/i386/x86-64-arch-10.d: Likewise.
-
-2008-01-23 Tristan Gingold <gingold@adacore.com>
-
- * gas/ia64/regs.d: Updated as the ia64 disassembler now displays
- symbolic names for all ar registers.
-
-2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/arch-10.d: New.
- * gas/i386/arch-11.s: Likewise.
- * gas/i386/arch-12.d: Likewise.
- * gas/i386/arch-12.s: Likewise.
-
- * gas/i386/i386.exp: Run arch-11 and arch-12.
-
-2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/arch-10-1.l: New.
- * gas/i386/arch-10-1.s: Likewise.
- * gas/i386/arch-10-2.l: Likewise.
- * gas/i386/arch-10-2.s: Likewise.
- * gas/i386/arch-10-3.l: Likewise.
- * gas/i386/arch-10-3.s: Likewise.
- * gas/i386/arch-10-4.l: Likewise.
- * gas/i386/arch-10-4.s: Likewise.
- * gas/i386/arch-10.d: Likewise.
- * gas/i386/arch-10.s: Likewise.
-
- * gas/i386/i386.exp: Run arch-10, arch-10-1, arch-10-2,
- arch-10-3 and arch-10-4.
-
- * gas/i386/nops-2.s: Use movsbl instead of cmove.
- * gas/i386/nops-2-i386.d: Updated.
- * gas/i386/nops-2-merom.d: Likewise.
- * gas/i386/nops-2.d: Likewise.
- * gas/i386/x86-64-nops-2.d: Likewise.
-
-2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/prescott.s: Add tests for movddup in Intel syntax.
- * gas/i386/x86-64-prescott.s: Likewise.
-
- * gas/i386/prescott.d: Updated.
- * gas/i386/x86-64-prescott.d: Likewise.
-
-2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/i386.s: Add more tests for movsx and movzx.
- * gas/i386/x86_64.s: Likewise.
-
- * gas/i386/inval.s: Remove tests for movsxw and movzxw.
-
- * gas/i386/x86-64-inval.s: Remove tests for movsxb, movsxw,
- movsxl, movzxb and movzxw.
-
- * gas/i386/i386.d: Updated.
- * gas/i386/inval.l: Likewise.
- * gas/i386/x86_64.d: Likewise.
- * gas/i386/x86-64-inval.l: Likewise.
-
-2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/i386.s: Add tests for movsx, movzx and movnti.
- * gas/i386/inval.s: Likewise.
- * gas/i386/x86_64.s: Likewise.
- * gas/i386/x86-64-inval.s: Likewise.
-
- * gas/i386/i386.d: Updated.
- * gas/i386/inval.l: Likewise.
- * gas/i386/x86_64.d: Likewise.
- * gas/i386/x86-64-inval.l: Likewise.
-
-2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/5534
- * gas/i386/i386.s: Add tests for fnstsw and fstsw.
- * gas/i386/inval.s: Likewise.
- * gas/i386/x86_64.s: Likewise.
-
- * gas/i386/intel.s: Use word instead of dword on ss.
-
- * gas/i386/x86-64-inval.s: Add tests for fnstsw, fstsw, in
- and out.
-
- * gas/i386/prefix.s: Remove invalid fstsw.
-
- * gas/i386/inval.l: Updated.
- * gas/i386/intelbad.l: Likewise.
- * gas/i386/i386.d: Likewise.
- * gas/i386/x86_64.d: Likewise.
- * gas/i386/x86-64-inval.l: Likewise.
- * gas/i386/prefix.d: Updated.
-
-2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/nops.s: Add more tests with opcodes from 0x0f19
- to 0x0f1f.
- * gas/i386/x86-64-nops.s: Likewise.
-
- * gas/i386/nops.d: Updated.
- * gas/i386/x86-64-nops.d: Likewise.
-
-2008-01-09 Bob Wilson <bob.wilson@acm.org>
-
- * gas/lns/lns.exp: Run new lns-big-delta test for targets that set
- DWARF2_USE_FIXED_ADVANCE_PC.
- * gas/lns/lns-big-delta.s: New.
- * gas/lns/lns-big-delta.d: New.
-
-2008-01-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
-
- PR gas/5322
- * lib/gas-defs.exp (gas_host_run): Add fourth argument to regsub
- command.
-
-2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/intel.s: Add tests for fadd, faddp, fdiv, fdivp,
- fdivr, fdivrp, fmul, fmulp, fsub, fsubp, fsubr and fsubrp.
-
- * gas/i386/intel.d: Updated.
- * gas/i386/intel.e: Likewise.
-
-2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/rexw.d: New.
- * gas/i386/rexw.s: Likewise.
-
- * gas/i386/x86-64-sse4_1-intel.d: Updated.
- * gas/i386/x86-64-sse4_1.d: Likewise.
-
-2008-01-04 Nick Clifton <nickc@redhat.com>
-
- * gas/ppc/altivec_and_spe.s: New test - checks that ISA extension
- command line options (-maltivec, -mspe) can be specified before
- CPU selection command line options.
- * gas/ppc/altivec_and_spe.d: Expected disassembly.
- * gas/ppc/ppc.exp: Run the new test
-
-2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/arch-9.d: New file.
- * gas/i386/arch-9.s: Likewise.
-
- * gas/i386/i386.exp: Run arch-9.
-
-2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/arch-5.d: New file.
- * gas/i386/arch-5.s: Likewise.
- * gas/i386/arch-6.d: Likewise.
- * gas/i386/arch-6.s: Likewise.
- * gas/i386/arch-7.d: Likewise.
- * gas/i386/arch-7.s: Likewise.
- * gas/i386/arch-8.d: Likewise.
- * gas/i386/arch-8.s: Likewise.
-
- * gas/i386/i386.exp: Run arch-5, arch-6, arch-7 and arch-8.
-
-2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
-
- * gas/i386/i386.s: Add tests for movq.
- * gas/i386/x86_64.s: Likewise.
-
- * gas/i386/i386.d Updated.
- * gas/i386/x86_64.d: Likewise.
-
-2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/5534
- * gas/i386/intel.s: Use QWORD on movq instead of DWORD.
-
- * gas/i386/inval.s: Add tests for movq.
- * gas/i386/x86-64-inval.s: Likewise.
-
- * gas/i386/inval.l: Updated.
- * gas/i386/x86-64-inval.l: Likewise.
-2008-01-02 Catherine Moore <clm@codesourcery.com>
+ * gas/i386/fma.d: New.
+ * gas/i386/fma.s: Likewise.
+ * gas/i386/fma-intel.d: Likewise.
+ * gas/i386/x86-64-fma.d: Likewise.
+ * gas/i386/x86-64-fma.s: Likewise.
+ * gas/i386/x86-64-fma-intel.d: Likewise.
- * gas/mips/jalr.s: New test.
- * gas/mips/jalr.l: New test output.
- * gas/mips/mips.exp: Run new test.
+ * gas/i386/i386.exp: Run fma, fma-intel, x86-64-fma and
+ x86-64-fma-intel.
-For older changes see ChangeLog-2007
+For older changes see ChangeLog-2008
\f
Local Variables:
mode: change-log
--- /dev/null
+2008-12-30 Nick Clifton <nickc@redhat.com>
+
+ * gas/ppc/ppc.exp: Do not run the booke_xcoff64 test.
+ * gas/ppc/booke_xcoff64.s: Delete.
+ * gas/ppc/booke_xcoff64.d: Delete.
+
+2008-12-23 Jon Beniston <jon@beniston.com>
+
+ * gas/lm32: New directory.
+ * gas/lm32/all.exp: New file.
+ * gas/lm32/csr.d: New file.
+ * gas/lm32/csr.s: New file.
+ * gas/lm32/insn.d: New file.
+ * gas/lm32/insn.s: New file.
+
+2008-12-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp: Run x86-64-avx-swap and x86-64-avx-swap-intel.
+
+ * gas/i386/opts.s: Add tests for movsd, movss, vmovsd and
+ vmovss.
+ * gas/i386/x86-64-opts.s: Likewise.
+
+ * gas/i386/opts.d: Updated.
+ * gas/i386/opts-intel.d: Likewise.
+ * gas/i386/sse2avx-opts.d: Likewise.
+ * gas/i386/sse2avx-opts-intel.d: Likewise.
+ * gas/i386/x86-64-opts.d: Likewise.
+ * gas/i386/x86-64-opts-intel.d: Likewise.
+ * gas/i386/x86-64-sse2avx-opts.d: Likewise.
+ * gas/i386/x86-64-sse2avx-opts-intel.d: Likewise.
+
+ * gas/i386/x86-64-avx-swap.d: New.
+ * gas/i386/x86-64-avx-swap.s: Likewise.
+ * gas/i386/x86-64-avx-swap-intel.d: Likewise.
+
+2008-12-23 Nick Clifton <nickc@redhat.com>
+
+ * gas/elf/type.s: Remove test of STT_IFUNC support.
+ * gas/elf/type.e: Update expected output.
+
+2008-12-21 Hans-Peter Nilsson <hp@axis.com>
+
+ * gas/cris/rd-dtpoffd1.d, gas/cris/rd-dtpoffd1.s: New test.
+
+2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp: Run opts, opts-intel, sse2avx-opts,
+ sse2avx-opts-intel, x86-64-opts, x86-64-opts-intel,
+ x86-64-sse2avx-opts and x86-64-sse2avx-opts-intel.
+
+ * gas/i386/opts.d: New.
+ * gas/i386/opts-intel.d: Likewise.
+ * gas/i386/opts.s: Likewise.
+ * gas/i386/sse2avx-opts.d: Likewise.
+ * gas/i386/sse2avx-opts-intel.d: Likewise.
+ * gas/i386/x86-64-opts.d: Likewise.
+ * gas/i386/x86-64-opts-intel.d: Likewise.
+ * gas/i386/x86-64-opts.s: Likewise.
+ * gas/i386/x86-64-sse2avx-opts.d: Likewise.
+ * gas/i386/x86-64-sse2avx-opts-intel.d: Likewise.
+
+2008-12-20 Hans-Peter Nilsson <hp@axis.com>
+
+ * gas/cris/rd-tls-1.s, gas/cris/rd-tls-1.d: Test :IE and
+ decoration on double-indirect.
+ * gas/cris/tls-err-1.s: Test :IE on wrong-size operand.
+
+2008-12-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/intel.d: Remove trailing white spaces after nop.
+ * gas/i386/intelpic.d: Likewise.
+ * gas/i386/nops16-1.d: Likewise.
+ * gas/i386/nops-1-i686.d: Likewise.
+ * gas/i386/nops-3.d: Likewise.
+ * gas/i386/nops-3-i386.d: Likewise.
+ * gas/i386/nops-3-i686.d: Likewise.
+ * gas/i386/nops-4.d: Likewise.
+ * gas/i386/nops-4-i386.d: Likewise.
+ * gas/i386/nops-4-i686.d: Likewise.
+ * gas/i386/opcode.d: Likewise.
+ * gas/i386/opcode-suffix.d: Likewise.
+ * gas/i386/reloc.d: Likewise.
+ * gas/i386/tlsnopic.d: Likewise.
+ * gas/i386/x86-64-nops-1.d: Likewise.
+ * gas/i386/x86-64-nops-1-nocona.d: Likewise.
+ * gas/i386/x86-64-nops-2.d: Likewise.
+ * gas/i386/x86-64-nops-3.d: Likewise.
+ * gas/i386/x86-64-nops-4-core2.d: Likewise.
+ * gas/i386/x86-64-nops-4.d: Likewise.
+ * gas/i386/x86-64-nops-4-k8.d: Likewise.
+ * gas/i386/x86-64-opcode.d: Likewise.
+
+2008-12-15 Richard Earnshaw <rearnsha@arm.com>
+
+ * gas/arm/group-reloc-ldc.d: Disassembly of VFP instructions now uses
+ unified syntax.
+ * gas/arm/vfp-non-overlap.d: Likewise.
+ * gas/arm/vfp-neon-syntax.d: Likewise.
+ * gas/arm/vfp-neon-syntax_t2.d: Likewise.
+ * gas/arm/vfp1.d: Likewise.
+ * gas/arm/vfp1_t2.d: Likewise.
+ * gas/arm/vfp1xD.d: Likewise.
+ * gas/arm/vfp1xD_t2.d: Likewise.
+ * gas/arm/vfp2.d: Likewise.
+ * gas/arm/vfp2_t2.d: Likewise.
+ * gas/arm/vfpv3-32drs.d: Likewise.
+ * gas/arm/vfpv3-const-conv.d: Likewise.
+
+2008-12-04 Ben Elliston <bje@au.ibm.com>
+
+ * gas/ppc/booke.s: Remove booke64 instructions.
+ * gas/ppc/booke.d: Update expected disassembly output.
+ * gas/ppc/booke_xcoff.s: Use -mbooke/-Mbooke.
+ * gas/ppc/booke_xcoff.d: Likewise.
+ * gas/ppc/booke_xcoff64.d: Likewise.
+ * gas/ppc/booke_xcoff64.s: Likewise.
+
+2008-12-03 Nick Clifton <nickc@redhat.com>
+
+ * gas/elf/type.s: Add test of STT_IFUNC symbol type.
+ * gas/elf/type.e: Update expected disassembly.
+ * gas/elf/elf.exp: Update grep of symbol types.
+
+2008-11-27 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+ * gas/cr16/pic-1.s: New.
+ * gas/cr16/pic-1.d: New.
+ * gas/cr16/pic-2.s: New.
+ * gas/cr16/pic-2.d: New.
+ * gas/cr16/pic.exp: Run pic tests.
+
+2008-11-19 Hans-Peter Nilsson <hp@axis.com>
+
+ * gas/cris/rd-tls-1.d, gas/cris/rd-tls-1.s: Use a local thread
+ variable instead of .text location for :GD decoration test.
+
+2008-11-18 Catherine Moore <clm@codesourcery.com>
+
+ * gas/arm/half-prec-neon.d: New.
+ * gas/arm/half-prec-neon.s: New.
+ * gas/arm/half-prec-vfp3.d: New.
+ * gas/arm/half-prec-vfp3.s: New.
+ * gas/arm/half-prec-psyntax.d: New.
+ * gas/arm/half-prec-psyntax.s: New.
+
+2008-11-12 Hans-Peter Nilsson <hp@axis.com>
+
+ * gas/cris/rd-bcnst2-pic.d, gas/cris/rd-bcnst2.d,
+ gas/cris/rd-bcnst2.s: New tests.
+
+2008-11-06 Adam Nemet <anemet@caviumnetworks.com>
+
+ * gas/mips/mips1-fp.s, testsuite/gas/mips/mips1-fp.d,
+ testsuite/gas/mips/mips1-fp.l: New tests.
+ * gas/mips/mips.exp: Run them.
+
+2008-11-06 Chao-ying Fu <fu@mips.com>
+
+ * gas/mips/mips32-sync.d, gas/mip/mips32-sync.s: New tests.
+ * gas/mips/mips.exp: Run them.
+
+2008-11-04 Bob Wilson <bob.wilson@acm.org>
+
+ * gas/xtensa/all.exp: Run jlong test.
+ * gas/xtensa/jlong.d: New.
+ * gas/xtensa/jlong.s: New.
+
+2008-11-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/intel.s: Add tests for cmovpe and cmovpo.
+ * gas/i386/opcode.s: Likewise.
+
+ * gas/i386/intel.d: Updated.
+ * gas/i386/opcode.d: Likewise.
+ * gas/i386/opcode-intel.d: Likewise.
+ * gas/i386/opcode-suffix.d: Likewise.
+
+2008-10-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp: Run nops-5, nops-5-i686, x86-64-nops-5 and
+ x86-64-nops-5-k8.
+
+ * gas/i386/nops-5.d: New.
+ * gas/i386/nops-5.s: Likewise.
+ * gas/i386/nops-5-i686.d: Likewise.
+ * gas/i386/x86-64-nops-5.d: Likewise.
+ * gas/i386/x86-64-nops-5-k8.d: Likewise.
+
+2008-10-06 Tom Tromey <tromey@redhat.com>
+
+ * gas/cfi/cfi-alpha-1.d, gas/cfi/cfi-alpha-3.d,
+ gas/cfi/cfi-arm-1.d, gas/cfi/cfi-common-1.d,
+ gas/cfi/cfi-common-2.d, gas/cfi/cfi-common-3.d,
+ gas/cfi/cfi-common-4.d, gas/cfi/cfi-common-5.d,
+ gas/cfi/cfi-common-6.d, gas/cfi/cfi-hppa-1.d,
+ gas/cfi/cfi-i386-2.d, gas/cfi/cfi-i386.d, gas/cfi/cfi-m68k.d,
+ gas/cfi/cfi-mips-1.d, gas/cfi/cfi-ppc-1.d, gas/cfi/cfi-s390-1.d,
+ gas/cfi/cfi-s390x-1.d, gas/cfi/cfi-sh-1.d, gas/cfi/cfi-sparc-1.d,
+ gas/cfi/cfi-sparc64-1.d, gas/cfi/cfi-x86_64.d: Update for readelf
+ change.
+
+2008-10-04 Hans-Peter Nilsson <hp@axis.com>
+
+ * gas/cris/rd-tls-1.s, gas/cris/rd-tls-1.d, gas/cris/rd-tls-2.s,
+ gas/cris/rd-tls-2.d, gas/cris/tls-err-1.s, gas/cris/tls-err-2.s,
+ gas/cris/tls-err-3.s: New tests.
+
+2008-09-26 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * gas/s390/esa-g5.d: Adjust according to the s390-opc changes.
+ * gas/s390/esa-g5.s: Likewise.
+ * gas/s390/esa-z990.d: Likewise.
+ * gas/s390/esa-z990.s: Likewise.
+ * gas/s390/zarch-z900.d: Likewise.
+ * gas/s390/zarch-z900.s: Likewise.
+ * gas/s390/zarch-z990.d: Likewise.
+ * gas/s390/zarch-z990.s: Likewise.
+
+2008-09-15 Alan Modra <amodra@bigpond.net.au>
+
+ * gas/all/gas.exp: Don't run redef tests on a bunch of targets.
+ * gas/elf/elf.exp: Likewise.
+
+2008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
+
+ * gas/z80/ld-group.s, gas/z80/ld-group.d: New test.
+ * gas/z80/block.s, gas/z80/block.d: New test
+ * gas/z80/arith.s, gas/z80/arith.d: New test
+ * gas/z80/rotate.s, gas/z80/rotate.d: New test
+ * gas/z80/bit.s, gas/z80/bit.d: New test
+ * gas/z80/branch.s, gas/z80/branch.d: New test
+ * gas/z80/inout.s, gas/z80/inout.d: New test
+ * gas/z80/misc.s, gas/z80/misc.d: New test
+ * gas/z80/z80.exp: Run them.
+
+2008-09-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/sse2avx.s: Remove pclmulXXX tests. Add tests for
+ Intel syntax.
+ * gas/i386/x86-64-sse2avx.s: Likewise.
+
+ * gas/i386/sse2avx.d: Updated.
+ * gas/i386/x86-64-sse2avx.d: Likewise.
+
+2008-09-09 Peter Bergner <bergner@vnet.ibm.com>
+
+ * gas/ppc/common.s: New test.
+ * gas/ppc/common.d: Likewise.
+ * gas/ppc/power4_32.s: Likewise.
+ * gas/ppc/power4_32.d: Likewise.
+ * gas/ppc/power6.s: Add attn, mtcr, mtcrf, mfcr, dcbz.
+ * gas/ppc/power6.d: Likewise.
+ * gas/ppc/ppc.exp: Run power4_32 test.
+
+2008-09-06 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * gas/mips/cfi-n64-1.s, gas/mips/cfi-n64-1.d: New test.
+ * gas/mips/mips.exp: Run it.
+
+2008-09-05 Nick Clifton <nickc@redhat.com>
+
+ * gas/arm/abs12.d: Update expected disassembly.
+ * gas/arm/tls_vxworks.d: Likewise.
+ * gas/arm/unwind_vxworks.d: Likewise.
+ * gas/arm/group-reloc-alu-encoding-bad.d: Skip for vxworks
+ targets.
+ * gas/arm/group-reloc-alu.d: Likewise.
+ * gas/arm/group-reloc-ldc-encoding-bad.d: Likewise.
+ * gas/arm/group-reloc-ldc.d: Likewise.
+ * gas/arm/group-reloc-ldr-encoding-bad.d: Likewise.
+ * gas/arm/group-reloc-ldr.d: Likewise.
+ * gas/arm/group-reloc-ldrs-encoding-bad.d: Likewise.
+ * gas/arm/group-reloc-ldrs.d: Likewise.
+ * gas/arm/local_function.d: Likewise.
+ * gas/arm/mapshort-elf.d: Likewise.
+ * gas/arm/undefined.d: Likewise.
+
+2008-09-04 Christian Groessler <chris@groessler.org>
+
+ * lib/gas-defs.exp (run_dump_test): If the test expects an error,
+ fail the test if gas doesn't report an error.
+
+2008-08-28 Jan Beulich <jbeulich@novell.com>
+
+ * gas/i386/intel.s: Add retf.
+ * gas/i386/intel.{d,e}: Adjust.
+ * gas/i386/opcode-intel.d: Replace lret with retf.
+
+2008-08-28 Jan Beulich <jbeulich@novell.com>
+
+ * gas/i386/gas/i386/opcode-suffix.d: Add suffixes to cmovXX.
+
+2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/ia64/dv-raw-err.s: Add tests for cr.iib0 and cr.iib1.
+ * gas/ia64/dv-waw-err.s: Likewise.
+ * gas/ia64/regs.s: Likewise.
+
+ * gas/ia64/dv-raw-err.l: Updated.
+ * gas/ia64/dv-waw-err.l: Likewise.
+ * gas/ia64/regs.d: Likewise.
+
+2008-08-28 Jan Beulich <jbeulich@novell.com>
+
+ * gas/i386/string-bad.{l,s}, gas/i386/string-ok.{d,e,s}: New.
+ * gas/i386/i386.exp: Run new tests.
+
+2008-08-27 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/intel.s: Add tests for fidivr.
+
+ * gas/i386/intel.d: Updated.
+
+2008-08-26 Jie Zhang <jie.zhang@analog.com>
+
+ * gas/bfin/arith_mode.d: New test.
+ * gas/bfin/arith_mode.s: New test.
+ * gas/bfin/invalid_arith_mode.l: New test.
+ * gas/bfin/invalid_arith_mode.s: New test.
+ * gas/bfin/bfin.exp: Add arith_mode and invalid_arith_mode.
+
+2008-08-22 Jie Zhang <jie.zhang@analog.com>
+
+ * gas/bfin/misc.s: New test.
+ * gas/bfin/misc.d: New test.
+ * gas/bfin/bfin.exp: Add misc test.
+
+2008-08-21 Richard Henderson <rth@redhat.com>
+
+ * gas/cfi/cfi-common-1.d: Allow for differing offsets, and
+ for DW_CFA_offset_extended_sf results. Allow for differing nops.
+ * gas/cfi/cfi-hppa-1.d: Invert data alignment sign. Change
+ offsets to match 64-bit offsets.
+ * gas/cfi/cfi.exp: Don't run common tests on hppa64.
+
+2008-08-20 Bob Wilson <bob.wilson@acm.org>
+
+ * gas/all/gas.exp: Expect the redef test to fail on Xtensa.
+
+2008-08-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ AVX Programming Reference (August, 2008)
+ * gas/i386/avx.s: Add AES + AVX tests.
+ * gas/i386/arch-10.s: Likewise.
+ * gas/i386/sse2avx.s: Likewise.
+ * gas/i386/x86-64-arch-2.s: Likewise.
+ * gas/i386/x86-64-avx.s: Likewise.
+ * gas/i386/x86-64-sse2avx.s: Likewise.
+
+ * gas/i386/arch-10.d: Updated.
+ * gas/i386/arch-10-1.l: Likewise.
+ * gas/i386/arch-10-2.l: Likewise.
+ * gas/i386/arch-10-3.l: Likewise.
+ * gas/i386/arch-10-4.l: Likewise.
+ * gas/i386/avx.d: Likewise.
+ * gas/i386/avx-intel.d: Likewise.
+ * gas/i386/sse2avx.d: Likewise.
+ * gas/i386/x86-64-arch-2.d: Likewise.
+ * gas/i386/x86-64-avx.d: Likewise.
+ * gas/i386/x86-64-avx-intel.d: Likewise.
+ * gas/i386/x86-64-sse2avx.d: Likewise.
+
+ * gas/i386/i386.exp: Run arch-avx-1, arch-avx-1-1 and
+ arch-avx-1-2.
+
+ * gas/i386/arch-avx-1.d: New.
+ * gas/i386/arch-avx-1.s: Likewise.
+ * gas/i386/arch-avx-1-1.l: Likewise.
+ * gas/i386/arch-avx-1-1.s: Likewise.
+ * gas/i386/arch-avx-1-2.l: Likewise.
+ * gas/i386/arch-avx-1-2.s: Likewise.
+
+2008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * gas/s390/esa-g5.d: lxr operands are floating point.
+ * gas/s390/esa-g5.s: Likewise.
+ * gas/testsuite/gas/s390/zarch-z9-ec.d: rrdtr, rrxtr third
+ operands is gpr.
+ * gas/testsuite/gas/s390/zarch-z9-ec.s: Likewise.
+
+2008-08-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/amd.s: Add syscall and sysret. Remove padding.
+
+ * gas/i386/amd.d: Updated.
+ * gas/i386/x86-64-opcode.d: Likewise.
+
+ * gas/i386/i386.exp: Run x86-64-intel64.
+
+ * gas/i386/x86-64-intel64.d: New.
+ * gas/i386/x86-64-intel64.s: Likewise.
+
+ * gas/i386/x86-64-opcode.s: Add syscall and sysret.
+
+2008-08-08 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * gas/mips/call-nonpic-1.s, gas/mips/call-nonpic-1.d: New test.
+ * gas/mips/mips.exp: Run it.
+
+2008-08-06 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * gas/mips/elf-rel8-mips16.d, gas/mips/elf-rel8-mips16.s,
+ * gas/mips/elf-rel9-mips16.d, gas/mips/elf-rel9-mips16.s,
+ * gas/mips/elf-rel13-mips16.d, gas/mips/elf-rel13-mips16.s: New tests.
+ * gas/mips/mips.exp: Run them.
+
+2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ * gas/ppc/power7.d: New.
+ * gas/ppc/power7.s: Likewise.
+ * gas/ppc/ppc.exp: Run power7 test.
+
+2008-08-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/cfi/cfi-i386.s: Remove tests for AVX register maps.
+ * gas/cfi/cfi-x86_64.s: Likewise.
+
+ * gas/cfi/cfi-i386.d: Updated.
+ * gas/cfi/cfi-x86_64.d: Likewise.
+
+2008-07-31 Peter Bergner <bergner@vnet.ibm.com>
+
+ * gas/ppc/cell.s: Add altivec instructions.
+ * gas/ppc/cell.d: Update expected output.
+ * gas/ppc/power6.d: New.
+ * gas/ppc/power6.s: Likewise.
+ * gas/ppc/ppc.exp (powerpc64*-*-*): Move cell from here to...
+ (powerpc*-*-*): Here. Run power6 test.
+
+2008-07-24 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/nops-1.d: Add -mtune=generic32.
+ * gas/i386/nops-2.d: Likewise.
+ * gas/i386/nops-3.d: Likewise.
+
+ * gas/i386/x86-64-nops-1.d: Add -mtune=generic64.
+ * gas/i386/x86-64-nops-2.d: Likewise.
+ * gas/i386/x86-64-nops-3.d: Likewise.
+ * gas/i386/x86-64-nops-4.d: Likewise.
+
+2008-07-22 Chao-ying Fu <fu@mips.com>
+
+ * gas/mips/tls-ill.l: Update error message.
+ * gas/mips/octeon-ill.l: Likewise.
+
+2008-07-14 Jie Zhang <jie.zhang@analog.com>
+
+ * gas/bfin/{bit2.s, cache2.s, control_code2.s, event2.s,
+ logical2.s, move2.s, parallel.s, parallel2.s, parallel3.s,
+ parallel4.s, shift2.s, stack2.s, video2.s}: Remove DOS line
+ endings.
+
+2008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * gas/mips/mips16-vis-1.d, gas/mips/mips16-vis-1.s: New tests.
+ * gas/mips/mips.exp: Run them.
+
+2008-07-09 Kai Tietz <kai.tietz@onevision.com>
+
+ * gas/i386/i386.exp (x86-64-pcrel): Disable for w64.
+ (x86-64-sse5): Likewise.
+ (x86-64-opcode-inval): Likewise.
+ (x86-64-opcode-inval-intel): Likewise.
+ (x86-64-w64-pcrel): New.
+ * gas/i386/x86-64-w64-pcrel.d: New.
+
+2008-07-07 Adam Nemet <anemet@caviumnetworks.com>
+
+ * gas/mips/mips32.s: Move out coprocessor2 insns from here ...
+ * gas/mips/mips32-cp2.s: ... to here.
+ * gas/mips/mips32.d: Update.
+ * gas/mips/mips32-cp2.d: New file.
+ * gas/mips/mips32r2.s: Move out coprocessor2 insns from here ...
+ * gas/mips/mips32r2-cp2.s: ... to here.
+ * gas/mips/mips32r2.d: Update.
+ * gas/mips/mips32r2-cp2.d: New file.
+ * gas/mips/mips64.s: Move out coprocessor2 insns from here ...
+ * gas/mips/mips64-cp2.s: ... to here.
+ * gas/mips/mips64.d: Update.
+ * gas/mips/mips64-cp2.d: New file.
+ * gas/mips/mips.exp: Run mips32-cp2, mips32r2-cp2 and mips64-cp
+ except for Octeon.
+ * gas/mips/octeon.s: Add supported coprocessor insns. Move pop
+ down to keep alphabetical order.
+ * gas/mips/octeon.d: Update.
+ * gas/mips/octeon-ill.s: Add unsupported coprocessor insns.
+ * gas/mips/octeon-ill.l: Update.
+
+2008-07-07 Paul Brook <paul@codesourcery.com>
+
+ * gas/arm/movw-local.d: New test.
+ * gas/arm/movw-local.s: New test.
+
+2008-06-27 Chao-ying Fu <fu@mips.com>
+
+ * gas/mips/odd-float.d: Replace ... with #pass.
+ * gas/mips/ldstla-32-shared.d: Add -march=mips1 for as.
+ * gas/mips/ldstla-32.d: Likewise.
+ * gas/mips/mips16-hilo-match.d: Add -mabi=32 -march=mips1 for as.
+
+2008-06-19 Chao-ying Fu <fu@mips.com>
+
+ * gas/mips/e32-rel2.d: Add -march=mips1 for as.
+
+2008-06-16 Hans-Peter Nilsson <hp@bitrange.com>
+
+ PR gas/6607
+ * gas/mmix/err-loc-10.s, gas/mmix/err-loc-9.s, gas/mmix/loc-6.d,
+ gas/mmix/loc-6.s, gas/mmix/loc-7.d, gas/mmix/loc-7.s: New tests.
+
+2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
+
+ * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for baddu,
+ bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs, syncw,
+ syncws, vm3mulu, vm0 and vmulu.
+ * gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: New test.
+ * gas/mips/mips.exp: Run it. Run octeon test with
+ run_dump_test_arches.
+
+ * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for seq* and sne*.
+ * gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: Add tests for seqi
+ and snei.
+
+2008-06-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp: Run sse-check-none and
+ x86-64-sse-check-none.
+
+ * gas/i386/sse-check-none.d: New.
+ * gas/i386/sse-check-none.s: Likewise.
+ * gas/i386/x86-64-sse-check-none.d: Likewise.
+
+2008-06-03 Paul Brook <paul@codesourcery.com>
+
+ * gas/arm/thumb32.d: Update expected output.
+
+2008-05-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/x86-64-avx.s: Add tests for vmovd on 64bit operands.
+
+ * gas/i386/x86-64-sse2avx.s: Add tests for movd on 64bit
+ operands.
+
+ * gas/testsuite/gas/i386/x86-64-avx.d: Updated.
+ * gas/testsuite/gas/i386/x86-64-avx-intel.d: Likewise.
+ * gas/testsuite/gas/i386/x86-64-sse2avx.d: Likewise.
+
+2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
+
+ * gas/s390/zarch-z990.d (idte): Fix operand format.
+
+2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/sse-noavx.s: Add tests for cvtpd2pi, cvtpi2pd and
+ cvttpd2pi.
+ * gas/i386/x86-64-sse-noavx.s: Likewise.
+
+ * gas/i386/sse-noavx.d: Updated.
+ * gas/i386/x86-64-sse-noavx.d: Likewise.
+
+2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/6517
+ * gas/i386/avx.s: Add tests for unspecified memory operand
+ size in Intel syntax.
+ * gas/i386/x86-64-avx.s: Likewise.
+
+ * gas/i386/simd.s: Add tests for cvtsi2ss and cvtsi2sd with
+ unspecified memory operand size in Intel syntax.
+
+ * gas/i386/avx.d: Updated.
+ * gas/i386/avx-intel.d: Likewise.
+ * gas/i386/simd.d: Likewise.
+ * gas/i386/simd-intel.d: Likewise.
+ * gas/i386/simd-suffix.d: Likewise.
+ * gas/i386/x86-64-avx.d: Likewise.
+ * gas/i386/x86-64-avx-intel.d: Likewise.
+
+2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/sse-noavx.s: Add tests for movdq2q and movq2dq.
+ * gas/i386/x86-64-sse-noavx.s: Likewise.
+
+ * gas/i386/sse-noavx.d: Updated.
+ * gas/i386/x86-64-sse-noavx.d: Likewise.
+
+2008-05-09 Catherine Moore <clm@codesourcery.com>
+
+ * gas/mips/mips16-hilo-match.s: New test.
+ * gas/mips/mip16-hilo-match.d: New test output.
+
+2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp: Run movbe, movbe-intel, inval-movbe, ept,
+ ept-intel, inval-ept, x86-64-movbe, x86-64-movbe-intel,
+ x86-64-inval-movbe. x86-64-ept, x86-64-ept-intel and
+ x86-64-inval-ept.
+
+ * gas/i386/arch-10.s: Add movbe and invept.
+ * gas/i386/x86-64-arch-2.s: Likewise.
+
+ * gas/i386/ept.d: New file
+ * gas/i386/ept-intel.d: Likewise.
+ * gas/i386/ept.s: Likewise.
+ * gas/i386/inval-ept.l: Likewise.
+ * gas/i386/inval-ept.s: Likewise.
+ * gas/i386/inval-movbe.l: Likewise.
+ * gas/i386/inval-movbe.s: Likewise.
+ * gas/i386/movbe.d: Likewise.
+ * gas/i386/movbe-intel.d: Likewise.
+ * gas/i386/movbe.s: Likewise.
+ * gas/i386/x86-64-inval-ept.l: Likewise.
+ * gas/i386/x86-64-inval-ept.s: Likewise.
+ * gas/i386/x86-64-inval-movbe.l: Likewise.
+ * gas/i386/x86-64-inval-movbe.s: Likewise.
+ * gas/i386/x86-64-ept.d: Likewise.
+ * gas/i386/x86-64-ept-intel.d: Likewise.
+ * gas/i386/x86-64-ept.s: Likewise.
+ * gas/i386/x86-64-movbe.d: Likewise.
+ * gas/i386/x86-64-movbe-intel.d: Likewise.
+ * gas/i386/x86-64-movbe.s: Likewise.
+
+ * gas/i386/arch-10.d: Updated.
+ * gas/i386/arch-10-1.l: Likewise.
+ * gas/i386/arch-10-2.l: Likewise.
+ * gas/i386/arch-10-3.l: Likewise.
+ * gas/i386/arch-10-4.l: Likewise.
+ * gas/i386/x86-64-arch-2.d: Likewise.
+
+2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
+
+ * gas/mips/mips4.s: Split out fp instruction from here ...
+ * gas/mips/mips4-fp.s: ... to here.
+ * gas/mips/mips4.d: Update.
+ * gas/mips/mips4-fp.l: New file. Check error messages with
+ -msoft-float.
+ * gas/mips/mips4-fp.d: New file. Check disassembly with
+ hard-float.
+
+ * gas/mips/mips32r2.s: Split out fp instructions from here ...
+ * gas/mips/mips32r2-fp32.s: ... to here.
+ * gas/mips/mips32r2.d: Update.
+ * gas/mips/mips32r2-fp32.l: New file. Check error messages with
+ -msoft-float.
+ * gas/mips/mips32r2-fp32.d: New file. Check disassembly with
+ hard-float.
+
+ * gas/mips/mips32r2-ill-nofp.s, gas/mips/mips32r2-ill-nofp.l: New
+ test derived from mips32r2-ill.
+
+ * gas/mips/mips32-sf32.l: New list test for mips32-sf32.s to check
+ error messages for soft-float targets.
+
+ * gas/mips/mips-macro-ill-sfp.s, gas/mips/mips-macro-ill-sfp.l:
+ New test for -msingle-float.
+ * gas/mips/mips-macro-ill-nofp.s, gas/mips/mips-macro-ill-nofp.l:
+ New test for -msoft-float.
+ * gas/mips/mips-hard-float-flag.s,
+ gas/mips/mips-hard-float-flag.l: New test for -mhard-float.
+ * gas/mips/mips-double-float-flag.s,
+ gas/mips/mips-double-float-flag.l: New test for -mdouble-float.
+
+ * gas/mips/mips.exp: Run new mips4-fp and mips32r2-fp dump tests.
+ Run mips4-fp and mips32r2-fp list tests with -msoft-float. Run
+ new mips32r2-ill-nofp with -msoft-float. Run new mips32-sf32 list
+ test with -msoft-float. Run new mips-macro-ill-sfp test with
+ -msingle-float. Run new mips-macro-ill-nofp test with
+ -msoft-float. Run new mips-hard-float-flag and
+ mips-double-float-flag tests.
+
+2008-04-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp: Run sse-noavx and x86-64-sse-noavx.
+
+ * gas/i386/sse-noavx.d: New.
+ * gas/i386/sse-noavx.s: Likewise.
+ * gas/i386/x86-64-sse-noavx.d: Likewise.
+ * gas/i386/x86-64-sse-noavx.s: Likewise.
+
+2008-04-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/sse2.s: Add tests for pmuludq, paddq and psubq.
+ * gas/i386/x86-64-simd.s: Likewise.
+
+ * gas/i386/sse2.d: Updated.
+ * gas/i386/x86-64-simd.d: Likewise.
+ * gas/i386/x86-64-simd-intel.d: Likewise.
+ * gas/i386/x86-64-simd-suffix.d: Likewise.
+
+2008-04-23 David S. Miller <davem@davemloft.net>
+
+ * gas/sparc/pc2210.d: New file.
+ * gas/sparc/pc2210.d: Likewise.
+ * gas/sparc/sparc.exp: Run new %pc22/%pc10 relocation test.
+
+2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/arch-10.d: Updated.
+ * gas/i386/avx.d: Likewise.
+ * gas/i386/avx-intel.d: Likewise.
+ * gas/i386/x86-64-arch-2.d: Likewise.
+ * gas/i386/x86-64-avx.d: Likewise.
+ * gas/i386/x86-64-avx-intel.d: Likewise.
+
+2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+ Michael Meissner <michael.meissner@amd.com>
+
+ * gas/i386/x86-64-sse5.s: Add protX tests to allow memory in the
+ middle operand.
+ * gas/i386/x86-64-sse5.d: Likewise.
+
+2008-04-16 David S. Miller <davem@davemloft.net>
+
+ * gas/sparc/gotops32.d: New.
+ * gas/sparc/gotops32.s: Likewise.
+ * gas/sparc/gotops64.d: Likewise.
+ * gas/sparc/gotops64.s: Likewise.
+ * gas/sparc/sparc.exp: Run new gotdata tests.
+
+2008-04-15 Andrew Stubbs <andrew.stubbs@st.com>
+
+ * gas/sh/arch/arch.exp: Align PC-relative instructions in the gererated
+ assembly files.
+ * gas/sh/arch/sh-dsp.s: Regenerate.
+ * gas/sh/arch/sh.s: Regenerate.
+ * gas/sh/arch/sh2.s: Regenerate.
+ * gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s: Regenerate.
+ * gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Regenerate.
+ * gas/sh/arch/sh2a-nofpu.s: Regenerate.
+ * gas/sh/arch/sh2a-or-sh3e.s: Regenerate.: Regenerate.
+ * gas/sh/arch/sh2a-or-sh4.s: Regenerate.
+ * gas/sh/arch/sh2a.s: Regenerate.
+ * gas/sh/arch/sh2e.s: Regenerate.
+ * gas/sh/arch/sh3-dsp.s: Regenerate.
+ * gas/sh/arch/sh3-nommu.s: Regenerate.
+ * gas/sh/arch/sh3.s: Regenerate.
+ * gas/sh/arch/sh3e.s: Regenerate.
+ * gas/sh/arch/sh4-nofpu.s: Regenerate.
+ * gas/sh/arch/sh4-nommu-nofpu.s: Regenerate.
+ * gas/sh/arch/sh4.s: Regenerate.
+ * gas/sh/arch/sh4a-nofpu.s: Regenerate.
+ * gas/sh/arch/sh4a.s: Regenerate.
+ * gas/sh/arch/sh4al-dsp.s: Regenerate.
+ * gas/sh/err-mova.s: New test.
+
+2008-04-14 Edmar Wienskoski <edmar@freescale.com>
+
+ * gas/ppc/e500mc.s, gas/ppc/e500mc.d: New test.
+ * gas/ppc/ppc.exp: Run the new test
+
+2008-04-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/lns/lns-big-delta.d: Updated.
+ * gas/lns/lns-common-1.d: Likewise.
+ * gas/lns/lns-common-1-alt.d: Likewise.
+ * gas/lns/lns-duplicate.d: Likewise.
+
+2008-04-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp: Run sse-check, sse-check-warn,
+ sse-check-error, x86-64-sse-check, x86-64-sse-check-warn and
+ x86-64-sse-check-error.
+
+ * gas/i386/sse-check.d: New.
+ * gas/i386/sse-check.s: Likewise.
+ * gas/i386/sse-check-error.l: Likewise.
+ * gas/i386/sse-check-error.s: Likewise.
+ * gas/i386/sse-check-warn.d: Likewise.
+ * gas/i386/sse-check-warn.e: Likewise.
+ * gas/i386/x86-64-sse-check.d: Likewise.
+ * gas/i386/x86-64-sse-check-error.l: Likewise.
+ * gas/i386/x86-64-sse-check-error.s: Likewise.
+ * gas/i386/x86-64-sse-check-warn.d: Likewise.
+
+2008-04-10 Santiago Urueña <suruena@gmail.com>
+
+ * gas/all/gas.exp: Check the performance of the -ag command line
+ switch.
+
+2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * gas/s390/zarch-z10.d: Map the compare and branch variants
+ with odd condition code mask to version with an even mask.
+
+2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/att-regs.s: Add AVX register test.
+ * gas/i386/intel-regs.s: Likewise.
+
+ * gas/i386/att-regs.d: Updated.
+ * gas/i386/intel-regs.d: Likewise.
+
+2008-04-07 Kaz Kojima <kkojima@rr.iij4u.or.jp>
+
+ PR gas/6043
+ * gas/sh/sh64/eh-1.d: New.
+ * gas/sh/sh64/eh-1.d: Likewise.
+
+2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL.
+ * gas/i386/arch-10-2.l: Likewise.
+ * gas/i386/arch-10-3.l: Likewise.
+ * gas/i386/arch-10-4.l: Likewise.
+ * gas/i386/arch-10.s: Likewise.
+ * gas/i386/clmul-intel.d: Likewise.
+ * gas/i386/clmul.d: Likewise.
+ * gas/i386/clmul.s: Likewise.
+ * gas/i386/x86-64-arch-2.s: Likewise.
+ * gas/i386/x86-64-clmul-intel.d: Likewise.
+ * gas/i386/x86-64-clmul.d: Likewise.
+ * gas/i386/x86-64-clmul.s: Likewise.
+
+ * gas/i386/arch-10.d: Replace clmul with pclmul.
+ * gas/i386/x86-64-arch-2.d: Likewise.
+
+2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
+ x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
+ x86-64-avx-intel and x86-64-inval-avx.
+
+ * gas/cfi/cfi-i386.s: Add tests for AVX register maps.
+ * gas/cfi/cfi-x86_64.s: Likewise.
+
+ * gas/i386/aes.d: New.
+ * gas/i386/aes.s: Likewise.
+ * gas/i386/aes-intel.d: Likewise.
+ * gas/i386/avx.d: Likewise.
+ * gas/i386/avx.s: Likewise.
+ * gas/i386/avx-intel.d: Likewise.
+ * gas/i386/clmul.d: Likewise.
+ * gas/i386/clmul-intel.d: Likewise.
+ * gas/i386/clmul.s: Likewise.
+ * gas/i386/i386.exp: Likewise.
+ * gas/i386/inval-avx.l: Likewise.
+ * gas/i386/inval-avx.s: Likewise.
+ * gas/i386/sse2avx.d: Likewise.
+ * gas/i386/sse2avx.s: Likewise.
+ * gas/i386/x86-64-aes.d: Likewise.
+ * gas/i386/x86-64-aes.s: Likewise.
+ * gas/i386/x86-64-aes-intel.d: Likewise.
+ * gas/i386/x86-64-avx.d: Likewise.
+ * gas/i386/x86-64-avx.s: Likewise.
+ * gas/i386/x86-64-avx-intel.d: Likewise.
+ * gas/i386/x86-64-clmul.d: Likewise.
+ * gas/i386/x86-64-clmul-intel.d: Likewise.
+ * gas/i386/x86-64-clmul.s: Likewise.
+ * gas/i386/x86-64-inval-avx.l: Likewise.
+ * gas/i386/x86-64-inval-avx.s: Likewise.
+ * gas/i386/x86-64-sse2avx.d: Likewise.
+ * gas/i386/x86-64-sse2avx.s: Likewise.
+
+ * gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
+ * gas/i386/x86-64-arch-2.s: Likewise.
+
+ * gas/i386/rexw.s: Add AVX tests.
+
+ * gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
+
+ * gas/cfi/cfi-i386.d: Updated.
+ * gas/cfi/cfi-x86_64.d: Likewise.
+ * gas/i386/arch-10.d: Likewise.
+ * gas/i386/arch-10-1.l: Likewise.
+ * gas/i386/arch-10-2.l: Likewise.
+ * gas/i386/arch-10-3.l: Likewise.
+ * gas/i386/arch-10-4.l: Likewise.
+ * gas/i386/rexw.d: Likewise.
+ * gas/i386/x86-64-arch-2.d: Likewise.
+ * gas/i386/x86-64-opcode-inval.d: Likewise.
+ * gas/i386/x86-64-opcode-inval-intel.d: Likewise.
+
+2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
+
+ From Jie Zhang <jie.zhang@analog.com>
+ * gas/bfin/load.d: Update.
+ * gas/bfin/expected_comparison_errors.l: New test.
+ * gas/bfin/expected_comparison_errors.s: New test.
+ * gas/bfin/bfin.exp: Add expected_comparison_errors.
+ * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add
+ tests for bad options of "multiply and multipy-accumulate to
+ accumulator" instructions. Add new vector instruction option
+ mode tests.
+ * gas/bfin/vector2.s: Add new vector instruction option mode test.
+ * gas/bfin/vector2.d: Adjust accordingly.
+ * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s:
+ Add check for mismatch of accumulator and data register.
+ * gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check
+ for IU option.
+
+ * gas/bfin/flow.d: Adjust since the generated labels for LOOP_BEGIN
+ and LOOP_END instruction are local now.
+ * gas/bfin/flow2.d: Likewise.
+
+ From Mike Frysinger <michael.frysinger@analog.com>
+ * gas/bfin/expected_errors.s, gas/bfin/expected_errors.l: Add test
+ for mismatched half registers in vector multipy-accumulate
+ instructions.
+
+ From Robin Getz <rgetz@blackfin.uclinux.org>
+ * gas/bfin/arithmetic.d: Update to reflect spaces/capitalization in
+ recent changes in opcodes/bfin-dis.c.
+ gas/bfin/arithmetic.s: Likewise.
+ gas/bfin/bit.d: Likewise.
+ gas/bfin/bit2.d: Likewise.
+ gas/bfin/control_code.d: Likewise.
+ gas/bfin/control_code2.d: Likewise.
+ gas/bfin/event.d: Likewise.
+ gas/bfin/event2.d: Likewise.
+ gas/bfin/flow.d: Likewise.
+ gas/bfin/flow2.d: Likewise.
+ gas/bfin/load.d: Likewise.
+ gas/bfin/logical.d: Likewise.
+ gas/bfin/logical2.d: Likewise.
+ gas/bfin/move.d: Likewise.
+ gas/bfin/move2.d: Likewise.
+ gas/bfin/parallel.d: Likewise.
+ gas/bfin/parallel2.d: Likewise.
+ gas/bfin/parallel3.d: Likewise.
+ gas/bfin/parallel4.d: Likewise.
+ gas/bfin/shift.d: Likewise.
+ gas/bfin/shift2.d: Likewise.
+ gas/bfin/stack.d: Likewise.
+ gas/bfin/stack2.d: Likewise.
+ gas/bfin/store.d: Likewise.
+ gas/bfin/vector.d: Likewise.
+ gas/bfin/vector2.d: Likewise.
+ gas/bfin/video.d: Likewise.
+ gas/bfin/video2.d: Likewise.
+
+2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * gas/s390/zarch-z10.d: New file.
+ * gas/s390/zarch-z10.s: New file.
+ * gas/s390/s390.exp: Run the z10 testcases.
+
+2008-03-17 Richard Sandiford <rsandifo@nildram.co.uk>
+
+ * gas/mips/elf-rel26.d: Add -32.
+ * gas/mips/mips16-intermix.d: Likewise.
+
+2008-03-13 Nick Clifton <nickc@redhat.com>
+
+ PR gas/5895
+ * gas/macros/exit.s: New test case.
+ * gas/macros/macros.exp: Run the new test, expect it to produce an
+ error result.
+
+2008-03-09 Paul Brook <paul@codesourcery.com>
+
+ * gas/arm/vfpv3-d16-bad.d: New test.
+ * gas/arm/vfpv3-d16-bad.l: New test.
+
+2008-03-06 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * gas/s390/esa-g5.d (cdfbr, cdfr, cefbr, cefr, cxfbr, cxfr,
+ dxr, fidr, fier, fixr, lzdr, lzer, lzxr, sqdr, sqer, tp): Fix
+ operand format.
+ * gas/s390/esa-g5.s: Likewise.
+ * gas/s390/zarch-z900.d (cdgbr, cdgr, cegbr, cegr, cxgbr,
+ cxgr): Likewise.
+ * gas/s390/zarch-z900.s: Likewise.
+ * gas/s390/zarch-z9-109.d (cu41, cu42): Remove mask operand.
+ * gas/s390/zarch-z9-109.s: Likewise.
+
+2008-03-04 Paul Brook <paul@codesourcery.com>
+
+ * gas/arm/archv6m.d: New test.
+ * gas/arm/archv6m.s: New test.
+ * gas/arm/t16-bad.s: Test low register non flag setting add.
+ * gas/arm/t16-bad.l: Update expected output.
+
+2008-03-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/5543
+ * gas/i386/i386.exp: Run inval-equ-1 and inval-equ-2.
+
+ * gas/i386/inval-equ-1.l: New.
+ * gas/i386/inval-equ-1.s: Likewise.
+ * gas/i386/inval-equ-2.l: Likewise.
+ * gas/i386/inval-equ-2.s: Likewise.
+
+2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/x86-64-branch.s: Add tests for 16-bit near indirect
+ branches.
+
+ * gas/i386/x86-64-inval.s: Remove tests for 16-bit near indirect
+ branches.
+
+ * gas/i386/x86-64-branch.d: Updated.
+ * gas/i386/x86-64-inval.l: Likewise.
+
+2008-02-27 Nick Clifton <nickc@redhat.com>
+
+ PR 3134
+ * gas/h8300/pr3134.s: New test.
+ * gas/h8300/pr3134.d: Expected disassembly
+ * gas/h8300/h8300.exp: Run the new test.
+
+ * gas/h8300/h8300-coff.exp: Fix test for COFF based ports to
+ accept h8300-rtemscoff not just h8300-rtems.
+
+2008-02-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/jump.d: Updated for COFF.
+
+2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/jump.s: Add tests for far branches.
+ * gas/i386/jump16.s: Likewise.
+
+ * gas/i386/jump.d: Updated.
+ * gas/i386/jump16.d: Likewise.
+ * gas/i386/x86-64-inval.l: Likewise.
+
+ * gas/i386/x86-64-inval.s: Add tests for 16-bit near indirect
+ branches.
+
+2008-02-22 Nick Clifton <nickc@redhat.com>
+
+ * gas/m68hc11/bug-1825.d: Update to match changes in the
+ information generated with source-in-disassembly listings.
+ * gas/m68hc11/indexed12.d: Likewise.
+ * gas/m68hc11/insns-dwarf2.d: Likewise.
+ * gas/m68hc11/lbranch-dwarf2.d: Likewise.
+
+2008-02-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * cfi/cfi.exp (gas_x86_64_check): New.
+ (gas_x86_32_check): Likewise.
+ Run 32bit and 64bit tests for x86 targets if they are supportd.
+
+2008-02-18 Jan Beulich <jbeulich@novell.com>
+
+ * gas/i386/att-regs.s, gas/i386/att-regs.d,
+ gas/i386/intel-regs.s, gas/i386/intel-regs.d: New.
+ * gas/i386/i386.exp: Run new tests.
+
+2008-02-14 Nick Clifton <nickc@redhat.com>
+
+ PR gas/5712
+ * gas/arm/fp-save.s: New test.
+ * gas/arm/fp-save.d: Expected disassembly.
+
+2008-02-13 Adam Nemet <anemet@caviumnetworks.com>
+
+ * gas/mips/branch-misc-2pic-64.d (#name): Have a unique name
+ different from the branch-misc-2-64.d test.
+
+2008-02-13 Jan Beulich <jbeulich@novell.com>
+
+ * gas/i386/intelok.s: Replace invalid offset expression with
+ valid ones.
+ * gas/i386/x86_64.s: Likewise.
+
+2008-02-13 Jan Beulich <jbeulich@novell.com>
+
+ * gas/i386/intelbad.s, gas/i386/intelok.s: Add 'bound' tests.
+ * gas/i386/intelbad.l, gas/i386/intelok.l, gas/i386/intelok.e,
+ gas/i386/opcode-intel.d: Adjust.
+
+2008-02-13 Jan Beulich <jbeulich@novell.com>
+
+ * gas/cfi/cfi-i386.s: Add code testing use of all registers.
+ Fix a few comments.
+ * gas/cfi/cfi-x86_64.s: Likewise.
+ * gas/cfi/cfi-i386.d, gas/cfi/cfi-x86_64.d: Adjust.
+
+2008-02-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp: Run x86-64-arch-2 instead of
+ x86-64-arch-10.
+
+ * gas/i386/x86-64-arch-10.d: Removed.
+
+ * gas/i386/x86-64-arch-2.d: New.
+ * gas/i386/x86-64-arch-2.s: Likewise.
+
+2008-02-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/x86-64-xsave.d: Remove prefix.
+
+2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/arch-10.s: Add xgetbv.
+
+ * gas/i386/arch-10.d: Updated.
+ * gas/i386/arch-10-1.l: Likewise.
+ * gas/i386/arch-10-2.l: Likewise.
+ * gas/i386/arch-10-3.l: Likewise.
+ * gas/i386/arch-10-4.l: Likewise.
+ * gas/i386/x86-64-arch-10.d: Likewise.
+
+2002-02-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp: Run xsave, xsave-intel, x86-64-xsave
+ and x86-64-xsave-intel.
+
+ * gas/i386/x86-64-xsave-intel.d: New file.
+ * gas/i386/x86-64-xsave.d: Likewise.
+ * gas/i386/x86-64-xsave.s: Likewise.
+ * gas/i386/xsave-intel.d: Likewise.
+ * gas/i386/xsave.d: Likewise.
+ * gas/i386/xsave.s: Likewise.
+
+2008-02-05 Adam Nemet <anemet@caviumnetworks.com>
+
+ * gas/mips/mips.exp: Invoke the tests smartmips, mips32-dsp,
+ mips32-dspr2, mips64-dsp and mips32-mt with run_dump_test instead
+ of run_dump_test_arches.
+ * gas/mips/smartmips.d: Pass -mips32.
+ * gas/mips/mips64-dsp.d: Pass -mips64r2.
+ * gas/mips/mips32-dsp.d: Pass -mips32r2.
+ * gas/mips/mips32-dspr2.d: Likewise.
+ * gas/mips/mips32-mt.d: Likewise.
+
+2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
+
+ * gas/mips/mips.exp: Call mips_arch_create for Octeon. Invoke
+ Octeon tests.
+ * gas/mips/octeon.s, gas/mips/octeon.d: New test.
+
+2008-01-31 Marc Gauthier <marc@tensilica.com>
+
+ * gas/all/gas.exp: Recognize Xtensa processor variants.
+ * gas/elf/elf.exp: Likewise.
+ * gas/lns/lns.exp: Likewise.
+
+2008-01-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/cfi/cfi-alpha-1.d: Replace DW_CFA_def_cfa_reg with
+ DW_CFA_def_cfa_register.
+ * gas/cfi/cfi-alpha-3.d: Likewise.
+ * gas/cfi/cfi-hppa-1.d: Likewise.
+ * gas/cfi/cfi-i386.d: Likewise.
+ * gas/cfi/cfi-m68k.d: Likewise.
+ * gas/cfi/cfi-mips-1.d: Likewise.
+ * gas/cfi/cfi-sh-1.d: Likewise.
+ * gas/cfi/cfi-sparc-1.d: Likewise.
+ * gas/cfi/cfi-sparc64-1.d: Likewise.
+ * gas/cfi/cfi-x86_64.d: Likewise.
+
+ * gas/cfi/cfi-common-1.d: Updated for i386/x86-64 register
+ names.
+ * gas/cfi/cfi-common-2.d: Likewise.
+ * gas/cfi/cfi-common-5.d: Likewise.
+ * gas/cfi/cfi-i386.d: Likewise.
+ * gas/cfi/cfi-x86_64.d: Likewise.
+
+2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/x86-64-sib.s: Add tests for r12.
+
+ * gas/i386/x86-64-sib-intel.d: Updated.
+ * gas/i386/x86-64-sib.d: Likewise.
+
+2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp : Run x86-64-arch-1 and x86-64-arch-10.
+
+ * gas/i386/x86-64-arch-1.d: New.
+ * gas/i386/x86-64-arch-1.s: Likewise.
+ * gas/i386/x86-64-arch-10.d: Likewise.
+
+2008-01-23 Tristan Gingold <gingold@adacore.com>
+
+ * gas/ia64/regs.d: Updated as the ia64 disassembler now displays
+ symbolic names for all ar registers.
+
+2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/arch-10.d: New.
+ * gas/i386/arch-11.s: Likewise.
+ * gas/i386/arch-12.d: Likewise.
+ * gas/i386/arch-12.s: Likewise.
+
+ * gas/i386/i386.exp: Run arch-11 and arch-12.
+
+2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/arch-10-1.l: New.
+ * gas/i386/arch-10-1.s: Likewise.
+ * gas/i386/arch-10-2.l: Likewise.
+ * gas/i386/arch-10-2.s: Likewise.
+ * gas/i386/arch-10-3.l: Likewise.
+ * gas/i386/arch-10-3.s: Likewise.
+ * gas/i386/arch-10-4.l: Likewise.
+ * gas/i386/arch-10-4.s: Likewise.
+ * gas/i386/arch-10.d: Likewise.
+ * gas/i386/arch-10.s: Likewise.
+
+ * gas/i386/i386.exp: Run arch-10, arch-10-1, arch-10-2,
+ arch-10-3 and arch-10-4.
+
+ * gas/i386/nops-2.s: Use movsbl instead of cmove.
+ * gas/i386/nops-2-i386.d: Updated.
+ * gas/i386/nops-2-merom.d: Likewise.
+ * gas/i386/nops-2.d: Likewise.
+ * gas/i386/x86-64-nops-2.d: Likewise.
+
+2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/prescott.s: Add tests for movddup in Intel syntax.
+ * gas/i386/x86-64-prescott.s: Likewise.
+
+ * gas/i386/prescott.d: Updated.
+ * gas/i386/x86-64-prescott.d: Likewise.
+
+2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.s: Add more tests for movsx and movzx.
+ * gas/i386/x86_64.s: Likewise.
+
+ * gas/i386/inval.s: Remove tests for movsxw and movzxw.
+
+ * gas/i386/x86-64-inval.s: Remove tests for movsxb, movsxw,
+ movsxl, movzxb and movzxw.
+
+ * gas/i386/i386.d: Updated.
+ * gas/i386/inval.l: Likewise.
+ * gas/i386/x86_64.d: Likewise.
+ * gas/i386/x86-64-inval.l: Likewise.
+
+2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.s: Add tests for movsx, movzx and movnti.
+ * gas/i386/inval.s: Likewise.
+ * gas/i386/x86_64.s: Likewise.
+ * gas/i386/x86-64-inval.s: Likewise.
+
+ * gas/i386/i386.d: Updated.
+ * gas/i386/inval.l: Likewise.
+ * gas/i386/x86_64.d: Likewise.
+ * gas/i386/x86-64-inval.l: Likewise.
+
+2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/5534
+ * gas/i386/i386.s: Add tests for fnstsw and fstsw.
+ * gas/i386/inval.s: Likewise.
+ * gas/i386/x86_64.s: Likewise.
+
+ * gas/i386/intel.s: Use word instead of dword on ss.
+
+ * gas/i386/x86-64-inval.s: Add tests for fnstsw, fstsw, in
+ and out.
+
+ * gas/i386/prefix.s: Remove invalid fstsw.
+
+ * gas/i386/inval.l: Updated.
+ * gas/i386/intelbad.l: Likewise.
+ * gas/i386/i386.d: Likewise.
+ * gas/i386/x86_64.d: Likewise.
+ * gas/i386/x86-64-inval.l: Likewise.
+ * gas/i386/prefix.d: Updated.
+
+2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/nops.s: Add more tests with opcodes from 0x0f19
+ to 0x0f1f.
+ * gas/i386/x86-64-nops.s: Likewise.
+
+ * gas/i386/nops.d: Updated.
+ * gas/i386/x86-64-nops.d: Likewise.
+
+2008-01-09 Bob Wilson <bob.wilson@acm.org>
+
+ * gas/lns/lns.exp: Run new lns-big-delta test for targets that set
+ DWARF2_USE_FIXED_ADVANCE_PC.
+ * gas/lns/lns-big-delta.s: New.
+ * gas/lns/lns-big-delta.d: New.
+
+2008-01-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ PR gas/5322
+ * lib/gas-defs.exp (gas_host_run): Add fourth argument to regsub
+ command.
+
+2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/intel.s: Add tests for fadd, faddp, fdiv, fdivp,
+ fdivr, fdivrp, fmul, fmulp, fsub, fsubp, fsubr and fsubrp.
+
+ * gas/i386/intel.d: Updated.
+ * gas/i386/intel.e: Likewise.
+
+2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/rexw.d: New.
+ * gas/i386/rexw.s: Likewise.
+
+ * gas/i386/x86-64-sse4_1-intel.d: Updated.
+ * gas/i386/x86-64-sse4_1.d: Likewise.
+
+2008-01-04 Nick Clifton <nickc@redhat.com>
+
+ * gas/ppc/altivec_and_spe.s: New test - checks that ISA extension
+ command line options (-maltivec, -mspe) can be specified before
+ CPU selection command line options.
+ * gas/ppc/altivec_and_spe.d: Expected disassembly.
+ * gas/ppc/ppc.exp: Run the new test
+
+2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/arch-9.d: New file.
+ * gas/i386/arch-9.s: Likewise.
+
+ * gas/i386/i386.exp: Run arch-9.
+
+2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/arch-5.d: New file.
+ * gas/i386/arch-5.s: Likewise.
+ * gas/i386/arch-6.d: Likewise.
+ * gas/i386/arch-6.s: Likewise.
+ * gas/i386/arch-7.d: Likewise.
+ * gas/i386/arch-7.s: Likewise.
+ * gas/i386/arch-8.d: Likewise.
+ * gas/i386/arch-8.s: Likewise.
+
+ * gas/i386/i386.exp: Run arch-5, arch-6, arch-7 and arch-8.
+
+2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.s: Add tests for movq.
+ * gas/i386/x86_64.s: Likewise.
+
+ * gas/i386/i386.d Updated.
+ * gas/i386/x86_64.d: Likewise.
+
+2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/5534
+ * gas/i386/intel.s: Use QWORD on movq instead of DWORD.
+
+ * gas/i386/inval.s: Add tests for movq.
+ * gas/i386/x86-64-inval.s: Likewise.
+
+ * gas/i386/inval.l: Updated.
+ * gas/i386/x86-64-inval.l: Likewise.
+
+2008-01-02 Catherine Moore <clm@codesourcery.com>
+
+ * gas/mips/jalr.s: New test.
+ * gas/mips/jalr.l: New test output.
+ * gas/mips/mips.exp: Run new test.
+
+For older changes see ChangeLog-2007
+\f
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
[ ]*31[ ]+\# AES \+ AVX
[ ]*32[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
[ ]*33[ ]+\# FMA
-[ ]*34[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
+[ ]*34[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
[ ]*35[ ]+\# MOVBE
[ ]*36[ ]+movbe \(%ecx\),%ebx
[ ]*37[ ]+\# EPT
[ ]*31[ ]+\# AES \+ AVX
[ ]*32[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
[ ]*33[ ]+\# FMA
-[ ]*34[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
+[ ]*34[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
[ ]*35[ ]+\# MOVBE
[ ]*36[ ]+movbe \(%ecx\),%ebx
[ ]*37[ ]+\# EPT
[ ]*31[ ]+\# AES \+ AVX
[ ]*32[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
[ ]*33[ ]+\# FMA
-[ ]*34[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
+[ ]*34[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
[ ]*35[ ]+\# MOVBE
[ ]*36[ ]+movbe \(%ecx\),%ebx
[ ]*37[ ]+\# EPT
[ ]*31[ ]+\# AES \+ AVX
[ ]*32[ ]+vaesenc \(%ecx\),%xmm0,%xmm2
[ ]*33[ ]+\# FMA
-[ ]*34[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
+[ ]*34[ ]+vfmadd132pd %xmm4,%xmm6,%xmm2
[ ]*35[ ]+\# MOVBE
[ ]*36[ ]+movbe \(%ecx\),%ebx
[ ]*37[ ]+\# EPT
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%ecx\),%xmm0
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
[ ]*[a-f0-9]+: c4 e2 79 dc 11 vaesenc \(%ecx\),%xmm0,%xmm2
-[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
+[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%ecx\),%ebx
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%ecx\),%ebx
[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
# AES + AVX
vaesenc (%ecx),%xmm0,%xmm2
# FMA
-vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
+vfmadd132pd %xmm4,%xmm6,%xmm2
# MOVBE
movbe (%ecx),%ebx
# EPT
[ ]*[a-f0-9]+: c4 e2 4d 2f 21 vmaskmovpd YMMWORD PTR \[ecx\],ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps ymm6,ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps YMMWORD PTR \[ecx\],ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps ymm6,YMMWORD PTR \[ecx\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 05 d6 07 vpermilpd ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 05 31 07 vpermilpd ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 04 d6 07 vpermilps ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 04 31 07 vpermilps ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 09 d6 07 vroundpd ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 09 31 07 vroundpd ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 08 d6 07 vroundps ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 08 31 07 vroundps ymm6,YMMWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc 58 d4 vaddps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2ps xmm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq xmm4,ymm4
[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dq xmm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 5b f4 vcvtdq2ps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 5b f4 vcvtps2dq ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 5b f4 vcvttps2dq ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup ymm4,ymm4
+[ ]*[a-f0-9]+: c5 ff 12 f4 vmovddup ymm6,ymm4
[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 16 f4 vmovshdup ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 12 f4 vmovsldup ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 10 21 vmovups ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest ymm4,ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 17 f4 vptest ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 53 f4 vrcpps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 52 f4 vrsqrtps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 51 f4 vsqrtpd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 51 f4 vsqrtps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd ymm4,ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0f f4 vtestpd ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps ymm4,ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0e f4 vtestps ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu ymm4,\[ecx\]
-[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
+[ ]*[a-f0-9]+: c4 e3 4d 0d d4 07 vblendpd ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0d 11 07 vblendpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0c d4 07 vblendps ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0c 11 07 vblendps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e3 4d 40 d4 07 vdpps ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 40 11 07 vdpps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 06 d4 07 vperm2f128 ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 06 11 07 vperm2f128 ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 cd c6 d4 07 vshufpd ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps ymm7,ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 69 39 20 vfmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 68 fc 20 vfmaddps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 68 39 20 vfmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5d fc 20 vfmaddsubpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5d 39 20 vfmaddsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5c fc 20 vfmaddsubps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5c 39 20 vfmaddsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5f fc 20 vfmsubaddpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5f 39 20 vfmsubaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5e fc 20 vfmsubaddps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5e 39 20 vfmsubaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 6d fc 20 vfmsubpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 6d 39 20 vfmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 6c fc 20 vfmsubps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 6c 39 20 vfmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 79 fc 20 vfnmaddpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 79 39 20 vfnmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 78 fc 20 vfnmaddps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 78 39 20 vfnmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 7d fc 20 vfnmsubpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 7d 39 20 vfnmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 7c fc 20 vfnmsubps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 7c 39 20 vfnmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd ymm7,ymm2,ymm6,ymm4,0xa
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\],0xa
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps ymm7,ymm2,ymm6,ymm4,0xa
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\],0xa
-[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 ymm6,ymm4,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 ymm6,ymm4,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 xmm4,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 XMMWORD PTR \[ecx\],ymm4,0x64
+[ ]*[a-f0-9]+: c4 e3 5d 18 f4 07 vinsertf128 ymm6,ymm4,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 5d 18 31 07 vinsertf128 ymm6,ymm4,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 e4 07 vextractf128 xmm4,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 21 07 vextractf128 XMMWORD PTR \[ecx\],ymm4,0x7
[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 ymm4,XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps xmm6,xmm4
[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps xmm4,XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 79 df f4 64 vaeskeygenassist xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 df 31 64 vaeskeygenassist xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps xmm6,XMMWORD PTR \[ecx\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 df 31 07 vaeskeygenassist xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 61 f4 07 vpcmpestri xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 61 31 07 vpcmpestri xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 60 f4 07 vpcmpestrm xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 60 31 07 vpcmpestrm xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 63 f4 07 vpcmpistri xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 63 31 07 vpcmpistri xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 62 f4 07 vpcmpistrm xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 62 31 07 vpcmpistrm xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 05 f4 07 vpermilpd xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 05 31 07 vpermilpd xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 04 f4 07 vpermilps xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 04 31 07 vpermilps xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 f9 70 f4 07 vpshufd xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 f9 70 31 07 vpshufd xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 fa 70 f4 07 vpshufhw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 fa 70 31 07 vpshufhw xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 fb 70 f4 07 vpshuflw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 fb 70 31 07 vpshuflw xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 09 f4 07 vroundpd xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 09 31 07 vroundpd xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 08 f4 07 vroundps xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 08 31 07 vroundps xmm6,XMMWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps XMMWORD PTR \[ecx\],xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd XMMWORD PTR \[ecx\],xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
+[ ]*[a-f0-9]+: c4 e3 49 0d d4 07 vblendpd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0d 11 07 vblendpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0c d4 07 vblendps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0c 11 07 vblendps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 c9 c2 11 07 vcmpordpd xmm2,xmm6,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 c8 c2 11 07 vcmpordps xmm2,xmm6,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e3 49 41 d4 07 vdppd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 41 11 07 vdppd xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 40 d4 07 vdpps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 40 11 07 vdpps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 42 d4 07 vmpsadbw xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 42 11 07 vmpsadbw xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0f d4 07 vpalignr xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0f 11 07 vpalignr xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0e d4 07 vpblendw xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0e 11 07 vpblendw xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 c9 c6 d4 07 vshufpd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps xmm7,xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c4 e3 69 4a 39 40 vblendvps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb xmm7,xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 69 fc 20 vfmaddpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 69 39 20 vfmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 69 39 20 vfmaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 68 fc 20 vfmaddps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 68 39 20 vfmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 68 39 20 vfmaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5d fc 20 vfmaddsubpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5d 39 20 vfmaddsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 5d 39 20 vfmaddsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5c fc 20 vfmaddsubps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5c 39 20 vfmaddsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 5c 39 20 vfmaddsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5f fc 20 vfmsubaddpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5f 39 20 vfmsubaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 5f 39 20 vfmsubaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5e fc 20 vfmsubaddps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5e 39 20 vfmsubaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 5e 39 20 vfmsubaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6d fc 20 vfmsubpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6d 39 20 vfmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6d 39 20 vfmsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6c fc 20 vfmsubps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6c 39 20 vfmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6c 39 20 vfmsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 79 fc 20 vfnmaddpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 79 39 20 vfnmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 79 39 20 vfnmaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 78 fc 20 vfnmaddps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 78 39 20 vfnmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 78 39 20 vfnmaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7d fc 20 vfnmsubpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7d 39 20 vfnmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7d 39 20 vfnmsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7c fc 20 vfnmsubps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7c 39 20 vfnmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7c 39 20 vfnmsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd xmm7,xmm2,xmm6,xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\],0xa
-[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps xmm7,xmm2,xmm6,xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\],0xa
-[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4,0xa
[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd ymm4,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd xmm6,xmm4
[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd xmm4,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 d8 12 31 vmovlps xmm6,xmm4,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd xmm6,xmm4,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps xmm6,xmm4,QWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd xmm2,xmm6,QWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd xmm2,xmm6,QWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 c9 6b fc 20 vfmaddsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6b 39 20 vfmaddsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6b 39 20 vfmaddsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6f fc 20 vfmsubsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6f 39 20 vfmsubsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6f 39 20 vfmsubsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7b fc 20 vfnmaddsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7b 39 20 vfnmaddsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7b 39 20 vfnmaddsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7f fc 20 vfnmsubsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7f 39 20 vfnmsubsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7f 39 20 vfnmsubsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4
+[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e3 49 0b d4 07 vroundsd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0b 11 07 vroundsd xmm2,xmm6,QWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb 5a d4 vcvtsd2ss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 1e vcmpgt_oqsd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca 58 11 vaddss xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca 5a d4 vcvtss2sd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 fa 2d 09 vcvtss2si ecx,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si ecx,xmm4
[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si ecx,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd DWORD PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[ecx\],xmm4,0x64
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps DWORD PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 16 e1 07 vpextrd ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 16 21 07 vpextrd DWORD PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 17 e1 07 vextractps ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps DWORD PTR \[ecx\],xmm4,0x7
[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd xmm6,xmm4,ecx
[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sd xmm6,xmm4,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss xmm6,xmm4,ecx
[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ss xmm6,xmm4,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss xmm2,xmm6,DWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps xmm2,xmm6,DWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss xmm2,xmm6,DWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 c9 6a fc 20 vfmaddss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6a 39 20 vfmaddss xmm7,xmm2,xmm6,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6a 39 20 vfmaddss xmm7,xmm2,DWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6e fc 20 vfmsubss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6e 39 20 vfmsubss xmm7,xmm2,xmm6,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6e 39 20 vfmsubss xmm7,xmm2,DWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7a fc 20 vfnmaddss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7a 39 20 vfnmaddss xmm7,xmm2,xmm6,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7a 39 20 vfnmaddss xmm7,xmm2,DWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7e fc 20 vfnmsubss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7e 39 20 vfnmsubss xmm7,xmm2,xmm6,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7e 39 20 vfnmsubss xmm7,xmm2,DWORD PTR \[ecx\],xmm4
+[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e3 49 21 d4 07 vinsertps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 21 11 07 vinsertps xmm2,xmm6,DWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0a d4 07 vroundss xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0a 11 07 vroundss xmm2,xmm6,DWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq xmm4,WORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq xmm4,WORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw xmm6,xmm4,ecx,0x64
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x64
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw WORD PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw WORD PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c5 d9 c4 f1 07 vpinsrw xmm6,xmm4,ecx,0x7
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw xmm6,xmm4,WORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 e1 07 vpextrb ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb BYTE PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb xmm6,xmm4,ecx,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb BYTE PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb xmm6,xmm4,ecx,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu xmm6,xmm4
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd ecx,xmm4
[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64
+[ ]*[a-f0-9]+: c5 c9 72 f4 07 vpslld xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 fc 07 vpslldq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 f4 07 vpsllq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 71 f4 07 vpsllw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 72 e4 07 vpsrad xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 71 e4 07 vpsraw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 72 d4 07 vpsrld xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 dc 07 vpsrldq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 d4 07 vpsrlq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 71 d4 07 vpsrlw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw ecx,xmm4,0x7
[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd ecx,ymm4
[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps ecx,ymm4
[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq xmm6,xmm4
[ ]*[a-f0-9]+: c5 fe e6 05 34 12 00 00 vcvtdq2pd ymm0,XMMWORD PTR ds:0x1234
[ ]*[a-f0-9]+: c5 fd 5a 05 34 12 00 00 vcvtpd2ps xmm0,YMMWORD PTR ds:0x1234
[ ]*[a-f0-9]+: c5 f9 e0 3d 34 12 00 00 vpavgb xmm7,xmm0,XMMWORD PTR ds:0x1234
-[ ]*[a-f0-9]+: c4 e3 79 df 05 34 12 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR ds:0x1234,0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 05 34 12 00 00 64 vpextrb BYTE PTR ds:0x1234,xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 05 34 12 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR ds:0x1234,0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 05 34 12 00 00 07 vpextrb BYTE PTR ds:0x1234,xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a 3d 34 12 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR ds:0x1234
[ ]*[a-f0-9]+: c4 e3 59 4a 35 34 12 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR ds:0x1234,xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 3d 34 12 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR ds:0x1234,0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 3d 34 12 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR ds:0x1234,0x7
[ ]*[a-f0-9]+: c5 fd 6f 05 34 12 00 00 vmovdqa ymm0,YMMWORD PTR ds:0x1234
[ ]*[a-f0-9]+: c5 fd 7f 05 34 12 00 00 vmovdqa YMMWORD PTR ds:0x1234,ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d 3d 34 12 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR ds:0x1234
-[ ]*[a-f0-9]+: c4 e3 7d 09 05 34 12 00 00 64 vroundpd ymm0,YMMWORD PTR ds:0x1234,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 05 34 12 00 00 64 vextractf128 XMMWORD PTR ds:0x1234,ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 3d 34 12 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR ds:0x1234,0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 05 34 12 00 00 07 vroundpd ymm0,YMMWORD PTR ds:0x1234,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 05 34 12 00 00 07 vextractf128 XMMWORD PTR ds:0x1234,ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 3d 34 12 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR ds:0x1234,0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b 35 34 12 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR ds:0x1234,ymm0
[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr DWORD PTR \[ebp\+0x0\]
[ ]*[a-f0-9]+: c5 f9 6f 45 00 vmovdqa xmm0,XMMWORD PTR \[ebp\+0x0\]
[ ]*[a-f0-9]+: c5 fe e6 45 00 vcvtdq2pd ymm0,XMMWORD PTR \[ebp\+0x0\]
[ ]*[a-f0-9]+: c5 fd 5a 45 00 vcvtpd2ps xmm0,YMMWORD PTR \[ebp\+0x0\]
[ ]*[a-f0-9]+: c5 f9 e0 7d 00 vpavgb xmm7,xmm0,XMMWORD PTR \[ebp\+0x0\]
-[ ]*[a-f0-9]+: c4 e3 79 df 45 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[ebp\+0x0\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 45 00 64 vpextrb BYTE PTR \[ebp\+0x0\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 45 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[ebp\+0x0\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 45 00 07 vpextrb BYTE PTR \[ebp\+0x0\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a 7d 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+0x0\]
[ ]*[a-f0-9]+: c4 e3 59 4a 75 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[ebp\+0x0\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 7d 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+0x0\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 7d 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+0x0\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 45 00 vmovdqa ymm0,YMMWORD PTR \[ebp\+0x0\]
[ ]*[a-f0-9]+: c5 fd 7f 45 00 vmovdqa YMMWORD PTR \[ebp\+0x0\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d 7d 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[ebp\+0x0\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 45 00 64 vroundpd ymm0,YMMWORD PTR \[ebp\+0x0\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 45 00 64 vextractf128 XMMWORD PTR \[ebp\+0x0\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 7d 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+0x0\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 45 00 07 vroundpd ymm0,YMMWORD PTR \[ebp\+0x0\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 45 00 07 vextractf128 XMMWORD PTR \[ebp\+0x0\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 7d 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+0x0\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b 75 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[ebp\+0x0\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 14 24 vldmxcsr DWORD PTR \[esp\]
[ ]*[a-f0-9]+: c5 f9 6f 04 24 vmovdqa xmm0,XMMWORD PTR \[esp\]
[ ]*[a-f0-9]+: c5 fe e6 04 24 vcvtdq2pd ymm0,XMMWORD PTR \[esp\]
[ ]*[a-f0-9]+: c5 fd 5a 04 24 vcvtpd2ps xmm0,YMMWORD PTR \[esp\]
[ ]*[a-f0-9]+: c5 f9 e0 3c 24 vpavgb xmm7,xmm0,XMMWORD PTR \[esp\]
-[ ]*[a-f0-9]+: c4 e3 79 df 04 24 64 vaeskeygenassist xmm0,XMMWORD PTR \[esp\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 04 24 64 vpextrb BYTE PTR \[esp\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 04 24 07 vaeskeygenassist xmm0,XMMWORD PTR \[esp\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 04 24 07 vpextrb BYTE PTR \[esp\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a 3c 24 vcvtsi2sd xmm7,xmm0,DWORD PTR \[esp\]
[ ]*[a-f0-9]+: c4 e3 59 4a 34 24 00 vblendvps xmm6,xmm4,XMMWORD PTR \[esp\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 3c 24 64 vpinsrb xmm7,xmm0,BYTE PTR \[esp\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 3c 24 07 vpinsrb xmm7,xmm0,BYTE PTR \[esp\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 04 24 vmovdqa ymm0,YMMWORD PTR \[esp\]
[ ]*[a-f0-9]+: c5 fd 7f 04 24 vmovdqa YMMWORD PTR \[esp\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 24 vpermilpd ymm7,ymm0,YMMWORD PTR \[esp\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 04 24 64 vroundpd ymm0,YMMWORD PTR \[esp\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 04 24 64 vextractf128 XMMWORD PTR \[esp\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 3c 24 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[esp\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 04 24 07 vroundpd ymm0,YMMWORD PTR \[esp\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 04 24 07 vextractf128 XMMWORD PTR \[esp\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 3c 24 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[esp\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b 34 24 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[esp\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr DWORD PTR \[ebp\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 85 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[ebp\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 85 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[ebp\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 85 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[ebp\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 bd 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[ebp\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 85 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[ebp\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 85 99 00 00 00 64 vpextrb BYTE PTR \[ebp\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 85 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[ebp\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 85 99 00 00 00 07 vpextrb BYTE PTR \[ebp\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a bd 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a b5 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[ebp\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 bd 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 bd 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 85 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[ebp\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 85 99 00 00 00 vmovdqa YMMWORD PTR \[ebp\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d bd 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[ebp\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 85 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[ebp\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 85 99 00 00 00 64 vextractf128 XMMWORD PTR \[ebp\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 bd 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 85 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[ebp\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 85 99 00 00 00 07 vextractf128 XMMWORD PTR \[ebp\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 bd 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b b5 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[ebp\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 14 25 99 00 00 00 vldmxcsr DWORD PTR \[eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 04 25 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 04 25 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 04 25 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 3c 25 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eiz\*1\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 04 25 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[eiz\*1\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 04 25 99 00 00 00 64 vpextrb BYTE PTR \[eiz\*1\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 04 25 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[eiz\*1\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 04 25 99 00 00 00 07 vpextrb BYTE PTR \[eiz\*1\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a 3c 25 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a 34 25 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eiz\*1\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 3c 25 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eiz\*1\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 3c 25 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[eiz\*1\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 04 25 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 04 25 99 00 00 00 vmovdqa YMMWORD PTR \[eiz\*1\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 25 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eiz\*1\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 04 25 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eiz\*1\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 04 25 99 00 00 00 64 vextractf128 XMMWORD PTR \[eiz\*1\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 3c 25 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eiz\*1\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 04 25 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[eiz\*1\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 04 25 99 00 00 00 07 vextractf128 XMMWORD PTR \[eiz\*1\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 3c 25 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eiz\*1\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b 34 25 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eiz\*1\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 14 65 99 00 00 00 vldmxcsr DWORD PTR \[eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 04 65 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 04 65 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 04 65 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 3c 65 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eiz\*2\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 04 65 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[eiz\*2\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 04 65 99 00 00 00 64 vpextrb BYTE PTR \[eiz\*2\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 04 65 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[eiz\*2\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 04 65 99 00 00 00 07 vpextrb BYTE PTR \[eiz\*2\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a 3c 65 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a 34 65 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eiz\*2\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 3c 65 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eiz\*2\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 3c 65 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[eiz\*2\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 04 65 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 04 65 99 00 00 00 vmovdqa YMMWORD PTR \[eiz\*2\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 65 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eiz\*2\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 04 65 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eiz\*2\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 04 65 99 00 00 00 64 vextractf128 XMMWORD PTR \[eiz\*2\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 3c 65 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eiz\*2\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 04 65 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[eiz\*2\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 04 65 99 00 00 00 07 vextractf128 XMMWORD PTR \[eiz\*2\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 3c 65 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eiz\*2\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b 34 65 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eiz\*2\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 94 20 99 00 00 00 vldmxcsr DWORD PTR \[eax\+eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 84 20 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 84 20 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 84 20 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 bc 20 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 84 20 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 84 20 99 00 00 00 64 vpextrb BYTE PTR \[eax\+eiz\*1\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 84 20 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 84 20 99 00 00 00 07 vpextrb BYTE PTR \[eax\+eiz\*1\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a bc 20 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a b4 20 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eax\+eiz\*1\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 20 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+eiz\*1\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 20 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+eiz\*1\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 84 20 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 84 20 99 00 00 00 vmovdqa YMMWORD PTR \[eax\+eiz\*1\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 20 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 20 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 20 99 00 00 00 64 vextractf128 XMMWORD PTR \[eax\+eiz\*1\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 20 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 20 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 20 99 00 00 00 07 vextractf128 XMMWORD PTR \[eax\+eiz\*1\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 20 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 20 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eax\+eiz\*1\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 94 60 99 00 00 00 vldmxcsr DWORD PTR \[eax\+eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 84 60 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 84 60 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 84 60 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 bc 60 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 84 60 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 84 60 99 00 00 00 64 vpextrb BYTE PTR \[eax\+eiz\*2\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 84 60 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 84 60 99 00 00 00 07 vpextrb BYTE PTR \[eax\+eiz\*2\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a bc 60 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a b4 60 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eax\+eiz\*2\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 60 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+eiz\*2\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 60 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+eiz\*2\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 84 60 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 84 60 99 00 00 00 vmovdqa YMMWORD PTR \[eax\+eiz\*2\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 60 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 60 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 60 99 00 00 00 64 vextractf128 XMMWORD PTR \[eax\+eiz\*2\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 60 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 60 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 60 99 00 00 00 07 vextractf128 XMMWORD PTR \[eax\+eiz\*2\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 60 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 60 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eax\+eiz\*2\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 94 98 99 00 00 00 vldmxcsr DWORD PTR \[eax\+ebx\*4\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 84 98 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 84 98 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 84 98 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 bc 98 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 84 98 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 84 98 99 00 00 00 64 vpextrb BYTE PTR \[eax\+ebx\*4\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 84 98 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 84 98 99 00 00 00 07 vpextrb BYTE PTR \[eax\+ebx\*4\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a bc 98 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+ebx\*4\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a b4 98 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eax\+ebx\*4\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 98 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+ebx\*4\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 98 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+ebx\*4\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 84 98 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 84 98 99 00 00 00 vmovdqa YMMWORD PTR \[eax\+ebx\*4\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 98 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 98 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 98 99 00 00 00 64 vextractf128 XMMWORD PTR \[eax\+ebx\*4\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 98 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 98 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 98 99 00 00 00 07 vextractf128 XMMWORD PTR \[eax\+ebx\*4\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 98 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 98 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eax\+ebx\*4\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 94 cc 99 00 00 00 vldmxcsr DWORD PTR \[esp\+ecx\*8\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 84 cc 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 84 cc 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 84 cc 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 bc cc 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 84 cc 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 84 cc 99 00 00 00 64 vpextrb BYTE PTR \[esp\+ecx\*8\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 84 cc 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 84 cc 99 00 00 00 07 vpextrb BYTE PTR \[esp\+ecx\*8\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a bc cc 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[esp\+ecx\*8\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a b4 cc 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[esp\+ecx\*8\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 bc cc 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[esp\+ecx\*8\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 bc cc 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[esp\+ecx\*8\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 84 cc 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 84 cc 99 00 00 00 vmovdqa YMMWORD PTR \[esp\+ecx\*8\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d bc cc 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 cc 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 cc 99 00 00 00 64 vextractf128 XMMWORD PTR \[esp\+ecx\*8\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc cc 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 cc 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 cc 99 00 00 00 07 vextractf128 XMMWORD PTR \[esp\+ecx\*8\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc cc 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 cc 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[esp\+ecx\*8\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 94 15 99 00 00 00 vldmxcsr DWORD PTR \[ebp\+edx\*1\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 84 15 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 84 15 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 84 15 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 bc 15 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 84 15 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 84 15 99 00 00 00 64 vpextrb BYTE PTR \[ebp\+edx\*1\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 84 15 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 84 15 99 00 00 00 07 vpextrb BYTE PTR \[ebp\+edx\*1\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a bc 15 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+edx\*1\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a b4 15 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[ebp\+edx\*1\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 15 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+edx\*1\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 15 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+edx\*1\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 84 15 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 84 15 99 00 00 00 vmovdqa YMMWORD PTR \[ebp\+edx\*1\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 15 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 15 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 15 99 00 00 00 64 vextractf128 XMMWORD PTR \[ebp\+edx\*1\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 15 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 15 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 15 99 00 00 00 07 vextractf128 XMMWORD PTR \[ebp\+edx\*1\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 15 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 15 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[ebp\+edx\*1\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f9 50 c0 vmovmskpd eax,xmm0
-[ ]*[a-f0-9]+: c5 c1 72 f0 64 vpslld xmm7,xmm0,0x64
+[ ]*[a-f0-9]+: c5 c1 72 f0 07 vpslld xmm7,xmm0,0x7
[ ]*[a-f0-9]+: c5 fc 50 c0 vmovmskps eax,ymm0
[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps YMMWORD PTR \[ecx\],ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps ymm6,ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps YMMWORD PTR \[ecx\],ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps ymm6,YMMWORD PTR \[ecx\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 05 d6 07 vpermilpd ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 05 31 07 vpermilpd ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 05 31 07 vpermilpd ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 04 d6 07 vpermilps ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 04 31 07 vpermilps ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 04 31 07 vpermilps ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 09 d6 07 vroundpd ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 09 31 07 vroundpd ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 09 31 07 vroundpd ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 08 d6 07 vroundps ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 08 31 07 vroundps ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 08 31 07 vroundps ymm6,YMMWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2ps xmm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq xmm4,ymm4
[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dq xmm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 5b f4 vcvtdq2ps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 5b f4 vcvtps2dq ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 5b f4 vcvttps2dq ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup ymm4,ymm4
+[ ]*[a-f0-9]+: c5 ff 12 f4 vmovddup ymm6,ymm4
[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 16 f4 vmovshdup ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 12 f4 vmovsldup ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 10 21 vmovups ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fc 10 21 vmovups ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest ymm4,ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 17 f4 vptest ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 53 f4 vrcpps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 52 f4 vrsqrtps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 51 f4 vsqrtpd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 51 f4 vsqrtps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd ymm4,ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0f f4 vtestpd ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd ymm4,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps ymm4,ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0e f4 vtestps ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps ymm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu ymm4,\[ecx\]
[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu ymm4,\[ecx\]
-[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps ymm2,ymm6,YMMWORD PTR \[ecx\],0x64
+[ ]*[a-f0-9]+: c4 e3 4d 0d d4 07 vblendpd ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0d 11 07 vblendpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0d 11 07 vblendpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0c d4 07 vblendps ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0c 11 07 vblendps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0c 11 07 vblendps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e3 4d 40 d4 07 vdpps ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 40 11 07 vdpps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 40 11 07 vdpps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 06 d4 07 vperm2f128 ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 06 11 07 vperm2f128 ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 06 11 07 vperm2f128 ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 cd c6 d4 07 vshufpd ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps ymm7,ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 69 39 20 vfmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 69 39 20 vfmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 68 fc 20 vfmaddps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 68 39 20 vfmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 68 39 20 vfmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5d fc 20 vfmaddsubpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5d 39 20 vfmaddsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5d 39 20 vfmaddsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5c fc 20 vfmaddsubps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5c 39 20 vfmaddsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5c 39 20 vfmaddsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5f fc 20 vfmsubaddpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5f 39 20 vfmsubaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5f 39 20 vfmsubaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5e fc 20 vfmsubaddps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5e 39 20 vfmsubaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5e 39 20 vfmsubaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 6d fc 20 vfmsubpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 6d 39 20 vfmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 6d 39 20 vfmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 6c fc 20 vfmsubps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 6c 39 20 vfmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 6c 39 20 vfmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 79 fc 20 vfnmaddpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 79 39 20 vfnmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 79 39 20 vfnmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 78 fc 20 vfnmaddps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 78 39 20 vfnmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 78 39 20 vfnmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 7d fc 20 vfnmsubpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 7d 39 20 vfnmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 7d 39 20 vfnmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 7c fc 20 vfnmsubps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 7c 39 20 vfnmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 cd 7c 39 20 vfnmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd ymm7,ymm2,ymm6,ymm4,0xa
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\],0xa
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\],0xa
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps ymm7,ymm2,ymm6,ymm4,0xa
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\],0xa
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps ymm7,ymm2,ymm6,YMMWORD PTR \[ecx\],0xa
-[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 ymm6,ymm4,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 ymm6,ymm4,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 ymm6,ymm4,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 xmm4,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 XMMWORD PTR \[ecx\],ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 XMMWORD PTR \[ecx\],ymm4,0x64
+[ ]*[a-f0-9]+: c4 e3 5d 18 f4 07 vinsertf128 ymm6,ymm4,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 5d 18 31 07 vinsertf128 ymm6,ymm4,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 5d 18 31 07 vinsertf128 ymm6,ymm4,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 e4 07 vextractf128 xmm4,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 21 07 vextractf128 XMMWORD PTR \[ecx\],ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 21 07 vextractf128 XMMWORD PTR \[ecx\],ymm4,0x7
[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 ymm4,XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 ymm4,XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 79 df f4 64 vaeskeygenassist xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 df 31 64 vaeskeygenassist xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 df 31 64 vaeskeygenassist xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps xmm6,XMMWORD PTR \[ecx\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 df 31 07 vaeskeygenassist xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 df 31 07 vaeskeygenassist xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 61 f4 07 vpcmpestri xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 61 31 07 vpcmpestri xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 61 31 07 vpcmpestri xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 60 f4 07 vpcmpestrm xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 60 31 07 vpcmpestrm xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 60 31 07 vpcmpestrm xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 63 f4 07 vpcmpistri xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 63 31 07 vpcmpistri xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 63 31 07 vpcmpistri xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 62 f4 07 vpcmpistrm xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 62 31 07 vpcmpistrm xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 62 31 07 vpcmpistrm xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 05 f4 07 vpermilpd xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 05 31 07 vpermilpd xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 05 31 07 vpermilpd xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 04 f4 07 vpermilps xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 04 31 07 vpermilps xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 04 31 07 vpermilps xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 f9 70 f4 07 vpshufd xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 f9 70 31 07 vpshufd xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 f9 70 31 07 vpshufd xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 fa 70 f4 07 vpshufhw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 fa 70 31 07 vpshufhw xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 fa 70 31 07 vpshufhw xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 fb 70 f4 07 vpshuflw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 fb 70 31 07 vpshuflw xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 fb 70 31 07 vpshuflw xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 09 f4 07 vroundpd xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 09 31 07 vroundpd xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 09 31 07 vroundpd xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 08 f4 07 vroundps xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 08 31 07 vroundps xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 08 31 07 vroundps xmm6,XMMWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps XMMWORD PTR \[ecx\],xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps XMMWORD PTR \[ecx\],xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd XMMWORD PTR \[ecx\],xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd XMMWORD PTR \[ecx\],xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps xmm2,xmm6,XMMWORD PTR \[ecx\],0x64
+[ ]*[a-f0-9]+: c4 e3 49 0d d4 07 vblendpd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0d 11 07 vblendpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0d 11 07 vblendpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0c d4 07 vblendps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0c 11 07 vblendps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0c 11 07 vblendps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 c9 c2 11 07 vcmpordpd xmm2,xmm6,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 c9 c2 11 07 vcmpordpd xmm2,xmm6,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 c8 c2 11 07 vcmpordps xmm2,xmm6,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 c8 c2 11 07 vcmpordps xmm2,xmm6,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e3 49 41 d4 07 vdppd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 41 11 07 vdppd xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 41 11 07 vdppd xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 40 d4 07 vdpps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 40 11 07 vdpps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 40 11 07 vdpps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 42 d4 07 vmpsadbw xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 42 11 07 vmpsadbw xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 42 11 07 vmpsadbw xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0f d4 07 vpalignr xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0f 11 07 vpalignr xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0f 11 07 vpalignr xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0e d4 07 vpblendw xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0e 11 07 vpblendw xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0e 11 07 vpblendw xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 c9 c6 d4 07 vshufpd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb xmm7,xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 69 fc 20 vfmaddpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 69 39 20 vfmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 69 39 20 vfmaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 69 39 20 vfmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 69 39 20 vfmaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 68 fc 20 vfmaddps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 68 39 20 vfmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 68 39 20 vfmaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 68 39 20 vfmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 68 39 20 vfmaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5d fc 20 vfmaddsubpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5d 39 20 vfmaddsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 5d 39 20 vfmaddsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5d 39 20 vfmaddsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 5d 39 20 vfmaddsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5c fc 20 vfmaddsubps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5c 39 20 vfmaddsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 5c 39 20 vfmaddsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5c 39 20 vfmaddsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 5c 39 20 vfmaddsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5f fc 20 vfmsubaddpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5f 39 20 vfmsubaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 5f 39 20 vfmsubaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5f 39 20 vfmsubaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 5f 39 20 vfmsubaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5e fc 20 vfmsubaddps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5e 39 20 vfmsubaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 5e 39 20 vfmsubaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5e 39 20 vfmsubaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 5e 39 20 vfmsubaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6d fc 20 vfmsubpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6d 39 20 vfmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6d 39 20 vfmsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6d 39 20 vfmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6d 39 20 vfmsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6c fc 20 vfmsubps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6c 39 20 vfmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6c 39 20 vfmsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6c 39 20 vfmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6c 39 20 vfmsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 79 fc 20 vfnmaddpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 79 39 20 vfnmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 79 39 20 vfnmaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 79 39 20 vfnmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 79 39 20 vfnmaddpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 78 fc 20 vfnmaddps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 78 39 20 vfnmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 78 39 20 vfnmaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 78 39 20 vfnmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 78 39 20 vfnmaddps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7d fc 20 vfnmsubpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7d 39 20 vfnmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7d 39 20 vfnmsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7d 39 20 vfnmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7d 39 20 vfnmsubpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7c fc 20 vfnmsubps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7c 39 20 vfnmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7c 39 20 vfnmsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7c 39 20 vfnmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7c 39 20 vfnmsubps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd xmm7,xmm2,xmm6,xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\],0xa
-[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\],0xa
-[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps xmm7,xmm2,xmm6,xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\],0xa
-[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps xmm7,xmm2,xmm6,XMMWORD PTR \[ecx\],0xa
-[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4,0xa
[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd ymm4,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd ymm4,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd xmm6,xmm4
[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd xmm6,xmm4,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps xmm6,xmm4,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps xmm6,xmm4,QWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd xmm2,xmm6,QWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd xmm2,xmm6,QWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd xmm2,xmm6,QWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd xmm2,xmm6,QWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 c9 6b fc 20 vfmaddsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6b 39 20 vfmaddsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6b 39 20 vfmaddsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6b 39 20 vfmaddsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6b 39 20 vfmaddsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6f fc 20 vfmsubsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6f 39 20 vfmsubsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6f 39 20 vfmsubsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6f 39 20 vfmsubsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6f 39 20 vfmsubsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7b fc 20 vfnmaddsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7b 39 20 vfnmaddsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7b 39 20 vfnmaddsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7b 39 20 vfnmaddsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7b 39 20 vfnmaddsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7f fc 20 vfnmsubsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7f 39 20 vfnmsubsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7f 39 20 vfnmsubsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7f 39 20 vfnmsubsd xmm7,xmm2,xmm6,QWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7f 39 20 vfnmsubsd xmm7,xmm2,QWORD PTR \[ecx\],xmm4
+[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e3 49 0b d4 07 vroundsd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0b 11 07 vroundsd xmm2,xmm6,QWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0b 11 07 vroundsd xmm2,xmm6,QWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca 58 11 vaddss xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca 58 11 vaddss xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si ecx,xmm4
[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si ecx,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si ecx,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd DWORD PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd DWORD PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[ecx\],xmm4,0x64
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps DWORD PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps DWORD PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 16 e1 07 vpextrd ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 16 21 07 vpextrd DWORD PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 16 21 07 vpextrd DWORD PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 17 e1 07 vextractps ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps DWORD PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps DWORD PTR \[ecx\],xmm4,0x7
[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd xmm6,xmm4,ecx
[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sd xmm6,xmm4,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sd xmm6,xmm4,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss xmm6,xmm4,ecx
[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ss xmm6,xmm4,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ss xmm6,xmm4,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss xmm2,xmm6,DWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss xmm2,xmm6,DWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps xmm2,xmm6,DWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps xmm2,xmm6,DWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss xmm2,xmm6,DWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss xmm2,xmm6,DWORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 c9 6a fc 20 vfmaddss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6a 39 20 vfmaddss xmm7,xmm2,xmm6,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6a 39 20 vfmaddss xmm7,xmm2,DWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6a 39 20 vfmaddss xmm7,xmm2,xmm6,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6a 39 20 vfmaddss xmm7,xmm2,DWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6e fc 20 vfmsubss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6e 39 20 vfmsubss xmm7,xmm2,xmm6,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6e 39 20 vfmsubss xmm7,xmm2,DWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6e 39 20 vfmsubss xmm7,xmm2,xmm6,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 6e 39 20 vfmsubss xmm7,xmm2,DWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7a fc 20 vfnmaddss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7a 39 20 vfnmaddss xmm7,xmm2,xmm6,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7a 39 20 vfnmaddss xmm7,xmm2,DWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7a 39 20 vfnmaddss xmm7,xmm2,xmm6,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7a 39 20 vfnmaddss xmm7,xmm2,DWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7e fc 20 vfnmsubss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7e 39 20 vfnmsubss xmm7,xmm2,xmm6,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7e 39 20 vfnmsubss xmm7,xmm2,DWORD PTR \[ecx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7e 39 20 vfnmsubss xmm7,xmm2,xmm6,DWORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c4 e3 59 7e 39 20 vfnmsubss xmm7,xmm2,DWORD PTR \[ecx\],xmm4
+[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e3 49 21 d4 07 vinsertps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 21 11 07 vinsertps xmm2,xmm6,DWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 21 11 07 vinsertps xmm2,xmm6,DWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0a d4 07 vroundss xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0a 11 07 vroundss xmm2,xmm6,DWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0a 11 07 vroundss xmm2,xmm6,DWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq xmm4,WORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq xmm4,WORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq xmm4,WORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq xmm4,WORD PTR \[ecx\]
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw xmm6,xmm4,ecx,0x64
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[ecx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x64
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw WORD PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw WORD PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw WORD PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw WORD PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c5 d9 c4 f1 07 vpinsrw xmm6,xmm4,ecx,0x7
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw xmm6,xmm4,WORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw xmm6,xmm4,WORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 e1 07 vpextrb ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb BYTE PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb BYTE PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb xmm6,xmm4,ecx,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb BYTE PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb BYTE PTR \[ecx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb xmm6,xmm4,ecx,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb xmm6,xmm4,BYTE PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu xmm6,xmm4
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd ecx,xmm4
[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64
+[ ]*[a-f0-9]+: c5 c9 72 f4 07 vpslld xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 fc 07 vpslldq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 f4 07 vpsllq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 71 f4 07 vpsllw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 72 e4 07 vpsrad xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 71 e4 07 vpsraw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 72 d4 07 vpsrld xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 dc 07 vpsrldq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 d4 07 vpsrlq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 71 d4 07 vpsrlw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw ecx,xmm4,0x7
[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd ecx,ymm4
[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps ecx,ymm4
[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq xmm6,xmm4
[ ]*[a-f0-9]+: c5 fe e6 05 34 12 00 00 vcvtdq2pd ymm0,XMMWORD PTR ds:0x1234
[ ]*[a-f0-9]+: c5 fd 5a 05 34 12 00 00 vcvtpd2ps xmm0,YMMWORD PTR ds:0x1234
[ ]*[a-f0-9]+: c5 f9 e0 3d 34 12 00 00 vpavgb xmm7,xmm0,XMMWORD PTR ds:0x1234
-[ ]*[a-f0-9]+: c4 e3 79 df 05 34 12 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR ds:0x1234,0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 05 34 12 00 00 64 vpextrb BYTE PTR ds:0x1234,xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 05 34 12 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR ds:0x1234,0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 05 34 12 00 00 07 vpextrb BYTE PTR ds:0x1234,xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a 3d 34 12 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR ds:0x1234
[ ]*[a-f0-9]+: c4 e3 59 4a 35 34 12 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR ds:0x1234,xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 3d 34 12 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR ds:0x1234,0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 3d 34 12 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR ds:0x1234,0x7
[ ]*[a-f0-9]+: c5 fd 6f 05 34 12 00 00 vmovdqa ymm0,YMMWORD PTR ds:0x1234
[ ]*[a-f0-9]+: c5 fd 7f 05 34 12 00 00 vmovdqa YMMWORD PTR ds:0x1234,ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d 3d 34 12 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR ds:0x1234
-[ ]*[a-f0-9]+: c4 e3 7d 09 05 34 12 00 00 64 vroundpd ymm0,YMMWORD PTR ds:0x1234,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 05 34 12 00 00 64 vextractf128 XMMWORD PTR ds:0x1234,ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 3d 34 12 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR ds:0x1234,0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 05 34 12 00 00 07 vroundpd ymm0,YMMWORD PTR ds:0x1234,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 05 34 12 00 00 07 vextractf128 XMMWORD PTR ds:0x1234,ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 3d 34 12 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR ds:0x1234,0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b 35 34 12 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR ds:0x1234,ymm0
[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr DWORD PTR \[ebp\+0x0\]
[ ]*[a-f0-9]+: c5 f9 6f 45 00 vmovdqa xmm0,XMMWORD PTR \[ebp\+0x0\]
[ ]*[a-f0-9]+: c5 fe e6 45 00 vcvtdq2pd ymm0,XMMWORD PTR \[ebp\+0x0\]
[ ]*[a-f0-9]+: c5 fd 5a 45 00 vcvtpd2ps xmm0,YMMWORD PTR \[ebp\+0x0\]
[ ]*[a-f0-9]+: c5 f9 e0 7d 00 vpavgb xmm7,xmm0,XMMWORD PTR \[ebp\+0x0\]
-[ ]*[a-f0-9]+: c4 e3 79 df 45 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[ebp\+0x0\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 45 00 64 vpextrb BYTE PTR \[ebp\+0x0\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 45 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[ebp\+0x0\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 45 00 07 vpextrb BYTE PTR \[ebp\+0x0\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a 7d 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+0x0\]
[ ]*[a-f0-9]+: c4 e3 59 4a 75 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[ebp\+0x0\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 7d 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+0x0\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 7d 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+0x0\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 45 00 vmovdqa ymm0,YMMWORD PTR \[ebp\+0x0\]
[ ]*[a-f0-9]+: c5 fd 7f 45 00 vmovdqa YMMWORD PTR \[ebp\+0x0\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d 7d 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[ebp\+0x0\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 45 00 64 vroundpd ymm0,YMMWORD PTR \[ebp\+0x0\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 45 00 64 vextractf128 XMMWORD PTR \[ebp\+0x0\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 7d 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+0x0\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 45 00 07 vroundpd ymm0,YMMWORD PTR \[ebp\+0x0\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 45 00 07 vextractf128 XMMWORD PTR \[ebp\+0x0\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 7d 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+0x0\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b 75 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[ebp\+0x0\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr DWORD PTR \[ebp\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 85 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[ebp\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 85 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[ebp\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 85 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[ebp\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 bd 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[ebp\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 85 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[ebp\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 85 99 00 00 00 64 vpextrb BYTE PTR \[ebp\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 85 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[ebp\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 85 99 00 00 00 07 vpextrb BYTE PTR \[ebp\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a bd 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a b5 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[ebp\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 bd 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 bd 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 85 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[ebp\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 85 99 00 00 00 vmovdqa YMMWORD PTR \[ebp\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d bd 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[ebp\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 85 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[ebp\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 85 99 00 00 00 64 vextractf128 XMMWORD PTR \[ebp\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 bd 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 85 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[ebp\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 85 99 00 00 00 07 vextractf128 XMMWORD PTR \[ebp\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 bd 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b b5 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[ebp\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 14 25 99 00 00 00 vldmxcsr DWORD PTR \[eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 04 25 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 04 25 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 04 25 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 3c 25 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eiz\*1\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 04 25 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[eiz\*1\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 04 25 99 00 00 00 64 vpextrb BYTE PTR \[eiz\*1\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 04 25 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[eiz\*1\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 04 25 99 00 00 00 07 vpextrb BYTE PTR \[eiz\*1\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a 3c 25 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a 34 25 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eiz\*1\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 3c 25 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eiz\*1\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 3c 25 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[eiz\*1\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 04 25 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 04 25 99 00 00 00 vmovdqa YMMWORD PTR \[eiz\*1\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 25 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eiz\*1\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 04 25 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eiz\*1\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 04 25 99 00 00 00 64 vextractf128 XMMWORD PTR \[eiz\*1\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 3c 25 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eiz\*1\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 04 25 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[eiz\*1\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 04 25 99 00 00 00 07 vextractf128 XMMWORD PTR \[eiz\*1\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 3c 25 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eiz\*1\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b 34 25 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eiz\*1\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 14 65 99 00 00 00 vldmxcsr DWORD PTR \[eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 04 65 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 04 65 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 04 65 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 3c 65 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eiz\*2\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 04 65 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[eiz\*2\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 04 65 99 00 00 00 64 vpextrb BYTE PTR \[eiz\*2\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 04 65 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[eiz\*2\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 04 65 99 00 00 00 07 vpextrb BYTE PTR \[eiz\*2\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a 3c 65 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a 34 65 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eiz\*2\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 3c 65 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eiz\*2\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 3c 65 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[eiz\*2\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 04 65 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 04 65 99 00 00 00 vmovdqa YMMWORD PTR \[eiz\*2\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 65 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eiz\*2\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 04 65 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eiz\*2\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 04 65 99 00 00 00 64 vextractf128 XMMWORD PTR \[eiz\*2\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 3c 65 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eiz\*2\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 04 65 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[eiz\*2\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 04 65 99 00 00 00 07 vextractf128 XMMWORD PTR \[eiz\*2\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 3c 65 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eiz\*2\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b 34 65 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eiz\*2\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 94 20 99 00 00 00 vldmxcsr DWORD PTR \[eax\+eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 84 20 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 84 20 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 84 20 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 bc 20 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 84 20 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 84 20 99 00 00 00 64 vpextrb BYTE PTR \[eax\+eiz\*1\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 84 20 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[eax\+eiz\*1\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 84 20 99 00 00 00 07 vpextrb BYTE PTR \[eax\+eiz\*1\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a bc 20 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a b4 20 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eax\+eiz\*1\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 20 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+eiz\*1\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 20 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+eiz\*1\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 84 20 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 84 20 99 00 00 00 vmovdqa YMMWORD PTR \[eax\+eiz\*1\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 20 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 20 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 20 99 00 00 00 64 vextractf128 XMMWORD PTR \[eax\+eiz\*1\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 20 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 20 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 20 99 00 00 00 07 vextractf128 XMMWORD PTR \[eax\+eiz\*1\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 20 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*1\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 20 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eax\+eiz\*1\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 94 60 99 00 00 00 vldmxcsr DWORD PTR \[eax\+eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 84 60 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 84 60 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 84 60 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 bc 60 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 84 60 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 84 60 99 00 00 00 64 vpextrb BYTE PTR \[eax\+eiz\*2\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 84 60 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[eax\+eiz\*2\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 84 60 99 00 00 00 07 vpextrb BYTE PTR \[eax\+eiz\*2\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a bc 60 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a b4 60 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eax\+eiz\*2\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 60 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+eiz\*2\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 60 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+eiz\*2\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 84 60 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 84 60 99 00 00 00 vmovdqa YMMWORD PTR \[eax\+eiz\*2\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 60 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 60 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 60 99 00 00 00 64 vextractf128 XMMWORD PTR \[eax\+eiz\*2\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 60 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 60 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 60 99 00 00 00 07 vextractf128 XMMWORD PTR \[eax\+eiz\*2\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 60 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+eiz\*2\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 60 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eax\+eiz\*2\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 94 98 99 00 00 00 vldmxcsr DWORD PTR \[eax\+ebx\*4\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 84 98 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 84 98 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 84 98 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 bc 98 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 84 98 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 84 98 99 00 00 00 64 vpextrb BYTE PTR \[eax\+ebx\*4\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 84 98 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[eax\+ebx\*4\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 84 98 99 00 00 00 07 vpextrb BYTE PTR \[eax\+ebx\*4\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a bc 98 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[eax\+ebx\*4\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a b4 98 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[eax\+ebx\*4\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 98 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+ebx\*4\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 98 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[eax\+ebx\*4\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 84 98 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 84 98 99 00 00 00 vmovdqa YMMWORD PTR \[eax\+ebx\*4\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 98 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 98 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 98 99 00 00 00 64 vextractf128 XMMWORD PTR \[eax\+ebx\*4\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 98 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 98 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 98 99 00 00 00 07 vextractf128 XMMWORD PTR \[eax\+ebx\*4\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 98 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[eax\+ebx\*4\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 98 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[eax\+ebx\*4\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 94 cc 99 00 00 00 vldmxcsr DWORD PTR \[esp\+ecx\*8\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 84 cc 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 84 cc 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 84 cc 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 bc cc 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 84 cc 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 84 cc 99 00 00 00 64 vpextrb BYTE PTR \[esp\+ecx\*8\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 84 cc 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[esp\+ecx\*8\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 84 cc 99 00 00 00 07 vpextrb BYTE PTR \[esp\+ecx\*8\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a bc cc 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[esp\+ecx\*8\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a b4 cc 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[esp\+ecx\*8\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 bc cc 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[esp\+ecx\*8\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 bc cc 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[esp\+ecx\*8\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 84 cc 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 84 cc 99 00 00 00 vmovdqa YMMWORD PTR \[esp\+ecx\*8\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d bc cc 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 cc 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 cc 99 00 00 00 64 vextractf128 XMMWORD PTR \[esp\+ecx\*8\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc cc 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 cc 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 cc 99 00 00 00 07 vextractf128 XMMWORD PTR \[esp\+ecx\*8\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc cc 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[esp\+ecx\*8\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 cc 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[esp\+ecx\*8\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f8 ae 94 15 99 00 00 00 vldmxcsr DWORD PTR \[ebp\+edx\*1\+0x99\]
[ ]*[a-f0-9]+: c5 f9 6f 84 15 99 00 00 00 vmovdqa xmm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fe e6 84 15 99 00 00 00 vcvtdq2pd ymm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fd 5a 84 15 99 00 00 00 vcvtpd2ps xmm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\]
[ ]*[a-f0-9]+: c5 f9 e0 bc 15 99 00 00 00 vpavgb xmm7,xmm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 79 df 84 15 99 00 00 00 64 vaeskeygenassist xmm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 84 15 99 00 00 00 64 vpextrb BYTE PTR \[ebp\+edx\*1\+0x99\],xmm0,0x64
+[ ]*[a-f0-9]+: c4 e3 79 df 84 15 99 00 00 00 07 vaeskeygenassist xmm0,XMMWORD PTR \[ebp\+edx\*1\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 84 15 99 00 00 00 07 vpextrb BYTE PTR \[ebp\+edx\*1\+0x99\],xmm0,0x7
[ ]*[a-f0-9]+: c5 fb 2a bc 15 99 00 00 00 vcvtsi2sd xmm7,xmm0,DWORD PTR \[ebp\+edx\*1\+0x99\]
[ ]*[a-f0-9]+: c4 e3 59 4a b4 15 99 00 00 00 00 vblendvps xmm6,xmm4,XMMWORD PTR \[ebp\+edx\*1\+0x99\],xmm0
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 15 99 00 00 00 64 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+edx\*1\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 15 99 00 00 00 07 vpinsrb xmm7,xmm0,BYTE PTR \[ebp\+edx\*1\+0x99\],0x7
[ ]*[a-f0-9]+: c5 fd 6f 84 15 99 00 00 00 vmovdqa ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\]
[ ]*[a-f0-9]+: c5 fd 7f 84 15 99 00 00 00 vmovdqa YMMWORD PTR \[ebp\+edx\*1\+0x99\],ymm0
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 15 99 00 00 00 vpermilpd ymm7,ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\]
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 15 99 00 00 00 64 vroundpd ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 15 99 00 00 00 64 vextractf128 XMMWORD PTR \[ebp\+edx\*1\+0x99\],ymm0,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 15 99 00 00 00 64 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 15 99 00 00 00 07 vroundpd ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 15 99 00 00 00 07 vextractf128 XMMWORD PTR \[ebp\+edx\*1\+0x99\],ymm0,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 15 99 00 00 00 07 vperm2f128 ymm7,ymm0,YMMWORD PTR \[ebp\+edx\*1\+0x99\],0x7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 15 99 00 00 00 00 vblendvpd ymm6,ymm4,YMMWORD PTR \[ebp\+edx\*1\+0x99\],ymm0
[ ]*[a-f0-9]+: c5 f9 50 c0 vmovmskpd eax,xmm0
-[ ]*[a-f0-9]+: c5 c1 72 f0 64 vpslld xmm7,xmm0,0x64
+[ ]*[a-f0-9]+: c5 c1 72 f0 07 vpslld xmm7,xmm0,0x7
[ ]*[a-f0-9]+: c5 fc 50 c0 vmovmskps eax,ymm0
#pass
[ ]*[a-f0-9]+: c4 e2 4d 2f 21 vmaskmovpd %ymm4,%ymm6,\(%ecx\)
[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps \(%ecx\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps %ymm4,%ymm6,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd \$0x64,\(%ecx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps \$0x64,\(%ecx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd \$0x64,\(%ecx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps \$0x64,\(%ecx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 05 d6 07 vpermilpd \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 05 31 07 vpermilpd \$0x7,\(%ecx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 04 d6 07 vpermilps \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 04 31 07 vpermilps \$0x7,\(%ecx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 09 d6 07 vroundpd \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 09 31 07 vroundpd \$0x7,\(%ecx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 08 d6 07 vroundps \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 08 31 07 vroundps \$0x7,\(%ecx\),%ymm6
[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc 58 d4 vaddps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2psy \(%ecx\),%xmm4
[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq %ymm4,%xmm4
[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dqy \(%ecx\),%xmm4
-[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 5b f4 vcvtdq2ps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 5b f4 vcvtps2dq %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 5b f4 vcvttps2dq %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 ff 12 f4 vmovddup %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 16 f4 vmovshdup %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 12 f4 vmovsldup %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 10 21 vmovups \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest %ymm4,%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 17 f4 vptest %ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 53 f4 vrcpps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 52 f4 vrsqrtps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 51 f4 vsqrtpd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 51 f4 vsqrtps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0f f4 vtestpd %ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0e f4 vtestps %ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps \$0x64,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0d d4 07 vblendpd \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0d 11 07 vblendpd \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0c d4 07 vblendps \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0c 11 07 vblendps \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 40 d4 07 vdpps \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 40 11 07 vdpps \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 06 d4 07 vperm2f128 \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 06 11 07 vperm2f128 \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c6 d4 07 vshufpd \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%ecx\),%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps %ymm4,%ymm6,%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps %ymm4,\(%ecx\),%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 69 39 20 vfmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 68 fc 20 vfmaddps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 68 39 20 vfmaddps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5d fc 20 vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5d 39 20 vfmaddsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5c fc 20 vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5c 39 20 vfmaddsubps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5f fc 20 vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5f 39 20 vfmsubaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5e fc 20 vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5e 39 20 vfmsubaddps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6d fc 20 vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6d 39 20 vfmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6c fc 20 vfmsubps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6c 39 20 vfmsubps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 79 fc 20 vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 79 39 20 vfnmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 78 fc 20 vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 78 39 20 vfnmaddps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7d fc 20 vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7d 39 20 vfnmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7c fc 20 vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7c 39 20 vfnmsubps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd \$0xa,%ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd \$0xa,\(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps \$0xa,%ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps \$0xa,\(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 \$0x64,%xmm4,%ymm4,%ymm6
-[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 \$0x64,\(%ecx\),%ymm4,%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 \$0x64,%ymm4,%xmm4
-[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 \$0x64,%ymm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 5d 18 f4 07 vinsertf128 \$0x7,%xmm4,%ymm4,%ymm6
+[ ]*[a-f0-9]+: c4 e3 5d 18 31 07 vinsertf128 \$0x7,\(%ecx\),%ymm4,%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 19 e4 07 vextractf128 \$0x7,%ymm4,%xmm4
+[ ]*[a-f0-9]+: c4 e3 7d 19 21 07 vextractf128 \$0x7,%ymm4,\(%ecx\)
[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps \(%ecx\),%xmm4
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%ecx\),%xmm6,%xmm7
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%ecx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 df f4 64 vaeskeygenassist \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 df 31 64 vaeskeygenassist \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps \$0x64,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 df 31 07 vaeskeygenassist \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 61 f4 07 vpcmpestri \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 61 31 07 vpcmpestri \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 60 f4 07 vpcmpestrm \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 60 31 07 vpcmpestrm \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 63 f4 07 vpcmpistri \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 63 31 07 vpcmpistri \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 62 f4 07 vpcmpistrm \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 62 31 07 vpcmpistrm \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 05 f4 07 vpermilpd \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 05 31 07 vpermilpd \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 04 f4 07 vpermilps \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 04 31 07 vpermilps \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c5 f9 70 f4 07 vpshufd \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 f9 70 31 07 vpshufd \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c5 fa 70 f4 07 vpshufhw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 fa 70 31 07 vpshufhw \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c5 fb 70 f4 07 vpshuflw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 fb 70 31 07 vpshuflw \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 09 f4 07 vroundpd \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 09 31 07 vroundpd \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 08 f4 07 vroundps \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 08 31 07 vroundps \$0x7,\(%ecx\),%xmm6
[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps %xmm4,%xmm6,\(%ecx\)
[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd %xmm4,%xmm6,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps \$0x64,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0d d4 07 vblendpd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0d 11 07 vblendpd \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0c d4 07 vblendps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0c 11 07 vblendps \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c2 11 07 vcmpordpd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c2 11 07 vcmpordps \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 41 d4 07 vdppd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 41 11 07 vdppd \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 40 d4 07 vdpps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 40 11 07 vdpps \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 42 d4 07 vmpsadbw \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 42 11 07 vmpsadbw \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0f d4 07 vpalignr \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0f 11 07 vpalignr \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0e d4 07 vpblendw \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0e 11 07 vpblendw \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c6 d4 07 vshufpd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%ecx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps %xmm4,%xmm6,%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4a 39 40 vblendvps %xmm4,\(%ecx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb %xmm4,%xmm6,%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 69 fc 20 vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 69 39 20 vfmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 69 39 20 vfmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 68 fc 20 vfmaddps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 68 39 20 vfmaddps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 68 39 20 vfmaddps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5d fc 20 vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5d 39 20 vfmaddsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5d 39 20 vfmaddsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5c fc 20 vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5c 39 20 vfmaddsubps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5c 39 20 vfmaddsubps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5f fc 20 vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5f 39 20 vfmsubaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5f 39 20 vfmsubaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5e fc 20 vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5e 39 20 vfmsubaddps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5e 39 20 vfmsubaddps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6d fc 20 vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6d 39 20 vfmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6d 39 20 vfmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6c fc 20 vfmsubps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6c 39 20 vfmsubps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6c 39 20 vfmsubps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 79 fc 20 vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 79 39 20 vfnmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 79 39 20 vfnmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 78 fc 20 vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 78 39 20 vfnmaddps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 78 39 20 vfnmaddps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7d fc 20 vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7d 39 20 vfnmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7d 39 20 vfnmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7c fc 20 vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7c 39 20 vfnmsubps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7c 39 20 vfnmsubps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd \$0xa,%xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd \$0xa,\(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd \$0xa,%xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps \$0xa,%xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps \$0xa,\(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps \$0xa,%xmm4,\(%ecx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd \(%ecx\),%xmm4
[ ]*[a-f0-9]+: c5 d8 12 31 vmovlps \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps \(%ecx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 c9 6b fc 20 vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6b 39 20 vfmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6b 39 20 vfmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6f fc 20 vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6f 39 20 vfmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6f 39 20 vfmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7b fc 20 vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7b 39 20 vfnmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7b 39 20 vfnmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7f fc 20 vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7f 39 20 vfnmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7f 39 20 vfnmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7
+[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0b d4 07 vroundsd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0b 11 07 vroundsd \$0x7,\(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 5a d4 vcvtsd2ss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 1e vcmpgt_oqsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%ecx\)
+[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%ecx\)
[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca 58 11 vaddss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca 5a d4 vcvtss2sd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 fa 2d 09 vcvtss2si \(%ecx\),%ecx
[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si %xmm4,%ecx
[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si \(%ecx\),%ecx
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 16 e1 07 vpextrd \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 16 21 07 vpextrd \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 17 e1 07 vextractps \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps \$0x7,%xmm4,\(%ecx\)
[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd %ecx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sdl \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss %ecx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ssl \(%ecx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 c9 6a fc 20 vfmaddss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6a 39 20 vfmaddss \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6a 39 20 vfmaddss %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6e fc 20 vfmsubss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6e 39 20 vfmsubss \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6e 39 20 vfmsubss %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7a fc 20 vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7a 39 20 vfnmaddss \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7a 39 20 vfnmaddss %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7e fc 20 vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7e 39 20 vfnmsubss \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7e 39 20 vfnmsubss %xmm4,\(%ecx\),%xmm2,%xmm7
+[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 21 d4 07 vinsertps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 21 11 07 vinsertps \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0a d4 07 vroundss \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0a 11 07 vroundss \$0x7,\(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq \(%ecx\),%xmm4
[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq \(%ecx\),%xmm4
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%ecx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%ecx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%ecx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c5 d9 c4 f1 07 vpinsrw \$0x7,%ecx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw \$0x7,\(%ecx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 14 e1 07 vpextrb \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb \$0x7,%ecx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb \$0x7,\(%ecx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb \$0x7,%ecx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb \$0x7,\(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx
[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
+[ ]*[a-f0-9]+: c5 c9 72 f4 07 vpslld \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 fc 07 vpslldq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 f4 07 vpsllq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 71 f4 07 vpsllw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 72 e4 07 vpsrad \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 71 e4 07 vpsraw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 72 d4 07 vpsrld \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 dc 07 vpsrldq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 d4 07 vpsrlq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 71 d4 07 vpsrlw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw \$0x7,%xmm4,%ecx
[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd %ymm4,%ecx
[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps %ymm4,%ecx
[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 fe e6 05 34 12 00 00 vcvtdq2pd 0x1234,%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 05 34 12 00 00 vcvtpd2psy 0x1234,%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 3d 34 12 00 00 vpavgb 0x1234,%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 05 34 12 00 00 64 vaeskeygenassist \$0x64,0x1234,%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 05 34 12 00 00 64 vpextrb \$0x64,%xmm0,0x1234
+[ ]*[a-f0-9]+: c4 e3 79 df 05 34 12 00 00 07 vaeskeygenassist \$0x7,0x1234,%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 05 34 12 00 00 07 vpextrb \$0x7,%xmm0,0x1234
[ ]*[a-f0-9]+: c5 fb 2a 3d 34 12 00 00 vcvtsi2sdl 0x1234,%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a 35 34 12 00 00 00 vblendvps %xmm0,0x1234,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 3d 34 12 00 00 64 vpinsrb \$0x64,0x1234,%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 3d 34 12 00 00 07 vpinsrb \$0x7,0x1234,%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 05 34 12 00 00 vmovdqa 0x1234,%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 05 34 12 00 00 vmovdqa %ymm0,0x1234
[ ]*[a-f0-9]+: c4 e2 7d 0d 3d 34 12 00 00 vpermilpd 0x1234,%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 05 34 12 00 00 64 vroundpd \$0x64,0x1234,%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 05 34 12 00 00 64 vextractf128 \$0x64,%ymm0,0x1234
-[ ]*[a-f0-9]+: c4 e3 7d 06 3d 34 12 00 00 64 vperm2f128 \$0x64,0x1234,%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 05 34 12 00 00 07 vroundpd \$0x7,0x1234,%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 05 34 12 00 00 07 vextractf128 \$0x7,%ymm0,0x1234
+[ ]*[a-f0-9]+: c4 e3 7d 06 3d 34 12 00 00 07 vperm2f128 \$0x7,0x1234,%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b 35 34 12 00 00 00 vblendvpd %ymm0,0x1234,%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr 0x0\(%ebp\)
[ ]*[a-f0-9]+: c5 f9 6f 45 00 vmovdqa 0x0\(%ebp\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 45 00 vcvtdq2pd 0x0\(%ebp\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 45 00 vcvtpd2psy 0x0\(%ebp\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 7d 00 vpavgb 0x0\(%ebp\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 45 00 64 vaeskeygenassist \$0x64,0x0\(%ebp\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 45 00 64 vpextrb \$0x64,%xmm0,0x0\(%ebp\)
+[ ]*[a-f0-9]+: c4 e3 79 df 45 00 07 vaeskeygenassist \$0x7,0x0\(%ebp\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 45 00 07 vpextrb \$0x7,%xmm0,0x0\(%ebp\)
[ ]*[a-f0-9]+: c5 fb 2a 7d 00 vcvtsi2sdl 0x0\(%ebp\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a 75 00 00 vblendvps %xmm0,0x0\(%ebp\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 7d 00 64 vpinsrb \$0x64,0x0\(%ebp\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 7d 00 07 vpinsrb \$0x7,0x0\(%ebp\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 45 00 vmovdqa 0x0\(%ebp\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 45 00 vmovdqa %ymm0,0x0\(%ebp\)
[ ]*[a-f0-9]+: c4 e2 7d 0d 7d 00 vpermilpd 0x0\(%ebp\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 45 00 64 vroundpd \$0x64,0x0\(%ebp\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 45 00 64 vextractf128 \$0x64,%ymm0,0x0\(%ebp\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 7d 00 64 vperm2f128 \$0x64,0x0\(%ebp\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 45 00 07 vroundpd \$0x7,0x0\(%ebp\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 45 00 07 vextractf128 \$0x7,%ymm0,0x0\(%ebp\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 7d 00 07 vperm2f128 \$0x7,0x0\(%ebp\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b 75 00 00 vblendvpd %ymm0,0x0\(%ebp\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 14 24 vldmxcsr \(%esp\)
[ ]*[a-f0-9]+: c5 f9 6f 04 24 vmovdqa \(%esp\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 04 24 vcvtdq2pd \(%esp\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 04 24 vcvtpd2psy \(%esp\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 3c 24 vpavgb \(%esp\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 04 24 64 vaeskeygenassist \$0x64,\(%esp\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 04 24 64 vpextrb \$0x64,%xmm0,\(%esp\)
+[ ]*[a-f0-9]+: c4 e3 79 df 04 24 07 vaeskeygenassist \$0x7,\(%esp\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 04 24 07 vpextrb \$0x7,%xmm0,\(%esp\)
[ ]*[a-f0-9]+: c5 fb 2a 3c 24 vcvtsi2sdl \(%esp\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a 34 24 00 vblendvps %xmm0,\(%esp\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 3c 24 64 vpinsrb \$0x64,\(%esp\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 3c 24 07 vpinsrb \$0x7,\(%esp\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 04 24 vmovdqa \(%esp\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 04 24 vmovdqa %ymm0,\(%esp\)
[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 24 vpermilpd \(%esp\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 04 24 64 vroundpd \$0x64,\(%esp\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 04 24 64 vextractf128 \$0x64,%ymm0,\(%esp\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 3c 24 64 vperm2f128 \$0x64,\(%esp\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 04 24 07 vroundpd \$0x7,\(%esp\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 04 24 07 vextractf128 \$0x7,%ymm0,\(%esp\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 3c 24 07 vperm2f128 \$0x7,\(%esp\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b 34 24 00 vblendvpd %ymm0,\(%esp\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr 0x99\(%ebp\)
[ ]*[a-f0-9]+: c5 f9 6f 85 99 00 00 00 vmovdqa 0x99\(%ebp\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 85 99 00 00 00 vcvtdq2pd 0x99\(%ebp\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 85 99 00 00 00 vcvtpd2psy 0x99\(%ebp\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 bd 99 00 00 00 vpavgb 0x99\(%ebp\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 85 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%ebp\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 85 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%ebp\)
+[ ]*[a-f0-9]+: c4 e3 79 df 85 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%ebp\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 85 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(%ebp\)
[ ]*[a-f0-9]+: c5 fb 2a bd 99 00 00 00 vcvtsi2sdl 0x99\(%ebp\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a b5 99 00 00 00 00 vblendvps %xmm0,0x99\(%ebp\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 bd 99 00 00 00 64 vpinsrb \$0x64,0x99\(%ebp\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 bd 99 00 00 00 07 vpinsrb \$0x7,0x99\(%ebp\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 85 99 00 00 00 vmovdqa 0x99\(%ebp\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 85 99 00 00 00 vmovdqa %ymm0,0x99\(%ebp\)
[ ]*[a-f0-9]+: c4 e2 7d 0d bd 99 00 00 00 vpermilpd 0x99\(%ebp\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 85 99 00 00 00 64 vroundpd \$0x64,0x99\(%ebp\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 85 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%ebp\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 bd 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%ebp\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 85 99 00 00 00 07 vroundpd \$0x7,0x99\(%ebp\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 85 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(%ebp\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 bd 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%ebp\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b b5 99 00 00 00 00 vblendvpd %ymm0,0x99\(%ebp\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 14 25 99 00 00 00 vldmxcsr 0x99\(,%eiz,1\)
[ ]*[a-f0-9]+: c5 f9 6f 04 25 99 00 00 00 vmovdqa 0x99\(,%eiz,1\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 04 25 99 00 00 00 vcvtdq2pd 0x99\(,%eiz,1\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 04 25 99 00 00 00 vcvtpd2psy 0x99\(,%eiz,1\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 3c 25 99 00 00 00 vpavgb 0x99\(,%eiz,1\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 04 25 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(,%eiz,1\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 04 25 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(,%eiz,1\)
+[ ]*[a-f0-9]+: c4 e3 79 df 04 25 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(,%eiz,1\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 04 25 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(,%eiz,1\)
[ ]*[a-f0-9]+: c5 fb 2a 3c 25 99 00 00 00 vcvtsi2sdl 0x99\(,%eiz,1\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a 34 25 99 00 00 00 00 vblendvps %xmm0,0x99\(,%eiz,1\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 3c 25 99 00 00 00 64 vpinsrb \$0x64,0x99\(,%eiz,1\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 3c 25 99 00 00 00 07 vpinsrb \$0x7,0x99\(,%eiz,1\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 04 25 99 00 00 00 vmovdqa 0x99\(,%eiz,1\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 04 25 99 00 00 00 vmovdqa %ymm0,0x99\(,%eiz,1\)
[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 25 99 00 00 00 vpermilpd 0x99\(,%eiz,1\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 04 25 99 00 00 00 64 vroundpd \$0x64,0x99\(,%eiz,1\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 04 25 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(,%eiz,1\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 3c 25 99 00 00 00 64 vperm2f128 \$0x64,0x99\(,%eiz,1\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 04 25 99 00 00 00 07 vroundpd \$0x7,0x99\(,%eiz,1\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 04 25 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(,%eiz,1\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 3c 25 99 00 00 00 07 vperm2f128 \$0x7,0x99\(,%eiz,1\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b 34 25 99 00 00 00 00 vblendvpd %ymm0,0x99\(,%eiz,1\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 14 65 99 00 00 00 vldmxcsr 0x99\(,%eiz,2\)
[ ]*[a-f0-9]+: c5 f9 6f 04 65 99 00 00 00 vmovdqa 0x99\(,%eiz,2\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 04 65 99 00 00 00 vcvtdq2pd 0x99\(,%eiz,2\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 04 65 99 00 00 00 vcvtpd2psy 0x99\(,%eiz,2\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 3c 65 99 00 00 00 vpavgb 0x99\(,%eiz,2\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 04 65 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(,%eiz,2\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 04 65 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(,%eiz,2\)
+[ ]*[a-f0-9]+: c4 e3 79 df 04 65 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(,%eiz,2\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 04 65 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(,%eiz,2\)
[ ]*[a-f0-9]+: c5 fb 2a 3c 65 99 00 00 00 vcvtsi2sdl 0x99\(,%eiz,2\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a 34 65 99 00 00 00 00 vblendvps %xmm0,0x99\(,%eiz,2\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 3c 65 99 00 00 00 64 vpinsrb \$0x64,0x99\(,%eiz,2\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 3c 65 99 00 00 00 07 vpinsrb \$0x7,0x99\(,%eiz,2\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 04 65 99 00 00 00 vmovdqa 0x99\(,%eiz,2\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 04 65 99 00 00 00 vmovdqa %ymm0,0x99\(,%eiz,2\)
[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 65 99 00 00 00 vpermilpd 0x99\(,%eiz,2\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 04 65 99 00 00 00 64 vroundpd \$0x64,0x99\(,%eiz,2\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 04 65 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(,%eiz,2\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 3c 65 99 00 00 00 64 vperm2f128 \$0x64,0x99\(,%eiz,2\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 04 65 99 00 00 00 07 vroundpd \$0x7,0x99\(,%eiz,2\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 04 65 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(,%eiz,2\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 3c 65 99 00 00 00 07 vperm2f128 \$0x7,0x99\(,%eiz,2\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b 34 65 99 00 00 00 00 vblendvpd %ymm0,0x99\(,%eiz,2\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 94 20 99 00 00 00 vldmxcsr 0x99\(%eax,%eiz,1\)
[ ]*[a-f0-9]+: c5 f9 6f 84 20 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,1\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 84 20 99 00 00 00 vcvtdq2pd 0x99\(%eax,%eiz,1\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 84 20 99 00 00 00 vcvtpd2psy 0x99\(%eax,%eiz,1\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 bc 20 99 00 00 00 vpavgb 0x99\(%eax,%eiz,1\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 84 20 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%eax,%eiz,1\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 84 20 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%eax,%eiz,1\)
+[ ]*[a-f0-9]+: c4 e3 79 df 84 20 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%eax,%eiz,1\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 84 20 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(%eax,%eiz,1\)
[ ]*[a-f0-9]+: c5 fb 2a bc 20 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%eiz,1\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a b4 20 99 00 00 00 00 vblendvps %xmm0,0x99\(%eax,%eiz,1\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 20 99 00 00 00 64 vpinsrb \$0x64,0x99\(%eax,%eiz,1\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 20 99 00 00 00 07 vpinsrb \$0x7,0x99\(%eax,%eiz,1\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 84 20 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,1\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 84 20 99 00 00 00 vmovdqa %ymm0,0x99\(%eax,%eiz,1\)
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 20 99 00 00 00 vpermilpd 0x99\(%eax,%eiz,1\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 20 99 00 00 00 64 vroundpd \$0x64,0x99\(%eax,%eiz,1\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 20 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%eax,%eiz,1\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 20 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%eax,%eiz,1\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 20 99 00 00 00 07 vroundpd \$0x7,0x99\(%eax,%eiz,1\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 20 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(%eax,%eiz,1\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 20 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%eax,%eiz,1\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 20 99 00 00 00 00 vblendvpd %ymm0,0x99\(%eax,%eiz,1\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 94 60 99 00 00 00 vldmxcsr 0x99\(%eax,%eiz,2\)
[ ]*[a-f0-9]+: c5 f9 6f 84 60 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,2\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 84 60 99 00 00 00 vcvtdq2pd 0x99\(%eax,%eiz,2\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 84 60 99 00 00 00 vcvtpd2psy 0x99\(%eax,%eiz,2\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 bc 60 99 00 00 00 vpavgb 0x99\(%eax,%eiz,2\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 84 60 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%eax,%eiz,2\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 84 60 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%eax,%eiz,2\)
+[ ]*[a-f0-9]+: c4 e3 79 df 84 60 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%eax,%eiz,2\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 84 60 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(%eax,%eiz,2\)
[ ]*[a-f0-9]+: c5 fb 2a bc 60 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%eiz,2\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a b4 60 99 00 00 00 00 vblendvps %xmm0,0x99\(%eax,%eiz,2\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 60 99 00 00 00 64 vpinsrb \$0x64,0x99\(%eax,%eiz,2\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 60 99 00 00 00 07 vpinsrb \$0x7,0x99\(%eax,%eiz,2\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 84 60 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,2\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 84 60 99 00 00 00 vmovdqa %ymm0,0x99\(%eax,%eiz,2\)
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 60 99 00 00 00 vpermilpd 0x99\(%eax,%eiz,2\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 60 99 00 00 00 64 vroundpd \$0x64,0x99\(%eax,%eiz,2\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 60 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%eax,%eiz,2\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 60 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%eax,%eiz,2\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 60 99 00 00 00 07 vroundpd \$0x7,0x99\(%eax,%eiz,2\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 60 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(%eax,%eiz,2\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 60 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%eax,%eiz,2\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 60 99 00 00 00 00 vblendvpd %ymm0,0x99\(%eax,%eiz,2\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 94 98 99 00 00 00 vldmxcsr 0x99\(%eax,%ebx,4\)
[ ]*[a-f0-9]+: c5 f9 6f 84 98 99 00 00 00 vmovdqa 0x99\(%eax,%ebx,4\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 84 98 99 00 00 00 vcvtdq2pd 0x99\(%eax,%ebx,4\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 84 98 99 00 00 00 vcvtpd2psy 0x99\(%eax,%ebx,4\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 bc 98 99 00 00 00 vpavgb 0x99\(%eax,%ebx,4\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 84 98 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%eax,%ebx,4\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 84 98 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%eax,%ebx,4\)
+[ ]*[a-f0-9]+: c4 e3 79 df 84 98 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%eax,%ebx,4\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 84 98 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(%eax,%ebx,4\)
[ ]*[a-f0-9]+: c5 fb 2a bc 98 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%ebx,4\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a b4 98 99 00 00 00 00 vblendvps %xmm0,0x99\(%eax,%ebx,4\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 98 99 00 00 00 64 vpinsrb \$0x64,0x99\(%eax,%ebx,4\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 98 99 00 00 00 07 vpinsrb \$0x7,0x99\(%eax,%ebx,4\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 84 98 99 00 00 00 vmovdqa 0x99\(%eax,%ebx,4\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 84 98 99 00 00 00 vmovdqa %ymm0,0x99\(%eax,%ebx,4\)
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 98 99 00 00 00 vpermilpd 0x99\(%eax,%ebx,4\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 98 99 00 00 00 64 vroundpd \$0x64,0x99\(%eax,%ebx,4\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 98 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%eax,%ebx,4\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 98 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%eax,%ebx,4\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 98 99 00 00 00 07 vroundpd \$0x7,0x99\(%eax,%ebx,4\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 98 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(%eax,%ebx,4\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 98 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%eax,%ebx,4\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 98 99 00 00 00 00 vblendvpd %ymm0,0x99\(%eax,%ebx,4\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 94 cc 99 00 00 00 vldmxcsr 0x99\(%esp,%ecx,8\)
[ ]*[a-f0-9]+: c5 f9 6f 84 cc 99 00 00 00 vmovdqa 0x99\(%esp,%ecx,8\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 84 cc 99 00 00 00 vcvtdq2pd 0x99\(%esp,%ecx,8\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 84 cc 99 00 00 00 vcvtpd2psy 0x99\(%esp,%ecx,8\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 bc cc 99 00 00 00 vpavgb 0x99\(%esp,%ecx,8\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 84 cc 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%esp,%ecx,8\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 84 cc 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%esp,%ecx,8\)
+[ ]*[a-f0-9]+: c4 e3 79 df 84 cc 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%esp,%ecx,8\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 84 cc 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(%esp,%ecx,8\)
[ ]*[a-f0-9]+: c5 fb 2a bc cc 99 00 00 00 vcvtsi2sdl 0x99\(%esp,%ecx,8\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a b4 cc 99 00 00 00 00 vblendvps %xmm0,0x99\(%esp,%ecx,8\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 bc cc 99 00 00 00 64 vpinsrb \$0x64,0x99\(%esp,%ecx,8\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 bc cc 99 00 00 00 07 vpinsrb \$0x7,0x99\(%esp,%ecx,8\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 84 cc 99 00 00 00 vmovdqa 0x99\(%esp,%ecx,8\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 84 cc 99 00 00 00 vmovdqa %ymm0,0x99\(%esp,%ecx,8\)
[ ]*[a-f0-9]+: c4 e2 7d 0d bc cc 99 00 00 00 vpermilpd 0x99\(%esp,%ecx,8\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 cc 99 00 00 00 64 vroundpd \$0x64,0x99\(%esp,%ecx,8\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 cc 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%esp,%ecx,8\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc cc 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%esp,%ecx,8\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 cc 99 00 00 00 07 vroundpd \$0x7,0x99\(%esp,%ecx,8\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 cc 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(%esp,%ecx,8\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc cc 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%esp,%ecx,8\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 cc 99 00 00 00 00 vblendvpd %ymm0,0x99\(%esp,%ecx,8\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 94 15 99 00 00 00 vldmxcsr 0x99\(%ebp,%edx,1\)
[ ]*[a-f0-9]+: c5 f9 6f 84 15 99 00 00 00 vmovdqa 0x99\(%ebp,%edx,1\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 84 15 99 00 00 00 vcvtdq2pd 0x99\(%ebp,%edx,1\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 84 15 99 00 00 00 vcvtpd2psy 0x99\(%ebp,%edx,1\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 bc 15 99 00 00 00 vpavgb 0x99\(%ebp,%edx,1\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 84 15 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%ebp,%edx,1\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 84 15 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%ebp,%edx,1\)
+[ ]*[a-f0-9]+: c4 e3 79 df 84 15 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%ebp,%edx,1\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 84 15 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(%ebp,%edx,1\)
[ ]*[a-f0-9]+: c5 fb 2a bc 15 99 00 00 00 vcvtsi2sdl 0x99\(%ebp,%edx,1\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a b4 15 99 00 00 00 00 vblendvps %xmm0,0x99\(%ebp,%edx,1\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 15 99 00 00 00 64 vpinsrb \$0x64,0x99\(%ebp,%edx,1\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 15 99 00 00 00 07 vpinsrb \$0x7,0x99\(%ebp,%edx,1\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 84 15 99 00 00 00 vmovdqa 0x99\(%ebp,%edx,1\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 84 15 99 00 00 00 vmovdqa %ymm0,0x99\(%ebp,%edx,1\)
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 15 99 00 00 00 vpermilpd 0x99\(%ebp,%edx,1\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 15 99 00 00 00 64 vroundpd \$0x64,0x99\(%ebp,%edx,1\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 15 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%ebp,%edx,1\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 15 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%ebp,%edx,1\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 15 99 00 00 00 07 vroundpd \$0x7,0x99\(%ebp,%edx,1\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 15 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(%ebp,%edx,1\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 15 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%ebp,%edx,1\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 15 99 00 00 00 00 vblendvpd %ymm0,0x99\(%ebp,%edx,1\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f9 50 c0 vmovmskpd %xmm0,%eax
-[ ]*[a-f0-9]+: c5 c1 72 f0 64 vpslld \$0x64,%xmm0,%xmm7
+[ ]*[a-f0-9]+: c5 c1 72 f0 07 vpslld \$0x7,%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fc 50 c0 vmovmskps %ymm0,%eax
[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%ecx\)
[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%ecx\)
[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps %ymm4,%ymm6,\(%ecx\)
[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps \(%ecx\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps %ymm4,%ymm6,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd \$0x64,\(%ecx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd \$0x64,\(%ecx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps \$0x64,\(%ecx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps \$0x64,\(%ecx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd \$0x64,\(%ecx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd \$0x64,\(%ecx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps \$0x64,\(%ecx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps \$0x64,\(%ecx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 05 d6 07 vpermilpd \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 05 31 07 vpermilpd \$0x7,\(%ecx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 05 31 07 vpermilpd \$0x7,\(%ecx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 04 d6 07 vpermilps \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 04 31 07 vpermilps \$0x7,\(%ecx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 04 31 07 vpermilps \$0x7,\(%ecx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 09 d6 07 vroundpd \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 09 31 07 vroundpd \$0x7,\(%ecx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 09 31 07 vroundpd \$0x7,\(%ecx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 08 d6 07 vroundps \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 08 31 07 vroundps \$0x7,\(%ecx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 08 31 07 vroundps \$0x7,\(%ecx\),%ymm6
[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2psy \(%ecx\),%xmm4
[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq %ymm4,%xmm4
[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dqy \(%ecx\),%xmm4
-[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 5b f4 vcvtdq2ps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 5b f4 vcvtps2dq %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 5b f4 vcvttps2dq %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 ff 12 f4 vmovddup %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 16 f4 vmovshdup %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 12 f4 vmovsldup %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 10 21 vmovups \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fc 10 21 vmovups \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest %ymm4,%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 17 f4 vptest %ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 53 f4 vrcpps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 52 f4 vrsqrtps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 51 f4 vsqrtpd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 51 f4 vsqrtps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0f f4 vtestpd %ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0e f4 vtestps %ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu \(%ecx\),%ymm4
-[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps \$0x64,\(%ecx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps \$0x64,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0d d4 07 vblendpd \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0d 11 07 vblendpd \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0d 11 07 vblendpd \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0c d4 07 vblendps \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0c 11 07 vblendps \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0c 11 07 vblendps \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 40 d4 07 vdpps \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 40 11 07 vdpps \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 40 11 07 vdpps \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 06 d4 07 vperm2f128 \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 06 11 07 vperm2f128 \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 06 11 07 vperm2f128 \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c6 d4 07 vshufpd \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%ecx\),%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%ecx\),%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps %ymm4,%ymm6,%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps %ymm4,\(%ecx\),%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps %ymm4,\(%ecx\),%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 69 39 20 vfmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 69 39 20 vfmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 68 fc 20 vfmaddps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 68 39 20 vfmaddps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 68 39 20 vfmaddps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5d fc 20 vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5d 39 20 vfmaddsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5d 39 20 vfmaddsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5c fc 20 vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5c 39 20 vfmaddsubps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5c 39 20 vfmaddsubps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5f fc 20 vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5f 39 20 vfmsubaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5f 39 20 vfmsubaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5e fc 20 vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5e 39 20 vfmsubaddps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5e 39 20 vfmsubaddps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6d fc 20 vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6d 39 20 vfmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6d 39 20 vfmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6c fc 20 vfmsubps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6c 39 20 vfmsubps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6c 39 20 vfmsubps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 79 fc 20 vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 79 39 20 vfnmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 79 39 20 vfnmaddpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 78 fc 20 vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 78 39 20 vfnmaddps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 78 39 20 vfnmaddps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7d fc 20 vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7d 39 20 vfnmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7d 39 20 vfnmsubpd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7c fc 20 vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7c 39 20 vfnmsubps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7c 39 20 vfnmsubps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps \(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd \$0xa,%ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd \$0xa,\(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd \$0xa,\(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps \$0xa,%ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps \$0xa,\(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps \$0xa,\(%ecx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 \$0x64,%xmm4,%ymm4,%ymm6
-[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 \$0x64,\(%ecx\),%ymm4,%ymm6
-[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 \$0x64,\(%ecx\),%ymm4,%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 \$0x64,%ymm4,%xmm4
-[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 \$0x64,%ymm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 \$0x64,%ymm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 5d 18 f4 07 vinsertf128 \$0x7,%xmm4,%ymm4,%ymm6
+[ ]*[a-f0-9]+: c4 e3 5d 18 31 07 vinsertf128 \$0x7,\(%ecx\),%ymm4,%ymm6
+[ ]*[a-f0-9]+: c4 e3 5d 18 31 07 vinsertf128 \$0x7,\(%ecx\),%ymm4,%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 19 e4 07 vextractf128 \$0x7,%ymm4,%xmm4
+[ ]*[a-f0-9]+: c4 e3 7d 19 21 07 vextractf128 \$0x7,%ymm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 7d 19 21 07 vextractf128 \$0x7,%ymm4,\(%ecx\)
[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%ecx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 df f4 64 vaeskeygenassist \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 df 31 64 vaeskeygenassist \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 df 31 64 vaeskeygenassist \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps \$0x64,\(%ecx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps \$0x64,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 df 31 07 vaeskeygenassist \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 df 31 07 vaeskeygenassist \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 61 f4 07 vpcmpestri \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 61 31 07 vpcmpestri \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 61 31 07 vpcmpestri \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 60 f4 07 vpcmpestrm \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 60 31 07 vpcmpestrm \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 60 31 07 vpcmpestrm \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 63 f4 07 vpcmpistri \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 63 31 07 vpcmpistri \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 63 31 07 vpcmpistri \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 62 f4 07 vpcmpistrm \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 62 31 07 vpcmpistrm \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 62 31 07 vpcmpistrm \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 05 f4 07 vpermilpd \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 05 31 07 vpermilpd \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 05 31 07 vpermilpd \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 04 f4 07 vpermilps \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 04 31 07 vpermilps \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 04 31 07 vpermilps \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c5 f9 70 f4 07 vpshufd \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 f9 70 31 07 vpshufd \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c5 f9 70 31 07 vpshufd \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c5 fa 70 f4 07 vpshufhw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 fa 70 31 07 vpshufhw \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c5 fa 70 31 07 vpshufhw \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c5 fb 70 f4 07 vpshuflw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 fb 70 31 07 vpshuflw \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c5 fb 70 31 07 vpshuflw \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 09 f4 07 vroundpd \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 09 31 07 vroundpd \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 09 31 07 vroundpd \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 08 f4 07 vroundps \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 08 31 07 vroundps \$0x7,\(%ecx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 08 31 07 vroundps \$0x7,\(%ecx\),%xmm6
[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps %xmm4,%xmm6,\(%ecx\)
[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps %xmm4,%xmm6,\(%ecx\)
[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd %xmm4,%xmm6,\(%ecx\)
[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd %xmm4,%xmm6,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps \$0x64,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0d d4 07 vblendpd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0d 11 07 vblendpd \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0d 11 07 vblendpd \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0c d4 07 vblendps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0c 11 07 vblendps \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0c 11 07 vblendps \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c2 11 07 vcmpordpd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c2 11 07 vcmpordpd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c2 11 07 vcmpordps \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c2 11 07 vcmpordps \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 41 d4 07 vdppd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 41 11 07 vdppd \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 41 11 07 vdppd \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 40 d4 07 vdpps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 40 11 07 vdpps \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 40 11 07 vdpps \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 42 d4 07 vmpsadbw \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 42 11 07 vmpsadbw \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 42 11 07 vmpsadbw \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0f d4 07 vpalignr \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0f 11 07 vpalignr \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0f 11 07 vpalignr \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0e d4 07 vpblendw \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0e 11 07 vpblendw \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0e 11 07 vpblendw \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c6 d4 07 vshufpd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%ecx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%ecx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb %xmm4,%xmm6,%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb %xmm4,\(%ecx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 69 fc 20 vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 69 39 20 vfmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 69 39 20 vfmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 69 39 20 vfmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 69 39 20 vfmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 68 fc 20 vfmaddps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 68 39 20 vfmaddps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 68 39 20 vfmaddps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 68 39 20 vfmaddps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 68 39 20 vfmaddps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5d fc 20 vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5d 39 20 vfmaddsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5d 39 20 vfmaddsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5d 39 20 vfmaddsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5d 39 20 vfmaddsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5c fc 20 vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5c 39 20 vfmaddsubps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5c 39 20 vfmaddsubps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5c 39 20 vfmaddsubps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5c 39 20 vfmaddsubps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5f fc 20 vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5f 39 20 vfmsubaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5f 39 20 vfmsubaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5f 39 20 vfmsubaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5f 39 20 vfmsubaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5e fc 20 vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5e 39 20 vfmsubaddps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5e 39 20 vfmsubaddps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5e 39 20 vfmsubaddps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5e 39 20 vfmsubaddps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6d fc 20 vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6d 39 20 vfmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6d 39 20 vfmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6d 39 20 vfmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6d 39 20 vfmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6c fc 20 vfmsubps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6c 39 20 vfmsubps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6c 39 20 vfmsubps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6c 39 20 vfmsubps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6c 39 20 vfmsubps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 79 fc 20 vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 79 39 20 vfnmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 79 39 20 vfnmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 79 39 20 vfnmaddpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 79 39 20 vfnmaddpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 78 fc 20 vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 78 39 20 vfnmaddps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 78 39 20 vfnmaddps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 78 39 20 vfnmaddps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 78 39 20 vfnmaddps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7d fc 20 vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7d 39 20 vfnmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7d 39 20 vfnmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7d 39 20 vfnmsubpd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7d 39 20 vfnmsubpd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7c fc 20 vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7c 39 20 vfnmsubps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7c 39 20 vfnmsubps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7c 39 20 vfnmsubps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7c 39 20 vfnmsubps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd \$0xa,%xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd \$0xa,\(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd \$0xa,%xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd \$0xa,\(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd \$0xa,%xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps \$0xa,%xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps \$0xa,\(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps \$0xa,%xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps \$0xa,\(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps \$0xa,%xmm4,\(%ecx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd \(%ecx\),%ymm4
[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps \(%ecx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 c9 6b fc 20 vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6b 39 20 vfmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6b 39 20 vfmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6b 39 20 vfmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6b 39 20 vfmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6f fc 20 vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6f 39 20 vfmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6f 39 20 vfmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6f 39 20 vfmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6f 39 20 vfmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7b fc 20 vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7b 39 20 vfnmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7b 39 20 vfnmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7b 39 20 vfnmaddsd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7b 39 20 vfnmaddsd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7f fc 20 vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7f 39 20 vfnmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7f 39 20 vfnmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7f 39 20 vfnmsubsd \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7f 39 20 vfnmsubsd %xmm4,\(%ecx\),%xmm2,%xmm7
+[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0b d4 07 vroundsd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0b 11 07 vroundsd \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0b 11 07 vroundsd \$0x7,\(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%ecx\)
+[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%ecx\)
+[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%ecx\)
+[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%ecx\)
[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca 58 11 vaddss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca 58 11 vaddss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si %xmm4,%ecx
[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si \(%ecx\),%ecx
[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si \(%ecx\),%ecx
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 16 e1 07 vpextrd \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 16 21 07 vpextrd \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 16 21 07 vpextrd \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 17 e1 07 vextractps \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps \$0x7,%xmm4,\(%ecx\)
[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd %ecx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sdl \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sdl \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss %ecx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ssl \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ssl \(%ecx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss \$0x64,\(%ecx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 c9 6a fc 20 vfmaddss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6a 39 20 vfmaddss \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6a 39 20 vfmaddss %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6a 39 20 vfmaddss \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6a 39 20 vfmaddss %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6e fc 20 vfmsubss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6e 39 20 vfmsubss \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6e 39 20 vfmsubss %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6e 39 20 vfmsubss \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6e 39 20 vfmsubss %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7a fc 20 vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7a 39 20 vfnmaddss \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7a 39 20 vfnmaddss %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7a 39 20 vfnmaddss \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7a 39 20 vfnmaddss %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7e fc 20 vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7e 39 20 vfnmsubss \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7e 39 20 vfnmsubss %xmm4,\(%ecx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7e 39 20 vfnmsubss \(%ecx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7e 39 20 vfnmsubss %xmm4,\(%ecx\),%xmm2,%xmm7
+[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 21 d4 07 vinsertps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 21 11 07 vinsertps \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 21 11 07 vinsertps \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0a d4 07 vroundss \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0a 11 07 vroundss \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0a 11 07 vroundss \$0x7,\(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq \(%ecx\),%xmm4
[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq \(%ecx\),%xmm4
[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq \(%ecx\),%xmm4
[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq \(%ecx\),%xmm4
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%ecx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%ecx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%ecx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%ecx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%ecx\)
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%ecx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%ecx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c5 d9 c4 f1 07 vpinsrw \$0x7,%ecx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw \$0x7,\(%ecx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw \$0x7,\(%ecx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 14 e1 07 vpextrb \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb \$0x7,%ecx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb \$0x7,\(%ecx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb \$0x7,\(%ecx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb \$0x7,%xmm4,\(%ecx\)
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb \$0x7,%ecx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb \$0x7,\(%ecx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb \$0x7,\(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx
[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
+[ ]*[a-f0-9]+: c5 c9 72 f4 07 vpslld \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 fc 07 vpslldq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 f4 07 vpsllq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 71 f4 07 vpsllw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 72 e4 07 vpsrad \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 71 e4 07 vpsraw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 72 d4 07 vpsrld \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 dc 07 vpsrldq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 d4 07 vpsrlq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 71 d4 07 vpsrlw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw \$0x7,%xmm4,%ecx
[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd %ymm4,%ecx
[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps %ymm4,%ecx
[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 fe e6 05 34 12 00 00 vcvtdq2pd 0x1234,%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 05 34 12 00 00 vcvtpd2psy 0x1234,%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 3d 34 12 00 00 vpavgb 0x1234,%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 05 34 12 00 00 64 vaeskeygenassist \$0x64,0x1234,%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 05 34 12 00 00 64 vpextrb \$0x64,%xmm0,0x1234
+[ ]*[a-f0-9]+: c4 e3 79 df 05 34 12 00 00 07 vaeskeygenassist \$0x7,0x1234,%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 05 34 12 00 00 07 vpextrb \$0x7,%xmm0,0x1234
[ ]*[a-f0-9]+: c5 fb 2a 3d 34 12 00 00 vcvtsi2sdl 0x1234,%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a 35 34 12 00 00 00 vblendvps %xmm0,0x1234,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 3d 34 12 00 00 64 vpinsrb \$0x64,0x1234,%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 3d 34 12 00 00 07 vpinsrb \$0x7,0x1234,%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 05 34 12 00 00 vmovdqa 0x1234,%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 05 34 12 00 00 vmovdqa %ymm0,0x1234
[ ]*[a-f0-9]+: c4 e2 7d 0d 3d 34 12 00 00 vpermilpd 0x1234,%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 05 34 12 00 00 64 vroundpd \$0x64,0x1234,%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 05 34 12 00 00 64 vextractf128 \$0x64,%ymm0,0x1234
-[ ]*[a-f0-9]+: c4 e3 7d 06 3d 34 12 00 00 64 vperm2f128 \$0x64,0x1234,%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 05 34 12 00 00 07 vroundpd \$0x7,0x1234,%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 05 34 12 00 00 07 vextractf128 \$0x7,%ymm0,0x1234
+[ ]*[a-f0-9]+: c4 e3 7d 06 3d 34 12 00 00 07 vperm2f128 \$0x7,0x1234,%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b 35 34 12 00 00 00 vblendvpd %ymm0,0x1234,%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr 0x0\(%ebp\)
[ ]*[a-f0-9]+: c5 f9 6f 45 00 vmovdqa 0x0\(%ebp\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 45 00 vcvtdq2pd 0x0\(%ebp\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 45 00 vcvtpd2psy 0x0\(%ebp\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 7d 00 vpavgb 0x0\(%ebp\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 45 00 64 vaeskeygenassist \$0x64,0x0\(%ebp\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 45 00 64 vpextrb \$0x64,%xmm0,0x0\(%ebp\)
+[ ]*[a-f0-9]+: c4 e3 79 df 45 00 07 vaeskeygenassist \$0x7,0x0\(%ebp\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 45 00 07 vpextrb \$0x7,%xmm0,0x0\(%ebp\)
[ ]*[a-f0-9]+: c5 fb 2a 7d 00 vcvtsi2sdl 0x0\(%ebp\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a 75 00 00 vblendvps %xmm0,0x0\(%ebp\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 7d 00 64 vpinsrb \$0x64,0x0\(%ebp\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 7d 00 07 vpinsrb \$0x7,0x0\(%ebp\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 45 00 vmovdqa 0x0\(%ebp\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 45 00 vmovdqa %ymm0,0x0\(%ebp\)
[ ]*[a-f0-9]+: c4 e2 7d 0d 7d 00 vpermilpd 0x0\(%ebp\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 45 00 64 vroundpd \$0x64,0x0\(%ebp\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 45 00 64 vextractf128 \$0x64,%ymm0,0x0\(%ebp\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 7d 00 64 vperm2f128 \$0x64,0x0\(%ebp\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 45 00 07 vroundpd \$0x7,0x0\(%ebp\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 45 00 07 vextractf128 \$0x7,%ymm0,0x0\(%ebp\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 7d 00 07 vperm2f128 \$0x7,0x0\(%ebp\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b 75 00 00 vblendvpd %ymm0,0x0\(%ebp\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr 0x99\(%ebp\)
[ ]*[a-f0-9]+: c5 f9 6f 85 99 00 00 00 vmovdqa 0x99\(%ebp\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 85 99 00 00 00 vcvtdq2pd 0x99\(%ebp\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 85 99 00 00 00 vcvtpd2psy 0x99\(%ebp\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 bd 99 00 00 00 vpavgb 0x99\(%ebp\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 85 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%ebp\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 85 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%ebp\)
+[ ]*[a-f0-9]+: c4 e3 79 df 85 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%ebp\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 85 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(%ebp\)
[ ]*[a-f0-9]+: c5 fb 2a bd 99 00 00 00 vcvtsi2sdl 0x99\(%ebp\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a b5 99 00 00 00 00 vblendvps %xmm0,0x99\(%ebp\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 bd 99 00 00 00 64 vpinsrb \$0x64,0x99\(%ebp\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 bd 99 00 00 00 07 vpinsrb \$0x7,0x99\(%ebp\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 85 99 00 00 00 vmovdqa 0x99\(%ebp\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 85 99 00 00 00 vmovdqa %ymm0,0x99\(%ebp\)
[ ]*[a-f0-9]+: c4 e2 7d 0d bd 99 00 00 00 vpermilpd 0x99\(%ebp\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 85 99 00 00 00 64 vroundpd \$0x64,0x99\(%ebp\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 85 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%ebp\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 bd 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%ebp\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 85 99 00 00 00 07 vroundpd \$0x7,0x99\(%ebp\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 85 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(%ebp\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 bd 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%ebp\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b b5 99 00 00 00 00 vblendvpd %ymm0,0x99\(%ebp\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 14 25 99 00 00 00 vldmxcsr 0x99\(,%eiz,1\)
[ ]*[a-f0-9]+: c5 f9 6f 04 25 99 00 00 00 vmovdqa 0x99\(,%eiz,1\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 04 25 99 00 00 00 vcvtdq2pd 0x99\(,%eiz,1\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 04 25 99 00 00 00 vcvtpd2psy 0x99\(,%eiz,1\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 3c 25 99 00 00 00 vpavgb 0x99\(,%eiz,1\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 04 25 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(,%eiz,1\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 04 25 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(,%eiz,1\)
+[ ]*[a-f0-9]+: c4 e3 79 df 04 25 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(,%eiz,1\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 04 25 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(,%eiz,1\)
[ ]*[a-f0-9]+: c5 fb 2a 3c 25 99 00 00 00 vcvtsi2sdl 0x99\(,%eiz,1\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a 34 25 99 00 00 00 00 vblendvps %xmm0,0x99\(,%eiz,1\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 3c 25 99 00 00 00 64 vpinsrb \$0x64,0x99\(,%eiz,1\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 3c 25 99 00 00 00 07 vpinsrb \$0x7,0x99\(,%eiz,1\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 04 25 99 00 00 00 vmovdqa 0x99\(,%eiz,1\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 04 25 99 00 00 00 vmovdqa %ymm0,0x99\(,%eiz,1\)
[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 25 99 00 00 00 vpermilpd 0x99\(,%eiz,1\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 04 25 99 00 00 00 64 vroundpd \$0x64,0x99\(,%eiz,1\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 04 25 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(,%eiz,1\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 3c 25 99 00 00 00 64 vperm2f128 \$0x64,0x99\(,%eiz,1\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 04 25 99 00 00 00 07 vroundpd \$0x7,0x99\(,%eiz,1\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 04 25 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(,%eiz,1\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 3c 25 99 00 00 00 07 vperm2f128 \$0x7,0x99\(,%eiz,1\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b 34 25 99 00 00 00 00 vblendvpd %ymm0,0x99\(,%eiz,1\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 14 65 99 00 00 00 vldmxcsr 0x99\(,%eiz,2\)
[ ]*[a-f0-9]+: c5 f9 6f 04 65 99 00 00 00 vmovdqa 0x99\(,%eiz,2\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 04 65 99 00 00 00 vcvtdq2pd 0x99\(,%eiz,2\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 04 65 99 00 00 00 vcvtpd2psy 0x99\(,%eiz,2\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 3c 65 99 00 00 00 vpavgb 0x99\(,%eiz,2\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 04 65 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(,%eiz,2\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 04 65 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(,%eiz,2\)
+[ ]*[a-f0-9]+: c4 e3 79 df 04 65 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(,%eiz,2\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 04 65 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(,%eiz,2\)
[ ]*[a-f0-9]+: c5 fb 2a 3c 65 99 00 00 00 vcvtsi2sdl 0x99\(,%eiz,2\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a 34 65 99 00 00 00 00 vblendvps %xmm0,0x99\(,%eiz,2\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 3c 65 99 00 00 00 64 vpinsrb \$0x64,0x99\(,%eiz,2\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 3c 65 99 00 00 00 07 vpinsrb \$0x7,0x99\(,%eiz,2\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 04 65 99 00 00 00 vmovdqa 0x99\(,%eiz,2\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 04 65 99 00 00 00 vmovdqa %ymm0,0x99\(,%eiz,2\)
[ ]*[a-f0-9]+: c4 e2 7d 0d 3c 65 99 00 00 00 vpermilpd 0x99\(,%eiz,2\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 04 65 99 00 00 00 64 vroundpd \$0x64,0x99\(,%eiz,2\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 04 65 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(,%eiz,2\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 3c 65 99 00 00 00 64 vperm2f128 \$0x64,0x99\(,%eiz,2\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 04 65 99 00 00 00 07 vroundpd \$0x7,0x99\(,%eiz,2\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 04 65 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(,%eiz,2\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 3c 65 99 00 00 00 07 vperm2f128 \$0x7,0x99\(,%eiz,2\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b 34 65 99 00 00 00 00 vblendvpd %ymm0,0x99\(,%eiz,2\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 94 20 99 00 00 00 vldmxcsr 0x99\(%eax,%eiz,1\)
[ ]*[a-f0-9]+: c5 f9 6f 84 20 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,1\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 84 20 99 00 00 00 vcvtdq2pd 0x99\(%eax,%eiz,1\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 84 20 99 00 00 00 vcvtpd2psy 0x99\(%eax,%eiz,1\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 bc 20 99 00 00 00 vpavgb 0x99\(%eax,%eiz,1\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 84 20 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%eax,%eiz,1\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 84 20 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%eax,%eiz,1\)
+[ ]*[a-f0-9]+: c4 e3 79 df 84 20 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%eax,%eiz,1\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 84 20 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(%eax,%eiz,1\)
[ ]*[a-f0-9]+: c5 fb 2a bc 20 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%eiz,1\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a b4 20 99 00 00 00 00 vblendvps %xmm0,0x99\(%eax,%eiz,1\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 20 99 00 00 00 64 vpinsrb \$0x64,0x99\(%eax,%eiz,1\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 20 99 00 00 00 07 vpinsrb \$0x7,0x99\(%eax,%eiz,1\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 84 20 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,1\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 84 20 99 00 00 00 vmovdqa %ymm0,0x99\(%eax,%eiz,1\)
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 20 99 00 00 00 vpermilpd 0x99\(%eax,%eiz,1\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 20 99 00 00 00 64 vroundpd \$0x64,0x99\(%eax,%eiz,1\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 20 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%eax,%eiz,1\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 20 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%eax,%eiz,1\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 20 99 00 00 00 07 vroundpd \$0x7,0x99\(%eax,%eiz,1\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 20 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(%eax,%eiz,1\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 20 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%eax,%eiz,1\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 20 99 00 00 00 00 vblendvpd %ymm0,0x99\(%eax,%eiz,1\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 94 60 99 00 00 00 vldmxcsr 0x99\(%eax,%eiz,2\)
[ ]*[a-f0-9]+: c5 f9 6f 84 60 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,2\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 84 60 99 00 00 00 vcvtdq2pd 0x99\(%eax,%eiz,2\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 84 60 99 00 00 00 vcvtpd2psy 0x99\(%eax,%eiz,2\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 bc 60 99 00 00 00 vpavgb 0x99\(%eax,%eiz,2\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 84 60 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%eax,%eiz,2\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 84 60 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%eax,%eiz,2\)
+[ ]*[a-f0-9]+: c4 e3 79 df 84 60 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%eax,%eiz,2\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 84 60 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(%eax,%eiz,2\)
[ ]*[a-f0-9]+: c5 fb 2a bc 60 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%eiz,2\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a b4 60 99 00 00 00 00 vblendvps %xmm0,0x99\(%eax,%eiz,2\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 60 99 00 00 00 64 vpinsrb \$0x64,0x99\(%eax,%eiz,2\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 60 99 00 00 00 07 vpinsrb \$0x7,0x99\(%eax,%eiz,2\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 84 60 99 00 00 00 vmovdqa 0x99\(%eax,%eiz,2\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 84 60 99 00 00 00 vmovdqa %ymm0,0x99\(%eax,%eiz,2\)
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 60 99 00 00 00 vpermilpd 0x99\(%eax,%eiz,2\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 60 99 00 00 00 64 vroundpd \$0x64,0x99\(%eax,%eiz,2\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 60 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%eax,%eiz,2\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 60 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%eax,%eiz,2\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 60 99 00 00 00 07 vroundpd \$0x7,0x99\(%eax,%eiz,2\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 60 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(%eax,%eiz,2\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 60 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%eax,%eiz,2\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 60 99 00 00 00 00 vblendvpd %ymm0,0x99\(%eax,%eiz,2\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 94 98 99 00 00 00 vldmxcsr 0x99\(%eax,%ebx,4\)
[ ]*[a-f0-9]+: c5 f9 6f 84 98 99 00 00 00 vmovdqa 0x99\(%eax,%ebx,4\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 84 98 99 00 00 00 vcvtdq2pd 0x99\(%eax,%ebx,4\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 84 98 99 00 00 00 vcvtpd2psy 0x99\(%eax,%ebx,4\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 bc 98 99 00 00 00 vpavgb 0x99\(%eax,%ebx,4\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 84 98 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%eax,%ebx,4\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 84 98 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%eax,%ebx,4\)
+[ ]*[a-f0-9]+: c4 e3 79 df 84 98 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%eax,%ebx,4\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 84 98 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(%eax,%ebx,4\)
[ ]*[a-f0-9]+: c5 fb 2a bc 98 99 00 00 00 vcvtsi2sdl 0x99\(%eax,%ebx,4\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a b4 98 99 00 00 00 00 vblendvps %xmm0,0x99\(%eax,%ebx,4\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 98 99 00 00 00 64 vpinsrb \$0x64,0x99\(%eax,%ebx,4\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 98 99 00 00 00 07 vpinsrb \$0x7,0x99\(%eax,%ebx,4\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 84 98 99 00 00 00 vmovdqa 0x99\(%eax,%ebx,4\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 84 98 99 00 00 00 vmovdqa %ymm0,0x99\(%eax,%ebx,4\)
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 98 99 00 00 00 vpermilpd 0x99\(%eax,%ebx,4\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 98 99 00 00 00 64 vroundpd \$0x64,0x99\(%eax,%ebx,4\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 98 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%eax,%ebx,4\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 98 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%eax,%ebx,4\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 98 99 00 00 00 07 vroundpd \$0x7,0x99\(%eax,%ebx,4\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 98 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(%eax,%ebx,4\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 98 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%eax,%ebx,4\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 98 99 00 00 00 00 vblendvpd %ymm0,0x99\(%eax,%ebx,4\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 94 cc 99 00 00 00 vldmxcsr 0x99\(%esp,%ecx,8\)
[ ]*[a-f0-9]+: c5 f9 6f 84 cc 99 00 00 00 vmovdqa 0x99\(%esp,%ecx,8\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 84 cc 99 00 00 00 vcvtdq2pd 0x99\(%esp,%ecx,8\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 84 cc 99 00 00 00 vcvtpd2psy 0x99\(%esp,%ecx,8\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 bc cc 99 00 00 00 vpavgb 0x99\(%esp,%ecx,8\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 84 cc 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%esp,%ecx,8\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 84 cc 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%esp,%ecx,8\)
+[ ]*[a-f0-9]+: c4 e3 79 df 84 cc 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%esp,%ecx,8\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 84 cc 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(%esp,%ecx,8\)
[ ]*[a-f0-9]+: c5 fb 2a bc cc 99 00 00 00 vcvtsi2sdl 0x99\(%esp,%ecx,8\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a b4 cc 99 00 00 00 00 vblendvps %xmm0,0x99\(%esp,%ecx,8\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 bc cc 99 00 00 00 64 vpinsrb \$0x64,0x99\(%esp,%ecx,8\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 bc cc 99 00 00 00 07 vpinsrb \$0x7,0x99\(%esp,%ecx,8\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 84 cc 99 00 00 00 vmovdqa 0x99\(%esp,%ecx,8\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 84 cc 99 00 00 00 vmovdqa %ymm0,0x99\(%esp,%ecx,8\)
[ ]*[a-f0-9]+: c4 e2 7d 0d bc cc 99 00 00 00 vpermilpd 0x99\(%esp,%ecx,8\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 cc 99 00 00 00 64 vroundpd \$0x64,0x99\(%esp,%ecx,8\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 cc 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%esp,%ecx,8\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc cc 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%esp,%ecx,8\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 cc 99 00 00 00 07 vroundpd \$0x7,0x99\(%esp,%ecx,8\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 cc 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(%esp,%ecx,8\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc cc 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%esp,%ecx,8\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 cc 99 00 00 00 00 vblendvpd %ymm0,0x99\(%esp,%ecx,8\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f8 ae 94 15 99 00 00 00 vldmxcsr 0x99\(%ebp,%edx,1\)
[ ]*[a-f0-9]+: c5 f9 6f 84 15 99 00 00 00 vmovdqa 0x99\(%ebp,%edx,1\),%xmm0
[ ]*[a-f0-9]+: c5 fe e6 84 15 99 00 00 00 vcvtdq2pd 0x99\(%ebp,%edx,1\),%ymm0
[ ]*[a-f0-9]+: c5 fd 5a 84 15 99 00 00 00 vcvtpd2psy 0x99\(%ebp,%edx,1\),%xmm0
[ ]*[a-f0-9]+: c5 f9 e0 bc 15 99 00 00 00 vpavgb 0x99\(%ebp,%edx,1\),%xmm0,%xmm7
-[ ]*[a-f0-9]+: c4 e3 79 df 84 15 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%ebp,%edx,1\),%xmm0
-[ ]*[a-f0-9]+: c4 e3 79 14 84 15 99 00 00 00 64 vpextrb \$0x64,%xmm0,0x99\(%ebp,%edx,1\)
+[ ]*[a-f0-9]+: c4 e3 79 df 84 15 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%ebp,%edx,1\),%xmm0
+[ ]*[a-f0-9]+: c4 e3 79 14 84 15 99 00 00 00 07 vpextrb \$0x7,%xmm0,0x99\(%ebp,%edx,1\)
[ ]*[a-f0-9]+: c5 fb 2a bc 15 99 00 00 00 vcvtsi2sdl 0x99\(%ebp,%edx,1\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c4 e3 59 4a b4 15 99 00 00 00 00 vblendvps %xmm0,0x99\(%ebp,%edx,1\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 20 bc 15 99 00 00 00 64 vpinsrb \$0x64,0x99\(%ebp,%edx,1\),%xmm0,%xmm7
+[ ]*[a-f0-9]+: c4 e3 79 20 bc 15 99 00 00 00 07 vpinsrb \$0x7,0x99\(%ebp,%edx,1\),%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fd 6f 84 15 99 00 00 00 vmovdqa 0x99\(%ebp,%edx,1\),%ymm0
[ ]*[a-f0-9]+: c5 fd 7f 84 15 99 00 00 00 vmovdqa %ymm0,0x99\(%ebp,%edx,1\)
[ ]*[a-f0-9]+: c4 e2 7d 0d bc 15 99 00 00 00 vpermilpd 0x99\(%ebp,%edx,1\),%ymm0,%ymm7
-[ ]*[a-f0-9]+: c4 e3 7d 09 84 15 99 00 00 00 64 vroundpd \$0x64,0x99\(%ebp,%edx,1\),%ymm0
-[ ]*[a-f0-9]+: c4 e3 7d 19 84 15 99 00 00 00 64 vextractf128 \$0x64,%ymm0,0x99\(%ebp,%edx,1\)
-[ ]*[a-f0-9]+: c4 e3 7d 06 bc 15 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%ebp,%edx,1\),%ymm0,%ymm7
+[ ]*[a-f0-9]+: c4 e3 7d 09 84 15 99 00 00 00 07 vroundpd \$0x7,0x99\(%ebp,%edx,1\),%ymm0
+[ ]*[a-f0-9]+: c4 e3 7d 19 84 15 99 00 00 00 07 vextractf128 \$0x7,%ymm0,0x99\(%ebp,%edx,1\)
+[ ]*[a-f0-9]+: c4 e3 7d 06 bc 15 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%ebp,%edx,1\),%ymm0,%ymm7
[ ]*[a-f0-9]+: c4 e3 5d 4b b4 15 99 00 00 00 00 vblendvpd %ymm0,0x99\(%ebp,%edx,1\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c5 f9 50 c0 vmovmskpd %xmm0,%eax
-[ ]*[a-f0-9]+: c5 c1 72 f0 64 vpslld \$0x64,%xmm0,%xmm7
+[ ]*[a-f0-9]+: c5 c1 72 f0 07 vpslld \$0x7,%xmm0,%xmm7
[ ]*[a-f0-9]+: c5 fc 50 c0 vmovmskps %ymm0,%eax
#pass
vmaskmovps %ymm4,%ymm6,(%ecx)
# Tests for op imm8, ymm/mem256, ymm
- vpermilpd $100,%ymm6,%ymm2
- vpermilpd $100,(%ecx),%ymm6
- vpermilps $100,%ymm6,%ymm2
- vpermilps $100,(%ecx),%ymm6
- vroundpd $100,%ymm6,%ymm2
- vroundpd $100,(%ecx),%ymm6
- vroundps $100,%ymm6,%ymm2
- vroundps $100,(%ecx),%ymm6
+ vpermilpd $7,%ymm6,%ymm2
+ vpermilpd $7,(%ecx),%ymm6
+ vpermilps $7,%ymm6,%ymm2
+ vpermilps $7,(%ecx),%ymm6
+ vroundpd $7,%ymm6,%ymm2
+ vroundpd $7,(%ecx),%ymm6
+ vroundps $7,%ymm6,%ymm2
+ vroundps $7,(%ecx),%ymm6
# Tests for op ymm/mem256, ymm, ymm
vaddpd %ymm4,%ymm6,%ymm2
vcvttpd2dqy (%ecx),%xmm4
# Tests for op ymm/mem256, ymm
- vcvtdq2ps %ymm4,%ymm4
+ vcvtdq2ps %ymm4,%ymm6
vcvtdq2ps (%ecx),%ymm4
- vcvtps2dq %ymm4,%ymm4
+ vcvtps2dq %ymm4,%ymm6
vcvtps2dq (%ecx),%ymm4
- vcvttps2dq %ymm4,%ymm4
+ vcvttps2dq %ymm4,%ymm6
vcvttps2dq (%ecx),%ymm4
- vmovapd %ymm4,%ymm4
+ vmovapd %ymm4,%ymm6
vmovapd (%ecx),%ymm4
- vmovaps %ymm4,%ymm4
+ vmovaps %ymm4,%ymm6
vmovaps (%ecx),%ymm4
- vmovdqa %ymm4,%ymm4
+ vmovdqa %ymm4,%ymm6
vmovdqa (%ecx),%ymm4
- vmovdqu %ymm4,%ymm4
+ vmovdqu %ymm4,%ymm6
vmovdqu (%ecx),%ymm4
- vmovddup %ymm4,%ymm4
+ vmovddup %ymm4,%ymm6
vmovddup (%ecx),%ymm4
- vmovshdup %ymm4,%ymm4
+ vmovshdup %ymm4,%ymm6
vmovshdup (%ecx),%ymm4
- vmovsldup %ymm4,%ymm4
+ vmovsldup %ymm4,%ymm6
vmovsldup (%ecx),%ymm4
- vmovupd %ymm4,%ymm4
+ vmovupd %ymm4,%ymm6
vmovupd (%ecx),%ymm4
- vmovups %ymm4,%ymm4
+ vmovups %ymm4,%ymm6
vmovups (%ecx),%ymm4
- vptest %ymm4,%ymm4
+ vptest %ymm4,%ymm6
vptest (%ecx),%ymm4
- vrcpps %ymm4,%ymm4
+ vrcpps %ymm4,%ymm6
vrcpps (%ecx),%ymm4
- vrsqrtps %ymm4,%ymm4
+ vrsqrtps %ymm4,%ymm6
vrsqrtps (%ecx),%ymm4
- vsqrtpd %ymm4,%ymm4
+ vsqrtpd %ymm4,%ymm6
vsqrtpd (%ecx),%ymm4
- vsqrtps %ymm4,%ymm4
+ vsqrtps %ymm4,%ymm6
vsqrtps (%ecx),%ymm4
- vtestpd %ymm4,%ymm4
+ vtestpd %ymm4,%ymm6
vtestpd (%ecx),%ymm4
- vtestps %ymm4,%ymm4
+ vtestps %ymm4,%ymm6
vtestps (%ecx),%ymm4
# Tests for op mem256, ymm
vlddqu (%ecx),%ymm4
# Tests for op imm8, ymm/mem256, ymm, ymm
- vblendpd $100,%ymm4,%ymm6,%ymm2
- vblendpd $100,(%ecx),%ymm6,%ymm2
- vblendps $100,%ymm4,%ymm6,%ymm2
- vblendps $100,(%ecx),%ymm6,%ymm2
- vcmppd $100,%ymm4,%ymm6,%ymm2
- vcmppd $100,(%ecx),%ymm6,%ymm2
- vcmpps $100,%ymm4,%ymm6,%ymm2
- vcmpps $100,(%ecx),%ymm6,%ymm2
- vdpps $100,%ymm4,%ymm6,%ymm2
- vdpps $100,(%ecx),%ymm6,%ymm2
- vperm2f128 $100,%ymm4,%ymm6,%ymm2
- vperm2f128 $100,(%ecx),%ymm6,%ymm2
- vshufpd $100,%ymm4,%ymm6,%ymm2
- vshufpd $100,(%ecx),%ymm6,%ymm2
- vshufps $100,%ymm4,%ymm6,%ymm2
- vshufps $100,(%ecx),%ymm6,%ymm2
+ vblendpd $7,%ymm4,%ymm6,%ymm2
+ vblendpd $7,(%ecx),%ymm6,%ymm2
+ vblendps $7,%ymm4,%ymm6,%ymm2
+ vblendps $7,(%ecx),%ymm6,%ymm2
+ vcmppd $7,%ymm4,%ymm6,%ymm2
+ vcmppd $7,(%ecx),%ymm6,%ymm2
+ vcmpps $7,%ymm4,%ymm6,%ymm2
+ vcmpps $7,(%ecx),%ymm6,%ymm2
+ vdpps $7,%ymm4,%ymm6,%ymm2
+ vdpps $7,(%ecx),%ymm6,%ymm2
+ vperm2f128 $7,%ymm4,%ymm6,%ymm2
+ vperm2f128 $7,(%ecx),%ymm6,%ymm2
+ vshufpd $7,%ymm4,%ymm6,%ymm2
+ vshufpd $7,(%ecx),%ymm6,%ymm2
+ vshufps $7,%ymm4,%ymm6,%ymm2
+ vshufps $7,(%ecx),%ymm6,%ymm2
# Tests for op ymm, ymm/mem256, ymm, ymm
vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
vblendvps %ymm4,%ymm6,%ymm2,%ymm7
vblendvps %ymm4,(%ecx),%ymm2,%ymm7
-# Tests for op ymm/mem256, ymm, ymm, ymm
-# Tests for op ymm, ymm/mem256, ymm, ymm
- vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
- vfmaddpd (%ecx),%ymm6,%ymm2,%ymm7
- vfmaddps %ymm4,%ymm6,%ymm2,%ymm7
- vfmaddps (%ecx),%ymm6,%ymm2,%ymm7
- vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7
- vfmaddsubpd (%ecx),%ymm6,%ymm2,%ymm7
- vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7
- vfmaddsubps (%ecx),%ymm6,%ymm2,%ymm7
- vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7
- vfmsubaddpd (%ecx),%ymm6,%ymm2,%ymm7
- vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7
- vfmsubaddps (%ecx),%ymm6,%ymm2,%ymm7
- vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7
- vfmsubpd (%ecx),%ymm6,%ymm2,%ymm7
- vfmsubps %ymm4,%ymm6,%ymm2,%ymm7
- vfmsubps (%ecx),%ymm6,%ymm2,%ymm7
- vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7
- vfnmaddpd (%ecx),%ymm6,%ymm2,%ymm7
- vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7
- vfnmaddps (%ecx),%ymm6,%ymm2,%ymm7
- vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7
- vfnmsubpd (%ecx),%ymm6,%ymm2,%ymm7
- vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7
- vfnmsubps (%ecx),%ymm6,%ymm2,%ymm7
- vpermilmo2pd %ymm4,%ymm6,%ymm2,%ymm7
- vpermilmo2pd (%ecx),%ymm6,%ymm2,%ymm7
- vpermilmz2pd %ymm4,%ymm6,%ymm2,%ymm7
- vpermilmz2pd (%ecx),%ymm6,%ymm2,%ymm7
- vpermiltd2pd %ymm4,%ymm6,%ymm2,%ymm7
- vpermiltd2pd (%ecx),%ymm6,%ymm2,%ymm7
- vpermilmo2ps %ymm4,%ymm6,%ymm2,%ymm7
- vpermilmo2ps (%ecx),%ymm6,%ymm2,%ymm7
- vpermilmz2ps %ymm4,%ymm6,%ymm2,%ymm7
- vpermilmz2ps (%ecx),%ymm6,%ymm2,%ymm7
- vpermiltd2ps %ymm4,%ymm6,%ymm2,%ymm7
- vpermiltd2ps (%ecx),%ymm6,%ymm2,%ymm7
-
-# Tests for op imm4, ymm/mem256, ymm, ymm, ymm
-# Tests for op imm4, ymm, ymm/mem256, ymm, ymm
- vpermil2pd $10,%ymm4,%ymm6,%ymm2,%ymm7
- vpermil2pd $10,(%ecx),%ymm6,%ymm2,%ymm7
- vpermil2ps $10,%ymm4,%ymm6,%ymm2,%ymm7
- vpermil2ps $10,(%ecx),%ymm6,%ymm2,%ymm7
-
# Tests for op imm8, xmm/mem128, ymm, ymm
- vinsertf128 $100,%xmm4,%ymm4,%ymm6
- vinsertf128 $100,(%ecx),%ymm4,%ymm6
+ vinsertf128 $7,%xmm4,%ymm4,%ymm6
+ vinsertf128 $7,(%ecx),%ymm4,%ymm6
# Tests for op imm8, ymm, xmm/mem128
- vextractf128 $100,%ymm4,%xmm4
- vextractf128 $100,%ymm4,(%ecx)
+ vextractf128 $7,%ymm4,%xmm4
+ vextractf128 $7,%ymm4,(%ecx)
# Tests for op mem128, ymm
vbroadcastf128 (%ecx),%ymm4
vmaskmovpd (%ecx),%xmm4,%xmm6
# Tests for op imm8, xmm/mem128, xmm
- vaeskeygenassist $100,%xmm4,%xmm6
- vaeskeygenassist $100,(%ecx),%xmm6
- vpcmpestri $100,%xmm4,%xmm6
- vpcmpestri $100,(%ecx),%xmm6
- vpcmpestrm $100,%xmm4,%xmm6
- vpcmpestrm $100,(%ecx),%xmm6
- vpcmpistri $100,%xmm4,%xmm6
- vpcmpistri $100,(%ecx),%xmm6
- vpcmpistrm $100,%xmm4,%xmm6
- vpcmpistrm $100,(%ecx),%xmm6
- vpermilpd $100,%xmm4,%xmm6
- vpermilpd $100,(%ecx),%xmm6
- vpermilps $100,%xmm4,%xmm6
- vpermilps $100,(%ecx),%xmm6
- vpshufd $100,%xmm4,%xmm6
- vpshufd $100,(%ecx),%xmm6
- vpshufhw $100,%xmm4,%xmm6
- vpshufhw $100,(%ecx),%xmm6
- vpshuflw $100,%xmm4,%xmm6
- vpshuflw $100,(%ecx),%xmm6
- vroundpd $100,%xmm4,%xmm6
- vroundpd $100,(%ecx),%xmm6
- vroundps $100,%xmm4,%xmm6
- vroundps $100,(%ecx),%xmm6
+ vaeskeygenassist $7,%xmm4,%xmm6
+ vaeskeygenassist $7,(%ecx),%xmm6
+ vpcmpestri $7,%xmm4,%xmm6
+ vpcmpestri $7,(%ecx),%xmm6
+ vpcmpestrm $7,%xmm4,%xmm6
+ vpcmpestrm $7,(%ecx),%xmm6
+ vpcmpistri $7,%xmm4,%xmm6
+ vpcmpistri $7,(%ecx),%xmm6
+ vpcmpistrm $7,%xmm4,%xmm6
+ vpcmpistrm $7,(%ecx),%xmm6
+ vpermilpd $7,%xmm4,%xmm6
+ vpermilpd $7,(%ecx),%xmm6
+ vpermilps $7,%xmm4,%xmm6
+ vpermilps $7,(%ecx),%xmm6
+ vpshufd $7,%xmm4,%xmm6
+ vpshufd $7,(%ecx),%xmm6
+ vpshufhw $7,%xmm4,%xmm6
+ vpshufhw $7,(%ecx),%xmm6
+ vpshuflw $7,%xmm4,%xmm6
+ vpshuflw $7,(%ecx),%xmm6
+ vroundpd $7,%xmm4,%xmm6
+ vroundpd $7,(%ecx),%xmm6
+ vroundps $7,%xmm4,%xmm6
+ vroundps $7,(%ecx),%xmm6
# Tests for op xmm, xmm, mem128
vmaskmovps %xmm4,%xmm6,(%ecx)
vmaskmovpd %xmm4,%xmm6,(%ecx)
# Tests for op imm8, xmm/mem128, xmm, xmm
- vblendpd $100,%xmm4,%xmm6,%xmm2
- vblendpd $100,(%ecx),%xmm6,%xmm2
- vblendps $100,%xmm4,%xmm6,%xmm2
- vblendps $100,(%ecx),%xmm6,%xmm2
- vcmppd $100,%xmm4,%xmm6,%xmm2
- vcmppd $100,(%ecx),%xmm6,%xmm2
- vcmpps $100,%xmm4,%xmm6,%xmm2
- vcmpps $100,(%ecx),%xmm6,%xmm2
- vdppd $100,%xmm4,%xmm6,%xmm2
- vdppd $100,(%ecx),%xmm6,%xmm2
- vdpps $100,%xmm4,%xmm6,%xmm2
- vdpps $100,(%ecx),%xmm6,%xmm2
- vmpsadbw $100,%xmm4,%xmm6,%xmm2
- vmpsadbw $100,(%ecx),%xmm6,%xmm2
- vpalignr $100,%xmm4,%xmm6,%xmm2
- vpalignr $100,(%ecx),%xmm6,%xmm2
- vpblendw $100,%xmm4,%xmm6,%xmm2
- vpblendw $100,(%ecx),%xmm6,%xmm2
- vshufpd $100,%xmm4,%xmm6,%xmm2
- vshufpd $100,(%ecx),%xmm6,%xmm2
- vshufps $100,%xmm4,%xmm6,%xmm2
- vshufps $100,(%ecx),%xmm6,%xmm2
+ vblendpd $7,%xmm4,%xmm6,%xmm2
+ vblendpd $7,(%ecx),%xmm6,%xmm2
+ vblendps $7,%xmm4,%xmm6,%xmm2
+ vblendps $7,(%ecx),%xmm6,%xmm2
+ vcmppd $7,%xmm4,%xmm6,%xmm2
+ vcmppd $7,(%ecx),%xmm6,%xmm2
+ vcmpps $7,%xmm4,%xmm6,%xmm2
+ vcmpps $7,(%ecx),%xmm6,%xmm2
+ vdppd $7,%xmm4,%xmm6,%xmm2
+ vdppd $7,(%ecx),%xmm6,%xmm2
+ vdpps $7,%xmm4,%xmm6,%xmm2
+ vdpps $7,(%ecx),%xmm6,%xmm2
+ vmpsadbw $7,%xmm4,%xmm6,%xmm2
+ vmpsadbw $7,(%ecx),%xmm6,%xmm2
+ vpalignr $7,%xmm4,%xmm6,%xmm2
+ vpalignr $7,(%ecx),%xmm6,%xmm2
+ vpblendw $7,%xmm4,%xmm6,%xmm2
+ vpblendw $7,(%ecx),%xmm6,%xmm2
+ vshufpd $7,%xmm4,%xmm6,%xmm2
+ vshufpd $7,(%ecx),%xmm6,%xmm2
+ vshufps $7,%xmm4,%xmm6,%xmm2
+ vshufps $7,(%ecx),%xmm6,%xmm2
# Tests for op xmm, xmm/mem128, xmm, xmm
vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
vpblendvb %xmm4,%xmm6,%xmm2,%xmm7
vpblendvb %xmm4,(%ecx),%xmm2,%xmm7
-# Tests for op xmm/mem128, xmm, xmm, xmm
-# Tests for op xmm, xmm/mem128, xmm, xmm
- vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7
- vfmaddpd (%ecx),%xmm6,%xmm2,%xmm7
- vfmaddpd %xmm4,(%ecx),%xmm2,%xmm7
- vfmaddps %xmm4,%xmm6,%xmm2,%xmm7
- vfmaddps (%ecx),%xmm6,%xmm2,%xmm7
- vfmaddps %xmm4,(%ecx),%xmm2,%xmm7
- vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7
- vfmaddsubpd (%ecx),%xmm6,%xmm2,%xmm7
- vfmaddsubpd %xmm4,(%ecx),%xmm2,%xmm7
- vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7
- vfmaddsubps (%ecx),%xmm6,%xmm2,%xmm7
- vfmaddsubps %xmm4,(%ecx),%xmm2,%xmm7
- vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7
- vfmsubaddpd (%ecx),%xmm6,%xmm2,%xmm7
- vfmsubaddpd %xmm4,(%ecx),%xmm2,%xmm7
- vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7
- vfmsubaddps (%ecx),%xmm6,%xmm2,%xmm7
- vfmsubaddps %xmm4,(%ecx),%xmm2,%xmm7
- vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7
- vfmsubpd (%ecx),%xmm6,%xmm2,%xmm7
- vfmsubpd %xmm4,(%ecx),%xmm2,%xmm7
- vfmsubps %xmm4,%xmm6,%xmm2,%xmm7
- vfmsubps (%ecx),%xmm6,%xmm2,%xmm7
- vfmsubps %xmm4,(%ecx),%xmm2,%xmm7
- vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7
- vfnmaddpd (%ecx),%xmm6,%xmm2,%xmm7
- vfnmaddpd %xmm4,(%ecx),%xmm2,%xmm7
- vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7
- vfnmaddps (%ecx),%xmm6,%xmm2,%xmm7
- vfnmaddps %xmm4,(%ecx),%xmm2,%xmm7
- vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7
- vfnmsubpd (%ecx),%xmm6,%xmm2,%xmm7
- vfnmsubpd %xmm4,(%ecx),%xmm2,%xmm7
- vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7
- vfnmsubps (%ecx),%xmm6,%xmm2,%xmm7
- vfnmsubps %xmm4,(%ecx),%xmm2,%xmm7
- vpermilmo2pd %xmm4,%xmm6,%xmm2,%xmm7
- vpermilmo2pd (%ecx),%xmm6,%xmm2,%xmm7
- vpermilmo2pd %xmm4,(%ecx),%xmm2,%xmm7
- vpermilmz2pd %xmm4,%xmm6,%xmm2,%xmm7
- vpermilmz2pd (%ecx),%xmm6,%xmm2,%xmm7
- vpermilmz2pd %xmm4,(%ecx),%xmm2,%xmm7
- vpermiltd2pd %xmm4,%xmm6,%xmm2,%xmm7
- vpermiltd2pd (%ecx),%xmm6,%xmm2,%xmm7
- vpermiltd2pd %xmm4,(%ecx),%xmm2,%xmm7
- vpermilmo2ps %xmm4,%xmm6,%xmm2,%xmm7
- vpermilmo2ps (%ecx),%xmm6,%xmm2,%xmm7
- vpermilmo2ps %xmm4,(%ecx),%xmm2,%xmm7
- vpermilmz2ps %xmm4,%xmm6,%xmm2,%xmm7
- vpermilmz2ps (%ecx),%xmm6,%xmm2,%xmm7
- vpermilmz2ps %xmm4,(%ecx),%xmm2,%xmm7
- vpermiltd2ps %xmm4,%xmm6,%xmm2,%xmm7
- vpermiltd2ps (%ecx),%xmm6,%xmm2,%xmm7
- vpermiltd2ps %xmm4,(%ecx),%xmm2,%xmm7
-
-# Tests for op imm4, xmm/mem128, xmm, xmm, xmm
-# Tests for op imm4, xmm, xmm/mem128, xmm, xmm
- vpermil2pd $10,%xmm4,%xmm6,%xmm2,%xmm7
- vpermil2pd $10,(%ecx),%xmm6,%xmm2,%xmm7
- vpermil2pd $10,%xmm4,(%ecx),%xmm2,%xmm7
- vpermil2ps $10,%xmm4,%xmm6,%xmm2,%xmm7
- vpermil2ps $10,(%ecx),%xmm6,%xmm2,%xmm7
- vpermil2ps $10,%xmm4,(%ecx),%xmm2,%xmm7
-
# Tests for op mem64, ymm
vbroadcastsd (%ecx),%ymm4
vmovhps (%ecx),%xmm4,%xmm6
# Tests for op imm8, xmm/mem64, xmm, xmm
- vcmpsd $100,%xmm4,%xmm6,%xmm2
- vcmpsd $100,(%ecx),%xmm6,%xmm2
- vroundsd $100,%xmm4,%xmm6,%xmm2
- vroundsd $100,(%ecx),%xmm6,%xmm2
-
-# Tests for op xmm/mem64, xmm, xmm, xmm
-# Tests for op xmm, xmm/mem64, xmm, xmm
- vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7
- vfmaddsd (%ecx),%xmm6,%xmm2,%xmm7
- vfmaddsd %xmm4,(%ecx),%xmm2,%xmm7
- vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7
- vfmsubsd (%ecx),%xmm6,%xmm2,%xmm7
- vfmsubsd %xmm4,(%ecx),%xmm2,%xmm7
- vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7
- vfnmaddsd (%ecx),%xmm6,%xmm2,%xmm7
- vfnmaddsd %xmm4,(%ecx),%xmm2,%xmm7
- vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7
- vfnmsubsd (%ecx),%xmm6,%xmm2,%xmm7
- vfnmsubsd %xmm4,(%ecx),%xmm2,%xmm7
+ vcmpsd $7,%xmm4,%xmm6,%xmm2
+ vcmpsd $7,(%ecx),%xmm6,%xmm2
+ vroundsd $7,%xmm4,%xmm6,%xmm2
+ vroundsd $7,(%ecx),%xmm6,%xmm2
# Tests for op xmm/mem64, xmm, xmm
vaddsd %xmm4,%xmm6,%xmm2
vcmptrue_ussd %xmm4,%xmm6,%xmm2
vcmptrue_ussd (%ecx),%xmm6,%xmm2
+# Tests for op mem64
+ vldmxcsr (%ecx)
+ vstmxcsr (%ecx)
+
# Tests for op xmm/mem32, xmm, xmm
vaddss %xmm4,%xmm6,%xmm2
vaddss (%ecx),%xmm6,%xmm2
vcvttss2si (%ecx),%ecx
# Tests for op imm8, xmm, regq/mem32
- vextractps $100,%xmm4,(%ecx)
+ vextractps $7,%xmm4,(%ecx)
+
# Tests for op imm8, xmm, regl/mem32
- vpextrd $100,%xmm4,%ecx
- vpextrd $100,%xmm4,(%ecx)
- vextractps $100,%xmm4,%ecx
- vextractps $100,%xmm4,(%ecx)
+ vpextrd $7,%xmm4,%ecx
+ vpextrd $7,%xmm4,(%ecx)
+ vextractps $7,%xmm4,%ecx
+ vextractps $7,%xmm4,(%ecx)
# Tests for op regl/mem32, xmm, xmm
vcvtsi2sd %ecx,%xmm4,%xmm6
vcvtsi2ss (%ecx),%xmm4,%xmm6
# Tests for op imm8, xmm/mem32, xmm, xmm
- vcmpss $100,%xmm4,%xmm6,%xmm2
- vcmpss $100,(%ecx),%xmm6,%xmm2
- vinsertps $100,%xmm4,%xmm6,%xmm2
- vinsertps $100,(%ecx),%xmm6,%xmm2
- vroundss $100,%xmm4,%xmm6,%xmm2
- vroundss $100,(%ecx),%xmm6,%xmm2
-
-# Tests for op xmm/mem32, xmm, xmm, xmm
-# Tests for op xmm, xmm/mem32, xmm, xmm
- vfmaddss %xmm4,%xmm6,%xmm2,%xmm7
- vfmaddss (%ecx),%xmm6,%xmm2,%xmm7
- vfmaddss %xmm4,(%ecx),%xmm2,%xmm7
- vfmsubss %xmm4,%xmm6,%xmm2,%xmm7
- vfmsubss (%ecx),%xmm6,%xmm2,%xmm7
- vfmsubss %xmm4,(%ecx),%xmm2,%xmm7
- vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7
- vfnmaddss (%ecx),%xmm6,%xmm2,%xmm7
- vfnmaddss %xmm4,(%ecx),%xmm2,%xmm7
- vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7
- vfnmsubss (%ecx),%xmm6,%xmm2,%xmm7
- vfnmsubss %xmm4,(%ecx),%xmm2,%xmm7
+ vcmpss $7,%xmm4,%xmm6,%xmm2
+ vcmpss $7,(%ecx),%xmm6,%xmm2
+ vinsertps $7,%xmm4,%xmm6,%xmm2
+ vinsertps $7,(%ecx),%xmm6,%xmm2
+ vroundss $7,%xmm4,%xmm6,%xmm2
+ vroundss $7,(%ecx),%xmm6,%xmm2
# Tests for op xmm/m16, xmm
vpmovsxbq %xmm4,%xmm6
vpmovzxbq (%ecx),%xmm4
# Tests for op imm8, xmm, regl/mem16
- vpextrw $100,%xmm4,%ecx
- vpextrw $100,%xmm4,(%ecx)
+ vpextrw $7,%xmm4,%ecx
+ vpextrw $7,%xmm4,(%ecx)
# Tests for op imm8, xmm, regq/mem16
- vpextrw $100,%xmm4,(%ecx)
+ vpextrw $7,%xmm4,(%ecx)
# Tests for op imm8, regl/mem16, xmm, xmm
- vpinsrw $100,%ecx,%xmm4,%xmm6
- vpinsrw $100,(%ecx),%xmm4,%xmm6
-
+ vpinsrw $7,%ecx,%xmm4,%xmm6
+ vpinsrw $7,(%ecx),%xmm4,%xmm6
# Tests for op imm8, xmm, regl/mem8
- vpextrb $100,%xmm4,%ecx
- vpextrb $100,%xmm4,(%ecx)
+ vpextrb $7,%xmm4,%ecx
+ vpextrb $7,%xmm4,(%ecx)
# Tests for op imm8, regl/mem8, xmm, xmm
- vpinsrb $100,%ecx,%xmm4,%xmm6
- vpinsrb $100,(%ecx),%xmm4,%xmm6
+ vpinsrb $7,%ecx,%xmm4,%xmm6
+ vpinsrb $7,(%ecx),%xmm4,%xmm6
# Tests for op imm8, xmm, regq/mem8
- vpextrb $100,%xmm4,(%ecx)
+ vpextrb $7,%xmm4,(%ecx)
# Tests for op imm8, regl/mem8, xmm, xmm
- vpinsrb $100,%ecx,%xmm4,%xmm6
- vpinsrb $100,(%ecx),%xmm4,%xmm6
+ vpinsrb $7,%ecx,%xmm4,%xmm6
+ vpinsrb $7,(%ecx),%xmm4,%xmm6
# Tests for op xmm, xmm
vmaskmovdqu %xmm4,%xmm6
vmovmskpd %xmm4,%ecx
vmovmskps %xmm4,%ecx
vpmovmskb %xmm4,%ecx
+
# Tests for op xmm, xmm, xmm
vmovhlps %xmm4,%xmm6,%xmm2
vmovlhps %xmm4,%xmm6,%xmm2
vmovss %xmm4,%xmm6,%xmm2
# Tests for op imm8, xmm, xmm
- vpslld $100,%xmm4,%xmm6
- vpslldq $100,%xmm4,%xmm6
- vpsllq $100,%xmm4,%xmm6
- vpsllw $100,%xmm4,%xmm6
- vpsrad $100,%xmm4,%xmm6
- vpsraw $100,%xmm4,%xmm6
- vpsrld $100,%xmm4,%xmm6
- vpsrldq $100,%xmm4,%xmm6
- vpsrlq $100,%xmm4,%xmm6
- vpsrlw $100,%xmm4,%xmm6
+ vpslld $7,%xmm4,%xmm6
+ vpslldq $7,%xmm4,%xmm6
+ vpsllq $7,%xmm4,%xmm6
+ vpsllw $7,%xmm4,%xmm6
+ vpsrad $7,%xmm4,%xmm6
+ vpsraw $7,%xmm4,%xmm6
+ vpsrld $7,%xmm4,%xmm6
+ vpsrldq $7,%xmm4,%xmm6
+ vpsrlq $7,%xmm4,%xmm6
+ vpsrlw $7,%xmm4,%xmm6
# Tests for op imm8, xmm, regl
- vpextrw $100,%xmm4,%ecx
+ vpextrw $7,%xmm4,%ecx
# Tests for op ymm, regl
vmovmskpd %ymm4,%ecx
vmovmskps %ymm4,%ecx
-
# Default instructions without suffixes.
vcvtpd2dq %xmm4,%xmm6
vcvtpd2dq %ymm4,%xmm6
vcvtdq2pd 0x1234,%ymm0
vcvtpd2psy 0x1234,%xmm0
vpavgb 0x1234,%xmm0,%xmm7
- vaeskeygenassist $100,0x1234,%xmm0
- vpextrb $100,%xmm0,0x1234
+ vaeskeygenassist $7,0x1234,%xmm0
+ vpextrb $7,%xmm0,0x1234
vcvtsi2sdl 0x1234,%xmm0,%xmm7
vblendvps %xmm0,0x1234,%xmm4,%xmm6
- vpinsrb $100,0x1234,%xmm0,%xmm7
+ vpinsrb $7,0x1234,%xmm0,%xmm7
vmovdqa 0x1234,%ymm0
vmovdqa %ymm0,0x1234
vpermilpd 0x1234,%ymm0,%ymm7
- vroundpd $100,0x1234,%ymm0
- vextractf128 $100,%ymm0,0x1234
- vperm2f128 $100,0x1234,%ymm0,%ymm7
+ vroundpd $7,0x1234,%ymm0
+ vextractf128 $7,%ymm0,0x1234
+ vperm2f128 $7,0x1234,%ymm0,%ymm7
vblendvpd %ymm0,0x1234,%ymm4,%ymm6
vldmxcsr (%ebp)
vmovdqa (%ebp),%xmm0
vcvtdq2pd (%ebp),%ymm0
vcvtpd2psy (%ebp),%xmm0
vpavgb (%ebp),%xmm0,%xmm7
- vaeskeygenassist $100,(%ebp),%xmm0
- vpextrb $100,%xmm0,(%ebp)
+ vaeskeygenassist $7,(%ebp),%xmm0
+ vpextrb $7,%xmm0,(%ebp)
vcvtsi2sdl (%ebp),%xmm0,%xmm7
vblendvps %xmm0,(%ebp),%xmm4,%xmm6
- vpinsrb $100,(%ebp),%xmm0,%xmm7
+ vpinsrb $7,(%ebp),%xmm0,%xmm7
vmovdqa (%ebp),%ymm0
vmovdqa %ymm0,(%ebp)
vpermilpd (%ebp),%ymm0,%ymm7
- vroundpd $100,(%ebp),%ymm0
- vextractf128 $100,%ymm0,(%ebp)
- vperm2f128 $100,(%ebp),%ymm0,%ymm7
+ vroundpd $7,(%ebp),%ymm0
+ vextractf128 $7,%ymm0,(%ebp)
+ vperm2f128 $7,(%ebp),%ymm0,%ymm7
vblendvpd %ymm0,(%ebp),%ymm4,%ymm6
vldmxcsr (%esp)
vmovdqa (%esp),%xmm0
vcvtdq2pd (%esp),%ymm0
vcvtpd2psy (%esp),%xmm0
vpavgb (%esp),%xmm0,%xmm7
- vaeskeygenassist $100,(%esp),%xmm0
- vpextrb $100,%xmm0,(%esp)
+ vaeskeygenassist $7,(%esp),%xmm0
+ vpextrb $7,%xmm0,(%esp)
vcvtsi2sdl (%esp),%xmm0,%xmm7
vblendvps %xmm0,(%esp),%xmm4,%xmm6
- vpinsrb $100,(%esp),%xmm0,%xmm7
+ vpinsrb $7,(%esp),%xmm0,%xmm7
vmovdqa (%esp),%ymm0
vmovdqa %ymm0,(%esp)
vpermilpd (%esp),%ymm0,%ymm7
- vroundpd $100,(%esp),%ymm0
- vextractf128 $100,%ymm0,(%esp)
- vperm2f128 $100,(%esp),%ymm0,%ymm7
+ vroundpd $7,(%esp),%ymm0
+ vextractf128 $7,%ymm0,(%esp)
+ vperm2f128 $7,(%esp),%ymm0,%ymm7
vblendvpd %ymm0,(%esp),%ymm4,%ymm6
vldmxcsr 0x99(%ebp)
vmovdqa 0x99(%ebp),%xmm0
vcvtdq2pd 0x99(%ebp),%ymm0
vcvtpd2psy 0x99(%ebp),%xmm0
vpavgb 0x99(%ebp),%xmm0,%xmm7
- vaeskeygenassist $100,0x99(%ebp),%xmm0
- vpextrb $100,%xmm0,0x99(%ebp)
+ vaeskeygenassist $7,0x99(%ebp),%xmm0
+ vpextrb $7,%xmm0,0x99(%ebp)
vcvtsi2sdl 0x99(%ebp),%xmm0,%xmm7
vblendvps %xmm0,0x99(%ebp),%xmm4,%xmm6
- vpinsrb $100,0x99(%ebp),%xmm0,%xmm7
+ vpinsrb $7,0x99(%ebp),%xmm0,%xmm7
vmovdqa 0x99(%ebp),%ymm0
vmovdqa %ymm0,0x99(%ebp)
vpermilpd 0x99(%ebp),%ymm0,%ymm7
- vroundpd $100,0x99(%ebp),%ymm0
- vextractf128 $100,%ymm0,0x99(%ebp)
- vperm2f128 $100,0x99(%ebp),%ymm0,%ymm7
+ vroundpd $7,0x99(%ebp),%ymm0
+ vextractf128 $7,%ymm0,0x99(%ebp)
+ vperm2f128 $7,0x99(%ebp),%ymm0,%ymm7
vblendvpd %ymm0,0x99(%ebp),%ymm4,%ymm6
vldmxcsr 0x99(,%eiz)
vmovdqa 0x99(,%eiz),%xmm0
vcvtdq2pd 0x99(,%eiz),%ymm0
vcvtpd2psy 0x99(,%eiz),%xmm0
vpavgb 0x99(,%eiz),%xmm0,%xmm7
- vaeskeygenassist $100,0x99(,%eiz),%xmm0
- vpextrb $100,%xmm0,0x99(,%eiz)
+ vaeskeygenassist $7,0x99(,%eiz),%xmm0
+ vpextrb $7,%xmm0,0x99(,%eiz)
vcvtsi2sdl 0x99(,%eiz),%xmm0,%xmm7
vblendvps %xmm0,0x99(,%eiz),%xmm4,%xmm6
- vpinsrb $100,0x99(,%eiz),%xmm0,%xmm7
+ vpinsrb $7,0x99(,%eiz),%xmm0,%xmm7
vmovdqa 0x99(,%eiz),%ymm0
vmovdqa %ymm0,0x99(,%eiz)
vpermilpd 0x99(,%eiz),%ymm0,%ymm7
- vroundpd $100,0x99(,%eiz),%ymm0
- vextractf128 $100,%ymm0,0x99(,%eiz)
- vperm2f128 $100,0x99(,%eiz),%ymm0,%ymm7
+ vroundpd $7,0x99(,%eiz),%ymm0
+ vextractf128 $7,%ymm0,0x99(,%eiz)
+ vperm2f128 $7,0x99(,%eiz),%ymm0,%ymm7
vblendvpd %ymm0,0x99(,%eiz),%ymm4,%ymm6
vldmxcsr 0x99(,%eiz,2)
vmovdqa 0x99(,%eiz,2),%xmm0
vcvtdq2pd 0x99(,%eiz,2),%ymm0
vcvtpd2psy 0x99(,%eiz,2),%xmm0
vpavgb 0x99(,%eiz,2),%xmm0,%xmm7
- vaeskeygenassist $100,0x99(,%eiz,2),%xmm0
- vpextrb $100,%xmm0,0x99(,%eiz,2)
+ vaeskeygenassist $7,0x99(,%eiz,2),%xmm0
+ vpextrb $7,%xmm0,0x99(,%eiz,2)
vcvtsi2sdl 0x99(,%eiz,2),%xmm0,%xmm7
vblendvps %xmm0,0x99(,%eiz,2),%xmm4,%xmm6
- vpinsrb $100,0x99(,%eiz,2),%xmm0,%xmm7
+ vpinsrb $7,0x99(,%eiz,2),%xmm0,%xmm7
vmovdqa 0x99(,%eiz,2),%ymm0
vmovdqa %ymm0,0x99(,%eiz,2)
vpermilpd 0x99(,%eiz,2),%ymm0,%ymm7
- vroundpd $100,0x99(,%eiz,2),%ymm0
- vextractf128 $100,%ymm0,0x99(,%eiz,2)
- vperm2f128 $100,0x99(,%eiz,2),%ymm0,%ymm7
+ vroundpd $7,0x99(,%eiz,2),%ymm0
+ vextractf128 $7,%ymm0,0x99(,%eiz,2)
+ vperm2f128 $7,0x99(,%eiz,2),%ymm0,%ymm7
vblendvpd %ymm0,0x99(,%eiz,2),%ymm4,%ymm6
vldmxcsr 0x99(%eax,%eiz)
vmovdqa 0x99(%eax,%eiz),%xmm0
vcvtdq2pd 0x99(%eax,%eiz),%ymm0
vcvtpd2psy 0x99(%eax,%eiz),%xmm0
vpavgb 0x99(%eax,%eiz),%xmm0,%xmm7
- vaeskeygenassist $100,0x99(%eax,%eiz),%xmm0
- vpextrb $100,%xmm0,0x99(%eax,%eiz)
+ vaeskeygenassist $7,0x99(%eax,%eiz),%xmm0
+ vpextrb $7,%xmm0,0x99(%eax,%eiz)
vcvtsi2sdl 0x99(%eax,%eiz),%xmm0,%xmm7
vblendvps %xmm0,0x99(%eax,%eiz),%xmm4,%xmm6
- vpinsrb $100,0x99(%eax,%eiz),%xmm0,%xmm7
+ vpinsrb $7,0x99(%eax,%eiz),%xmm0,%xmm7
vmovdqa 0x99(%eax,%eiz),%ymm0
vmovdqa %ymm0,0x99(%eax,%eiz)
vpermilpd 0x99(%eax,%eiz),%ymm0,%ymm7
- vroundpd $100,0x99(%eax,%eiz),%ymm0
- vextractf128 $100,%ymm0,0x99(%eax,%eiz)
- vperm2f128 $100,0x99(%eax,%eiz),%ymm0,%ymm7
+ vroundpd $7,0x99(%eax,%eiz),%ymm0
+ vextractf128 $7,%ymm0,0x99(%eax,%eiz)
+ vperm2f128 $7,0x99(%eax,%eiz),%ymm0,%ymm7
vblendvpd %ymm0,0x99(%eax,%eiz),%ymm4,%ymm6
vldmxcsr 0x99(%eax,%eiz,2)
vmovdqa 0x99(%eax,%eiz,2),%xmm0
vcvtdq2pd 0x99(%eax,%eiz,2),%ymm0
vcvtpd2psy 0x99(%eax,%eiz,2),%xmm0
vpavgb 0x99(%eax,%eiz,2),%xmm0,%xmm7
- vaeskeygenassist $100,0x99(%eax,%eiz,2),%xmm0
- vpextrb $100,%xmm0,0x99(%eax,%eiz,2)
+ vaeskeygenassist $7,0x99(%eax,%eiz,2),%xmm0
+ vpextrb $7,%xmm0,0x99(%eax,%eiz,2)
vcvtsi2sdl 0x99(%eax,%eiz,2),%xmm0,%xmm7
vblendvps %xmm0,0x99(%eax,%eiz,2),%xmm4,%xmm6
- vpinsrb $100,0x99(%eax,%eiz,2),%xmm0,%xmm7
+ vpinsrb $7,0x99(%eax,%eiz,2),%xmm0,%xmm7
vmovdqa 0x99(%eax,%eiz,2),%ymm0
vmovdqa %ymm0,0x99(%eax,%eiz,2)
vpermilpd 0x99(%eax,%eiz,2),%ymm0,%ymm7
- vroundpd $100,0x99(%eax,%eiz,2),%ymm0
- vextractf128 $100,%ymm0,0x99(%eax,%eiz,2)
- vperm2f128 $100,0x99(%eax,%eiz,2),%ymm0,%ymm7
+ vroundpd $7,0x99(%eax,%eiz,2),%ymm0
+ vextractf128 $7,%ymm0,0x99(%eax,%eiz,2)
+ vperm2f128 $7,0x99(%eax,%eiz,2),%ymm0,%ymm7
vblendvpd %ymm0,0x99(%eax,%eiz,2),%ymm4,%ymm6
vldmxcsr 0x99(%eax,%ebx,4)
vmovdqa 0x99(%eax,%ebx,4),%xmm0
vcvtdq2pd 0x99(%eax,%ebx,4),%ymm0
vcvtpd2psy 0x99(%eax,%ebx,4),%xmm0
vpavgb 0x99(%eax,%ebx,4),%xmm0,%xmm7
- vaeskeygenassist $100,0x99(%eax,%ebx,4),%xmm0
- vpextrb $100,%xmm0,0x99(%eax,%ebx,4)
+ vaeskeygenassist $7,0x99(%eax,%ebx,4),%xmm0
+ vpextrb $7,%xmm0,0x99(%eax,%ebx,4)
vcvtsi2sdl 0x99(%eax,%ebx,4),%xmm0,%xmm7
vblendvps %xmm0,0x99(%eax,%ebx,4),%xmm4,%xmm6
- vpinsrb $100,0x99(%eax,%ebx,4),%xmm0,%xmm7
+ vpinsrb $7,0x99(%eax,%ebx,4),%xmm0,%xmm7
vmovdqa 0x99(%eax,%ebx,4),%ymm0
vmovdqa %ymm0,0x99(%eax,%ebx,4)
vpermilpd 0x99(%eax,%ebx,4),%ymm0,%ymm7
- vroundpd $100,0x99(%eax,%ebx,4),%ymm0
- vextractf128 $100,%ymm0,0x99(%eax,%ebx,4)
- vperm2f128 $100,0x99(%eax,%ebx,4),%ymm0,%ymm7
+ vroundpd $7,0x99(%eax,%ebx,4),%ymm0
+ vextractf128 $7,%ymm0,0x99(%eax,%ebx,4)
+ vperm2f128 $7,0x99(%eax,%ebx,4),%ymm0,%ymm7
vblendvpd %ymm0,0x99(%eax,%ebx,4),%ymm4,%ymm6
vldmxcsr 0x99(%esp,%ecx,8)
vmovdqa 0x99(%esp,%ecx,8),%xmm0
vcvtdq2pd 0x99(%esp,%ecx,8),%ymm0
vcvtpd2psy 0x99(%esp,%ecx,8),%xmm0
vpavgb 0x99(%esp,%ecx,8),%xmm0,%xmm7
- vaeskeygenassist $100,0x99(%esp,%ecx,8),%xmm0
- vpextrb $100,%xmm0,0x99(%esp,%ecx,8)
+ vaeskeygenassist $7,0x99(%esp,%ecx,8),%xmm0
+ vpextrb $7,%xmm0,0x99(%esp,%ecx,8)
vcvtsi2sdl 0x99(%esp,%ecx,8),%xmm0,%xmm7
vblendvps %xmm0,0x99(%esp,%ecx,8),%xmm4,%xmm6
- vpinsrb $100,0x99(%esp,%ecx,8),%xmm0,%xmm7
+ vpinsrb $7,0x99(%esp,%ecx,8),%xmm0,%xmm7
vmovdqa 0x99(%esp,%ecx,8),%ymm0
vmovdqa %ymm0,0x99(%esp,%ecx,8)
vpermilpd 0x99(%esp,%ecx,8),%ymm0,%ymm7
- vroundpd $100,0x99(%esp,%ecx,8),%ymm0
- vextractf128 $100,%ymm0,0x99(%esp,%ecx,8)
- vperm2f128 $100,0x99(%esp,%ecx,8),%ymm0,%ymm7
+ vroundpd $7,0x99(%esp,%ecx,8),%ymm0
+ vextractf128 $7,%ymm0,0x99(%esp,%ecx,8)
+ vperm2f128 $7,0x99(%esp,%ecx,8),%ymm0,%ymm7
vblendvpd %ymm0,0x99(%esp,%ecx,8),%ymm4,%ymm6
vldmxcsr 0x99(%ebp,%edx,1)
vmovdqa 0x99(%ebp,%edx,1),%xmm0
vcvtdq2pd 0x99(%ebp,%edx,1),%ymm0
vcvtpd2psy 0x99(%ebp,%edx,1),%xmm0
vpavgb 0x99(%ebp,%edx,1),%xmm0,%xmm7
- vaeskeygenassist $100,0x99(%ebp,%edx,1),%xmm0
- vpextrb $100,%xmm0,0x99(%ebp,%edx,1)
+ vaeskeygenassist $7,0x99(%ebp,%edx,1),%xmm0
+ vpextrb $7,%xmm0,0x99(%ebp,%edx,1)
vcvtsi2sdl 0x99(%ebp,%edx,1),%xmm0,%xmm7
vblendvps %xmm0,0x99(%ebp,%edx,1),%xmm4,%xmm6
- vpinsrb $100,0x99(%ebp,%edx,1),%xmm0,%xmm7
+ vpinsrb $7,0x99(%ebp,%edx,1),%xmm0,%xmm7
vmovdqa 0x99(%ebp,%edx,1),%ymm0
vmovdqa %ymm0,0x99(%ebp,%edx,1)
vpermilpd 0x99(%ebp,%edx,1),%ymm0,%ymm7
- vroundpd $100,0x99(%ebp,%edx,1),%ymm0
- vextractf128 $100,%ymm0,0x99(%ebp,%edx,1)
- vperm2f128 $100,0x99(%ebp,%edx,1),%ymm0,%ymm7
+ vroundpd $7,0x99(%ebp,%edx,1),%ymm0
+ vextractf128 $7,%ymm0,0x99(%ebp,%edx,1)
+ vperm2f128 $7,0x99(%ebp,%edx,1),%ymm0,%ymm7
vblendvpd %ymm0,0x99(%ebp,%edx,1),%ymm4,%ymm6
# Tests for all register operands.
vmovmskpd %xmm0,%eax
- vpslld $100,%xmm0,%xmm7
+ vpslld $7,%xmm0,%xmm7
vmovmskps %ymm0,%eax
.intel_syntax noprefix
+
# Tests for op mem64
vldmxcsr DWORD PTR [ecx]
vldmxcsr [ecx]
vmaskmovps [ecx],ymm6,ymm4
# Tests for op imm8, ymm/mem256, ymm
- vpermilpd ymm2,ymm6,100
- vpermilpd ymm6,YMMWORD PTR [ecx],100
- vpermilpd ymm6,[ecx],100
- vpermilps ymm2,ymm6,100
- vpermilps ymm6,YMMWORD PTR [ecx],100
- vpermilps ymm6,[ecx],100
- vroundpd ymm2,ymm6,100
- vroundpd ymm6,YMMWORD PTR [ecx],100
- vroundpd ymm6,[ecx],100
- vroundps ymm2,ymm6,100
- vroundps ymm6,YMMWORD PTR [ecx],100
- vroundps ymm6,[ecx],100
+ vpermilpd ymm2,ymm6,7
+ vpermilpd ymm6,YMMWORD PTR [ecx],7
+ vpermilpd ymm6,[ecx],7
+ vpermilps ymm2,ymm6,7
+ vpermilps ymm6,YMMWORD PTR [ecx],7
+ vpermilps ymm6,[ecx],7
+ vroundpd ymm2,ymm6,7
+ vroundpd ymm6,YMMWORD PTR [ecx],7
+ vroundpd ymm6,[ecx],7
+ vroundps ymm2,ymm6,7
+ vroundps ymm6,YMMWORD PTR [ecx],7
+ vroundps ymm6,[ecx],7
# Tests for op ymm/mem256, ymm, ymm
vaddpd ymm2,ymm6,ymm4
vcvttpd2dq xmm4,YMMWORD PTR [ecx]
# Tests for op ymm/mem256, ymm
- vcvtdq2ps ymm4,ymm4
+ vcvtdq2ps ymm6,ymm4
vcvtdq2ps ymm4,YMMWORD PTR [ecx]
vcvtdq2ps ymm4,[ecx]
- vcvtps2dq ymm4,ymm4
+ vcvtps2dq ymm6,ymm4
vcvtps2dq ymm4,YMMWORD PTR [ecx]
vcvtps2dq ymm4,[ecx]
- vcvttps2dq ymm4,ymm4
+ vcvttps2dq ymm6,ymm4
vcvttps2dq ymm4,YMMWORD PTR [ecx]
vcvttps2dq ymm4,[ecx]
- vmovapd ymm4,ymm4
+ vmovapd ymm6,ymm4
vmovapd ymm4,YMMWORD PTR [ecx]
vmovapd ymm4,[ecx]
- vmovaps ymm4,ymm4
+ vmovaps ymm6,ymm4
vmovaps ymm4,YMMWORD PTR [ecx]
vmovaps ymm4,[ecx]
- vmovdqa ymm4,ymm4
+ vmovdqa ymm6,ymm4
vmovdqa ymm4,YMMWORD PTR [ecx]
vmovdqa ymm4,[ecx]
- vmovdqu ymm4,ymm4
+ vmovdqu ymm6,ymm4
vmovdqu ymm4,YMMWORD PTR [ecx]
vmovdqu ymm4,[ecx]
- vmovddup ymm4,ymm4
+ vmovddup ymm6,ymm4
vmovddup ymm4,YMMWORD PTR [ecx]
vmovddup ymm4,[ecx]
- vmovshdup ymm4,ymm4
+ vmovshdup ymm6,ymm4
vmovshdup ymm4,YMMWORD PTR [ecx]
vmovshdup ymm4,[ecx]
- vmovsldup ymm4,ymm4
+ vmovsldup ymm6,ymm4
vmovsldup ymm4,YMMWORD PTR [ecx]
vmovsldup ymm4,[ecx]
- vmovupd ymm4,ymm4
+ vmovupd ymm6,ymm4
vmovupd ymm4,YMMWORD PTR [ecx]
vmovupd ymm4,[ecx]
- vmovups ymm4,ymm4
+ vmovups ymm6,ymm4
vmovups ymm4,YMMWORD PTR [ecx]
vmovups ymm4,[ecx]
- vptest ymm4,ymm4
+ vptest ymm6,ymm4
vptest ymm4,YMMWORD PTR [ecx]
vptest ymm4,[ecx]
- vrcpps ymm4,ymm4
+ vrcpps ymm6,ymm4
vrcpps ymm4,YMMWORD PTR [ecx]
vrcpps ymm4,[ecx]
- vrsqrtps ymm4,ymm4
+ vrsqrtps ymm6,ymm4
vrsqrtps ymm4,YMMWORD PTR [ecx]
vrsqrtps ymm4,[ecx]
- vsqrtpd ymm4,ymm4
+ vsqrtpd ymm6,ymm4
vsqrtpd ymm4,YMMWORD PTR [ecx]
vsqrtpd ymm4,[ecx]
- vsqrtps ymm4,ymm4
+ vsqrtps ymm6,ymm4
vsqrtps ymm4,YMMWORD PTR [ecx]
vsqrtps ymm4,[ecx]
- vtestpd ymm4,ymm4
+ vtestpd ymm6,ymm4
vtestpd ymm4,YMMWORD PTR [ecx]
vtestpd ymm4,[ecx]
- vtestps ymm4,ymm4
+ vtestps ymm6,ymm4
vtestps ymm4,YMMWORD PTR [ecx]
vtestps ymm4,[ecx]
vlddqu ymm4,[ecx]
# Tests for op imm8, ymm/mem256, ymm, ymm
- vblendpd ymm2,ymm6,ymm4,100
- vblendpd ymm2,ymm6,YMMWORD PTR [ecx],100
- vblendpd ymm2,ymm6,[ecx],100
- vblendps ymm2,ymm6,ymm4,100
- vblendps ymm2,ymm6,YMMWORD PTR [ecx],100
- vblendps ymm2,ymm6,[ecx],100
- vcmppd ymm2,ymm6,ymm4,100
- vcmppd ymm2,ymm6,YMMWORD PTR [ecx],100
- vcmppd ymm2,ymm6,[ecx],100
- vcmpps ymm2,ymm6,ymm4,100
- vcmpps ymm2,ymm6,YMMWORD PTR [ecx],100
- vcmpps ymm2,ymm6,[ecx],100
- vdpps ymm2,ymm6,ymm4,100
- vdpps ymm2,ymm6,YMMWORD PTR [ecx],100
- vdpps ymm2,ymm6,[ecx],100
- vperm2f128 ymm2,ymm6,ymm4,100
- vperm2f128 ymm2,ymm6,YMMWORD PTR [ecx],100
- vperm2f128 ymm2,ymm6,[ecx],100
- vshufpd ymm2,ymm6,ymm4,100
- vshufpd ymm2,ymm6,YMMWORD PTR [ecx],100
- vshufpd ymm2,ymm6,[ecx],100
- vshufps ymm2,ymm6,ymm4,100
- vshufps ymm2,ymm6,YMMWORD PTR [ecx],100
- vshufps ymm2,ymm6,[ecx],100
+ vblendpd ymm2,ymm6,ymm4,7
+ vblendpd ymm2,ymm6,YMMWORD PTR [ecx],7
+ vblendpd ymm2,ymm6,[ecx],7
+ vblendps ymm2,ymm6,ymm4,7
+ vblendps ymm2,ymm6,YMMWORD PTR [ecx],7
+ vblendps ymm2,ymm6,[ecx],7
+ vcmppd ymm2,ymm6,ymm4,7
+ vcmppd ymm2,ymm6,YMMWORD PTR [ecx],7
+ vcmppd ymm2,ymm6,[ecx],7
+ vcmpps ymm2,ymm6,ymm4,7
+ vcmpps ymm2,ymm6,YMMWORD PTR [ecx],7
+ vcmpps ymm2,ymm6,[ecx],7
+ vdpps ymm2,ymm6,ymm4,7
+ vdpps ymm2,ymm6,YMMWORD PTR [ecx],7
+ vdpps ymm2,ymm6,[ecx],7
+ vperm2f128 ymm2,ymm6,ymm4,7
+ vperm2f128 ymm2,ymm6,YMMWORD PTR [ecx],7
+ vperm2f128 ymm2,ymm6,[ecx],7
+ vshufpd ymm2,ymm6,ymm4,7
+ vshufpd ymm2,ymm6,YMMWORD PTR [ecx],7
+ vshufpd ymm2,ymm6,[ecx],7
+ vshufps ymm2,ymm6,ymm4,7
+ vshufps ymm2,ymm6,YMMWORD PTR [ecx],7
+ vshufps ymm2,ymm6,[ecx],7
# Tests for op ymm, ymm/mem256, ymm, ymm
vblendvpd ymm7,ymm2,ymm6,ymm4
vblendvps ymm7,ymm2,YMMWORD PTR [ecx],ymm4
vblendvps ymm7,ymm2,[ecx],ymm4
-# Tests for op ymm/mem256, ymm, ymm, ymm
-# Tests for op ymm, ymm/mem256, ymm, ymm
- vfmaddpd ymm7,ymm2,ymm6,ymm4
- vfmaddpd ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vfmaddpd ymm7,ymm2,ymm6,[ecx]
- vfmaddps ymm7,ymm2,ymm6,ymm4
- vfmaddps ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vfmaddps ymm7,ymm2,ymm6,[ecx]
- vfmaddsubpd ymm7,ymm2,ymm6,ymm4
- vfmaddsubpd ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vfmaddsubpd ymm7,ymm2,ymm6,[ecx]
- vfmaddsubps ymm7,ymm2,ymm6,ymm4
- vfmaddsubps ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vfmaddsubps ymm7,ymm2,ymm6,[ecx]
- vfmsubaddpd ymm7,ymm2,ymm6,ymm4
- vfmsubaddpd ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vfmsubaddpd ymm7,ymm2,ymm6,[ecx]
- vfmsubaddps ymm7,ymm2,ymm6,ymm4
- vfmsubaddps ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vfmsubaddps ymm7,ymm2,ymm6,[ecx]
- vfmsubpd ymm7,ymm2,ymm6,ymm4
- vfmsubpd ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vfmsubpd ymm7,ymm2,ymm6,[ecx]
- vfmsubps ymm7,ymm2,ymm6,ymm4
- vfmsubps ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vfmsubps ymm7,ymm2,ymm6,[ecx]
- vfnmaddpd ymm7,ymm2,ymm6,ymm4
- vfnmaddpd ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vfnmaddpd ymm7,ymm2,ymm6,[ecx]
- vfnmaddps ymm7,ymm2,ymm6,ymm4
- vfnmaddps ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vfnmaddps ymm7,ymm2,ymm6,[ecx]
- vfnmsubpd ymm7,ymm2,ymm6,ymm4
- vfnmsubpd ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vfnmsubpd ymm7,ymm2,ymm6,[ecx]
- vfnmsubps ymm7,ymm2,ymm6,ymm4
- vfnmsubps ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vfnmsubps ymm7,ymm2,ymm6,[ecx]
- vpermilmo2pd ymm7,ymm2,ymm6,ymm4
- vpermilmo2pd ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vpermilmo2pd ymm7,ymm2,ymm6,[ecx]
- vpermilmz2pd ymm7,ymm2,ymm6,ymm4
- vpermilmz2pd ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vpermilmz2pd ymm7,ymm2,ymm6,[ecx]
- vpermiltd2pd ymm7,ymm2,ymm6,ymm4
- vpermiltd2pd ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vpermiltd2pd ymm7,ymm2,ymm6,[ecx]
- vpermilmo2ps ymm7,ymm2,ymm6,ymm4
- vpermilmo2ps ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vpermilmo2ps ymm7,ymm2,ymm6,[ecx]
- vpermilmz2ps ymm7,ymm2,ymm6,ymm4
- vpermilmz2ps ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vpermilmz2ps ymm7,ymm2,ymm6,[ecx]
- vpermiltd2ps ymm7,ymm2,ymm6,ymm4
- vpermiltd2ps ymm7,ymm2,ymm6,YMMWORD PTR [ecx]
- vpermiltd2ps ymm7,ymm2,ymm6,[ecx]
-
-# Tests for op imm4, ymm/mem256, ymm, ymm, ymm
-# Tests for op imm4, ymm, ymm/mem256, ymm, ymm
- vpermil2pd ymm7,ymm2,ymm6,ymm4,10
- vpermil2pd ymm7,ymm2,ymm6,YMMWORD PTR [ecx],10
- vpermil2pd ymm7,ymm2,ymm6,[ecx],10
- vpermil2ps ymm7,ymm2,ymm6,ymm4,10
- vpermil2ps ymm7,ymm2,ymm6,YMMWORD PTR [ecx],10
- vpermil2ps ymm7,ymm2,ymm6,[ecx],10
-
# Tests for op imm8, xmm/mem128, ymm, ymm
- vinsertf128 ymm6,ymm4,xmm4,100
- vinsertf128 ymm6,ymm4,XMMWORD PTR [ecx],100
- vinsertf128 ymm6,ymm4,[ecx],100
+ vinsertf128 ymm6,ymm4,xmm4,7
+ vinsertf128 ymm6,ymm4,XMMWORD PTR [ecx],7
+ vinsertf128 ymm6,ymm4,[ecx],7
# Tests for op imm8, ymm, xmm/mem128
- vextractf128 xmm4,ymm4,100
- vextractf128 XMMWORD PTR [ecx],ymm4,100
- vextractf128 [ecx],ymm4,100
+ vextractf128 xmm4,ymm4,7
+ vextractf128 XMMWORD PTR [ecx],ymm4,7
+ vextractf128 [ecx],ymm4,7
# Tests for op mem128, ymm
vbroadcastf128 ymm4,XMMWORD PTR [ecx]
vmaskmovpd xmm6,xmm4,[ecx]
# Tests for op imm8, xmm/mem128, xmm
- vaeskeygenassist xmm6,xmm4,100
- vaeskeygenassist xmm6,XMMWORD PTR [ecx],100
- vaeskeygenassist xmm6,[ecx],100
- vpcmpestri xmm6,xmm4,100
- vpcmpestri xmm6,XMMWORD PTR [ecx],100
- vpcmpestri xmm6,[ecx],100
- vpcmpestrm xmm6,xmm4,100
- vpcmpestrm xmm6,XMMWORD PTR [ecx],100
- vpcmpestrm xmm6,[ecx],100
- vpcmpistri xmm6,xmm4,100
- vpcmpistri xmm6,XMMWORD PTR [ecx],100
- vpcmpistri xmm6,[ecx],100
- vpcmpistrm xmm6,xmm4,100
- vpcmpistrm xmm6,XMMWORD PTR [ecx],100
- vpcmpistrm xmm6,[ecx],100
- vpermilpd xmm6,xmm4,100
- vpermilpd xmm6,XMMWORD PTR [ecx],100
- vpermilpd xmm6,[ecx],100
- vpermilps xmm6,xmm4,100
- vpermilps xmm6,XMMWORD PTR [ecx],100
- vpermilps xmm6,[ecx],100
- vpshufd xmm6,xmm4,100
- vpshufd xmm6,XMMWORD PTR [ecx],100
- vpshufd xmm6,[ecx],100
- vpshufhw xmm6,xmm4,100
- vpshufhw xmm6,XMMWORD PTR [ecx],100
- vpshufhw xmm6,[ecx],100
- vpshuflw xmm6,xmm4,100
- vpshuflw xmm6,XMMWORD PTR [ecx],100
- vpshuflw xmm6,[ecx],100
- vroundpd xmm6,xmm4,100
- vroundpd xmm6,XMMWORD PTR [ecx],100
- vroundpd xmm6,[ecx],100
- vroundps xmm6,xmm4,100
- vroundps xmm6,XMMWORD PTR [ecx],100
- vroundps xmm6,[ecx],100
+ vaeskeygenassist xmm6,xmm4,7
+ vaeskeygenassist xmm6,XMMWORD PTR [ecx],7
+ vaeskeygenassist xmm6,[ecx],7
+ vpcmpestri xmm6,xmm4,7
+ vpcmpestri xmm6,XMMWORD PTR [ecx],7
+ vpcmpestri xmm6,[ecx],7
+ vpcmpestrm xmm6,xmm4,7
+ vpcmpestrm xmm6,XMMWORD PTR [ecx],7
+ vpcmpestrm xmm6,[ecx],7
+ vpcmpistri xmm6,xmm4,7
+ vpcmpistri xmm6,XMMWORD PTR [ecx],7
+ vpcmpistri xmm6,[ecx],7
+ vpcmpistrm xmm6,xmm4,7
+ vpcmpistrm xmm6,XMMWORD PTR [ecx],7
+ vpcmpistrm xmm6,[ecx],7
+ vpermilpd xmm6,xmm4,7
+ vpermilpd xmm6,XMMWORD PTR [ecx],7
+ vpermilpd xmm6,[ecx],7
+ vpermilps xmm6,xmm4,7
+ vpermilps xmm6,XMMWORD PTR [ecx],7
+ vpermilps xmm6,[ecx],7
+ vpshufd xmm6,xmm4,7
+ vpshufd xmm6,XMMWORD PTR [ecx],7
+ vpshufd xmm6,[ecx],7
+ vpshufhw xmm6,xmm4,7
+ vpshufhw xmm6,XMMWORD PTR [ecx],7
+ vpshufhw xmm6,[ecx],7
+ vpshuflw xmm6,xmm4,7
+ vpshuflw xmm6,XMMWORD PTR [ecx],7
+ vpshuflw xmm6,[ecx],7
+ vroundpd xmm6,xmm4,7
+ vroundpd xmm6,XMMWORD PTR [ecx],7
+ vroundpd xmm6,[ecx],7
+ vroundps xmm6,xmm4,7
+ vroundps xmm6,XMMWORD PTR [ecx],7
+ vroundps xmm6,[ecx],7
# Tests for op xmm, xmm, mem128
vmaskmovps XMMWORD PTR [ecx],xmm6,xmm4
vmaskmovpd [ecx],xmm6,xmm4
# Tests for op imm8, xmm/mem128, xmm, xmm
- vblendpd xmm2,xmm6,xmm4,100
- vblendpd xmm2,xmm6,XMMWORD PTR [ecx],100
- vblendpd xmm2,xmm6,[ecx],100
- vblendps xmm2,xmm6,xmm4,100
- vblendps xmm2,xmm6,XMMWORD PTR [ecx],100
- vblendps xmm2,xmm6,[ecx],100
- vcmppd xmm2,xmm6,xmm4,100
- vcmppd xmm2,xmm6,XMMWORD PTR [ecx],100
- vcmppd xmm2,xmm6,[ecx],100
- vcmpps xmm2,xmm6,xmm4,100
- vcmpps xmm2,xmm6,XMMWORD PTR [ecx],100
- vcmpps xmm2,xmm6,[ecx],100
- vdppd xmm2,xmm6,xmm4,100
- vdppd xmm2,xmm6,XMMWORD PTR [ecx],100
- vdppd xmm2,xmm6,[ecx],100
- vdpps xmm2,xmm6,xmm4,100
- vdpps xmm2,xmm6,XMMWORD PTR [ecx],100
- vdpps xmm2,xmm6,[ecx],100
- vmpsadbw xmm2,xmm6,xmm4,100
- vmpsadbw xmm2,xmm6,XMMWORD PTR [ecx],100
- vmpsadbw xmm2,xmm6,[ecx],100
- vpalignr xmm2,xmm6,xmm4,100
- vpalignr xmm2,xmm6,XMMWORD PTR [ecx],100
- vpalignr xmm2,xmm6,[ecx],100
- vpblendw xmm2,xmm6,xmm4,100
- vpblendw xmm2,xmm6,XMMWORD PTR [ecx],100
- vpblendw xmm2,xmm6,[ecx],100
- vshufpd xmm2,xmm6,xmm4,100
- vshufpd xmm2,xmm6,XMMWORD PTR [ecx],100
- vshufpd xmm2,xmm6,[ecx],100
- vshufps xmm2,xmm6,xmm4,100
- vshufps xmm2,xmm6,XMMWORD PTR [ecx],100
- vshufps xmm2,xmm6,[ecx],100
+ vblendpd xmm2,xmm6,xmm4,7
+ vblendpd xmm2,xmm6,XMMWORD PTR [ecx],7
+ vblendpd xmm2,xmm6,[ecx],7
+ vblendps xmm2,xmm6,xmm4,7
+ vblendps xmm2,xmm6,XMMWORD PTR [ecx],7
+ vblendps xmm2,xmm6,[ecx],7
+ vcmppd xmm2,xmm6,xmm4,7
+ vcmppd xmm2,xmm6,XMMWORD PTR [ecx],7
+ vcmppd xmm2,xmm6,[ecx],7
+ vcmpps xmm2,xmm6,xmm4,7
+ vcmpps xmm2,xmm6,XMMWORD PTR [ecx],7
+ vcmpps xmm2,xmm6,[ecx],7
+ vdppd xmm2,xmm6,xmm4,7
+ vdppd xmm2,xmm6,XMMWORD PTR [ecx],7
+ vdppd xmm2,xmm6,[ecx],7
+ vdpps xmm2,xmm6,xmm4,7
+ vdpps xmm2,xmm6,XMMWORD PTR [ecx],7
+ vdpps xmm2,xmm6,[ecx],7
+ vmpsadbw xmm2,xmm6,xmm4,7
+ vmpsadbw xmm2,xmm6,XMMWORD PTR [ecx],7
+ vmpsadbw xmm2,xmm6,[ecx],7
+ vpalignr xmm2,xmm6,xmm4,7
+ vpalignr xmm2,xmm6,XMMWORD PTR [ecx],7
+ vpalignr xmm2,xmm6,[ecx],7
+ vpblendw xmm2,xmm6,xmm4,7
+ vpblendw xmm2,xmm6,XMMWORD PTR [ecx],7
+ vpblendw xmm2,xmm6,[ecx],7
+ vshufpd xmm2,xmm6,xmm4,7
+ vshufpd xmm2,xmm6,XMMWORD PTR [ecx],7
+ vshufpd xmm2,xmm6,[ecx],7
+ vshufps xmm2,xmm6,xmm4,7
+ vshufps xmm2,xmm6,XMMWORD PTR [ecx],7
+ vshufps xmm2,xmm6,[ecx],7
# Tests for op xmm, xmm/mem128, xmm, xmm
vblendvpd xmm7,xmm2,xmm6,xmm4
vpblendvb xmm7,xmm2,XMMWORD PTR [ecx],xmm4
vpblendvb xmm7,xmm2,[ecx],xmm4
-# Tests for op xmm/mem128, xmm, xmm, xmm
-# Tests for op xmm, xmm/mem128, xmm, xmm
- vfmaddpd xmm7,xmm2,xmm6,xmm4
- vfmaddpd xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vfmaddpd xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vfmaddpd xmm7,xmm2,xmm6,[ecx]
- vfmaddpd xmm7,xmm2,[ecx],xmm4
- vfmaddps xmm7,xmm2,xmm6,xmm4
- vfmaddps xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vfmaddps xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vfmaddps xmm7,xmm2,xmm6,[ecx]
- vfmaddps xmm7,xmm2,[ecx],xmm4
- vfmaddsubpd xmm7,xmm2,xmm6,xmm4
- vfmaddsubpd xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vfmaddsubpd xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vfmaddsubpd xmm7,xmm2,xmm6,[ecx]
- vfmaddsubpd xmm7,xmm2,[ecx],xmm4
- vfmaddsubps xmm7,xmm2,xmm6,xmm4
- vfmaddsubps xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vfmaddsubps xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vfmaddsubps xmm7,xmm2,xmm6,[ecx]
- vfmaddsubps xmm7,xmm2,[ecx],xmm4
- vfmsubaddpd xmm7,xmm2,xmm6,xmm4
- vfmsubaddpd xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vfmsubaddpd xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vfmsubaddpd xmm7,xmm2,xmm6,[ecx]
- vfmsubaddpd xmm7,xmm2,[ecx],xmm4
- vfmsubaddps xmm7,xmm2,xmm6,xmm4
- vfmsubaddps xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vfmsubaddps xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vfmsubaddps xmm7,xmm2,xmm6,[ecx]
- vfmsubaddps xmm7,xmm2,[ecx],xmm4
- vfmsubpd xmm7,xmm2,xmm6,xmm4
- vfmsubpd xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vfmsubpd xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vfmsubpd xmm7,xmm2,xmm6,[ecx]
- vfmsubpd xmm7,xmm2,[ecx],xmm4
- vfmsubps xmm7,xmm2,xmm6,xmm4
- vfmsubps xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vfmsubps xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vfmsubps xmm7,xmm2,xmm6,[ecx]
- vfmsubps xmm7,xmm2,[ecx],xmm4
- vfnmaddpd xmm7,xmm2,xmm6,xmm4
- vfnmaddpd xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vfnmaddpd xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vfnmaddpd xmm7,xmm2,xmm6,[ecx]
- vfnmaddpd xmm7,xmm2,[ecx],xmm4
- vfnmaddps xmm7,xmm2,xmm6,xmm4
- vfnmaddps xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vfnmaddps xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vfnmaddps xmm7,xmm2,xmm6,[ecx]
- vfnmaddps xmm7,xmm2,[ecx],xmm4
- vfnmsubpd xmm7,xmm2,xmm6,xmm4
- vfnmsubpd xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vfnmsubpd xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vfnmsubpd xmm7,xmm2,xmm6,[ecx]
- vfnmsubpd xmm7,xmm2,[ecx],xmm4
- vfnmsubps xmm7,xmm2,xmm6,xmm4
- vfnmsubps xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vfnmsubps xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vfnmsubps xmm7,xmm2,xmm6,[ecx]
- vfnmsubps xmm7,xmm2,[ecx],xmm4
- vpermilmo2pd xmm7,xmm2,xmm6,xmm4
- vpermilmo2pd xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vpermilmo2pd xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vpermilmo2pd xmm7,xmm2,xmm6,[ecx]
- vpermilmo2pd xmm7,xmm2,[ecx],xmm4
- vpermilmz2pd xmm7,xmm2,xmm6,xmm4
- vpermilmz2pd xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vpermilmz2pd xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vpermilmz2pd xmm7,xmm2,xmm6,[ecx]
- vpermilmz2pd xmm7,xmm2,[ecx],xmm4
- vpermiltd2pd xmm7,xmm2,xmm6,xmm4
- vpermiltd2pd xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vpermiltd2pd xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vpermiltd2pd xmm7,xmm2,xmm6,[ecx]
- vpermiltd2pd xmm7,xmm2,[ecx],xmm4
- vpermilmo2ps xmm7,xmm2,xmm6,xmm4
- vpermilmo2ps xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vpermilmo2ps xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vpermilmo2ps xmm7,xmm2,xmm6,[ecx]
- vpermilmo2ps xmm7,xmm2,[ecx],xmm4
- vpermilmz2ps xmm7,xmm2,xmm6,xmm4
- vpermilmz2ps xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vpermilmz2ps xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vpermilmz2ps xmm7,xmm2,xmm6,[ecx]
- vpermilmz2ps xmm7,xmm2,[ecx],xmm4
- vpermiltd2ps xmm7,xmm2,xmm6,xmm4
- vpermiltd2ps xmm7,xmm2,xmm6,XMMWORD PTR [ecx]
- vpermiltd2ps xmm7,xmm2,XMMWORD PTR [ecx],xmm4
- vpermiltd2ps xmm7,xmm2,xmm6,[ecx]
- vpermiltd2ps xmm7,xmm2,[ecx],xmm4
-
-# Tests for op imm4, xmm/mem128, xmm, xmm, xmm
-# Tests for op imm4, xmm, xmm/mem128, xmm, xmm
- vpermil2pd xmm7,xmm2,xmm6,xmm4,10
- vpermil2pd xmm7,xmm2,xmm6,XMMWORD PTR [ecx],10
- vpermil2pd xmm7,xmm2,XMMWORD PTR [ecx],xmm4,10
- vpermil2pd xmm7,xmm2,xmm6,[ecx],10
- vpermil2pd xmm7,xmm2,[ecx],xmm4,10
- vpermil2ps xmm7,xmm2,xmm6,xmm4,10
- vpermil2ps xmm7,xmm2,xmm6,XMMWORD PTR [ecx],10
- vpermil2ps xmm7,xmm2,XMMWORD PTR [ecx],xmm4,10
- vpermil2ps xmm7,xmm2,xmm6,[ecx],10
- vpermil2ps xmm7,xmm2,[ecx],xmm4,10
-
# Tests for op mem64, ymm
vbroadcastsd ymm4,QWORD PTR [ecx]
vbroadcastsd ymm4,[ecx]
vmovhps xmm6,xmm4,[ecx]
# Tests for op imm8, xmm/mem64, xmm, xmm
- vcmpsd xmm2,xmm6,xmm4,100
- vcmpsd xmm2,xmm6,QWORD PTR [ecx],100
- vcmpsd xmm2,xmm6,[ecx],100
- vroundsd xmm2,xmm6,xmm4,100
- vroundsd xmm2,xmm6,QWORD PTR [ecx],100
- vroundsd xmm2,xmm6,[ecx],100
-
-# Tests for op xmm/mem64, xmm, xmm, xmm
-# Tests for op xmm, xmm/mem64, xmm, xmm
- vfmaddsd xmm7,xmm2,xmm6,xmm4
- vfmaddsd xmm7,xmm2,xmm6,QWORD PTR [ecx]
- vfmaddsd xmm7,xmm2,QWORD PTR [ecx],xmm4
- vfmaddsd xmm7,xmm2,xmm6,[ecx]
- vfmaddsd xmm7,xmm2,[ecx],xmm4
- vfmsubsd xmm7,xmm2,xmm6,xmm4
- vfmsubsd xmm7,xmm2,xmm6,QWORD PTR [ecx]
- vfmsubsd xmm7,xmm2,QWORD PTR [ecx],xmm4
- vfmsubsd xmm7,xmm2,xmm6,[ecx]
- vfmsubsd xmm7,xmm2,[ecx],xmm4
- vfnmaddsd xmm7,xmm2,xmm6,xmm4
- vfnmaddsd xmm7,xmm2,xmm6,QWORD PTR [ecx]
- vfnmaddsd xmm7,xmm2,QWORD PTR [ecx],xmm4
- vfnmaddsd xmm7,xmm2,xmm6,[ecx]
- vfnmaddsd xmm7,xmm2,[ecx],xmm4
- vfnmsubsd xmm7,xmm2,xmm6,xmm4
- vfnmsubsd xmm7,xmm2,xmm6,QWORD PTR [ecx]
- vfnmsubsd xmm7,xmm2,QWORD PTR [ecx],xmm4
- vfnmsubsd xmm7,xmm2,xmm6,[ecx]
- vfnmsubsd xmm7,xmm2,[ecx],xmm4
+ vcmpsd xmm2,xmm6,xmm4,7
+ vcmpsd xmm2,xmm6,QWORD PTR [ecx],7
+ vcmpsd xmm2,xmm6,[ecx],7
+ vroundsd xmm2,xmm6,xmm4,7
+ vroundsd xmm2,xmm6,QWORD PTR [ecx],7
+ vroundsd xmm2,xmm6,[ecx],7
# Tests for op xmm/mem64, xmm, xmm
vaddsd xmm2,xmm6,xmm4
vcmptrue_ussd xmm2,xmm6,QWORD PTR [ecx]
vcmptrue_ussd xmm2,xmm6,[ecx]
+# Tests for op mem64
+ vldmxcsr DWORD PTR [ecx]
+ vldmxcsr [ecx]
+ vstmxcsr DWORD PTR [ecx]
+ vstmxcsr [ecx]
+
# Tests for op xmm/mem32, xmm, xmm
vaddss xmm2,xmm6,xmm4
vaddss xmm2,xmm6,DWORD PTR [ecx]
vcvttss2si ecx,[ecx]
# Tests for op imm8, xmm, regq/mem32
- vextractps DWORD PTR [ecx],xmm4,100
- vextractps [ecx],xmm4,100
+ vextractps DWORD PTR [ecx],xmm4,7
+ vextractps [ecx],xmm4,7
+
# Tests for op imm8, xmm, regl/mem32
- vpextrd ecx,xmm4,100
- vpextrd DWORD PTR [ecx],xmm4,100
- vpextrd [ecx],xmm4,100
- vextractps ecx,xmm4,100
- vextractps DWORD PTR [ecx],xmm4,100
- vextractps [ecx],xmm4,100
+ vpextrd ecx,xmm4,7
+ vpextrd DWORD PTR [ecx],xmm4,7
+ vpextrd [ecx],xmm4,7
+ vextractps ecx,xmm4,7
+ vextractps DWORD PTR [ecx],xmm4,7
+ vextractps [ecx],xmm4,7
# Tests for op regl/mem32, xmm, xmm
vcvtsi2sd xmm6,xmm4,ecx
vcvtsi2ss xmm6,xmm4,[ecx]
# Tests for op imm8, xmm/mem32, xmm, xmm
- vcmpss xmm2,xmm6,xmm4,100
- vcmpss xmm2,xmm6,DWORD PTR [ecx],100
- vcmpss xmm2,xmm6,[ecx],100
- vinsertps xmm2,xmm6,xmm4,100
- vinsertps xmm2,xmm6,DWORD PTR [ecx],100
- vinsertps xmm2,xmm6,[ecx],100
- vroundss xmm2,xmm6,xmm4,100
- vroundss xmm2,xmm6,DWORD PTR [ecx],100
- vroundss xmm2,xmm6,[ecx],100
-
-# Tests for op xmm/mem32, xmm, xmm, xmm
-# Tests for op xmm, xmm/mem32, xmm, xmm
- vfmaddss xmm7,xmm2,xmm6,xmm4
- vfmaddss xmm7,xmm2,xmm6,DWORD PTR [ecx]
- vfmaddss xmm7,xmm2,DWORD PTR [ecx],xmm4
- vfmaddss xmm7,xmm2,xmm6,[ecx]
- vfmaddss xmm7,xmm2,[ecx],xmm4
- vfmsubss xmm7,xmm2,xmm6,xmm4
- vfmsubss xmm7,xmm2,xmm6,DWORD PTR [ecx]
- vfmsubss xmm7,xmm2,DWORD PTR [ecx],xmm4
- vfmsubss xmm7,xmm2,xmm6,[ecx]
- vfmsubss xmm7,xmm2,[ecx],xmm4
- vfnmaddss xmm7,xmm2,xmm6,xmm4
- vfnmaddss xmm7,xmm2,xmm6,DWORD PTR [ecx]
- vfnmaddss xmm7,xmm2,DWORD PTR [ecx],xmm4
- vfnmaddss xmm7,xmm2,xmm6,[ecx]
- vfnmaddss xmm7,xmm2,[ecx],xmm4
- vfnmsubss xmm7,xmm2,xmm6,xmm4
- vfnmsubss xmm7,xmm2,xmm6,DWORD PTR [ecx]
- vfnmsubss xmm7,xmm2,DWORD PTR [ecx],xmm4
- vfnmsubss xmm7,xmm2,xmm6,[ecx]
- vfnmsubss xmm7,xmm2,[ecx],xmm4
+ vcmpss xmm2,xmm6,xmm4,7
+ vcmpss xmm2,xmm6,DWORD PTR [ecx],7
+ vcmpss xmm2,xmm6,[ecx],7
+ vinsertps xmm2,xmm6,xmm4,7
+ vinsertps xmm2,xmm6,DWORD PTR [ecx],7
+ vinsertps xmm2,xmm6,[ecx],7
+ vroundss xmm2,xmm6,xmm4,7
+ vroundss xmm2,xmm6,DWORD PTR [ecx],7
+ vroundss xmm2,xmm6,[ecx],7
# Tests for op xmm/m16, xmm
vpmovsxbq xmm6,xmm4
vpmovzxbq xmm4,[ecx]
# Tests for op imm8, xmm, regl/mem16
- vpextrw ecx,xmm4,100
- vpextrw WORD PTR [ecx],xmm4,100
- vpextrw [ecx],xmm4,100
+ vpextrw ecx,xmm4,7
+ vpextrw WORD PTR [ecx],xmm4,7
+ vpextrw [ecx],xmm4,7
# Tests for op imm8, xmm, regq/mem16
- vpextrw WORD PTR [ecx],xmm4,100
- vpextrw [ecx],xmm4,100
+ vpextrw WORD PTR [ecx],xmm4,7
+ vpextrw [ecx],xmm4,7
# Tests for op imm8, regl/mem16, xmm, xmm
- vpinsrw xmm6,xmm4,ecx,100
- vpinsrw xmm6,xmm4,WORD PTR [ecx],100
- vpinsrw xmm6,xmm4,[ecx],100
-
+ vpinsrw xmm6,xmm4,ecx,7
+ vpinsrw xmm6,xmm4,WORD PTR [ecx],7
+ vpinsrw xmm6,xmm4,[ecx],7
# Tests for op imm8, xmm, regl/mem8
- vpextrb ecx,xmm4,100
- vpextrb BYTE PTR [ecx],xmm4,100
- vpextrb [ecx],xmm4,100
+ vpextrb ecx,xmm4,7
+ vpextrb BYTE PTR [ecx],xmm4,7
+ vpextrb [ecx],xmm4,7
# Tests for op imm8, regl/mem8, xmm, xmm
- vpinsrb xmm6,xmm4,ecx,100
- vpinsrb xmm6,xmm4,BYTE PTR [ecx],100
- vpinsrb xmm6,xmm4,[ecx],100
+ vpinsrb xmm6,xmm4,ecx,7
+ vpinsrb xmm6,xmm4,BYTE PTR [ecx],7
+ vpinsrb xmm6,xmm4,[ecx],7
# Tests for op imm8, xmm, regq/mem8
- vpextrb BYTE PTR [ecx],xmm4,100
- vpextrb [ecx],xmm4,100
+ vpextrb BYTE PTR [ecx],xmm4,7
+ vpextrb [ecx],xmm4,7
# Tests for op imm8, regl/mem8, xmm, xmm
- vpinsrb xmm6,xmm4,ecx,100
- vpinsrb xmm6,xmm4,BYTE PTR [ecx],100
- vpinsrb xmm6,xmm4,[ecx],100
+ vpinsrb xmm6,xmm4,ecx,7
+ vpinsrb xmm6,xmm4,BYTE PTR [ecx],7
+ vpinsrb xmm6,xmm4,[ecx],7
# Tests for op xmm, xmm
vmaskmovdqu xmm6,xmm4
vmovmskpd ecx,xmm4
vmovmskps ecx,xmm4
vpmovmskb ecx,xmm4
+
# Tests for op xmm, xmm, xmm
vmovhlps xmm2,xmm6,xmm4
vmovlhps xmm2,xmm6,xmm4
vmovss xmm2,xmm6,xmm4
# Tests for op imm8, xmm, xmm
- vpslld xmm6,xmm4,100
- vpslldq xmm6,xmm4,100
- vpsllq xmm6,xmm4,100
- vpsllw xmm6,xmm4,100
- vpsrad xmm6,xmm4,100
- vpsraw xmm6,xmm4,100
- vpsrld xmm6,xmm4,100
- vpsrldq xmm6,xmm4,100
- vpsrlq xmm6,xmm4,100
- vpsrlw xmm6,xmm4,100
+ vpslld xmm6,xmm4,7
+ vpslldq xmm6,xmm4,7
+ vpsllq xmm6,xmm4,7
+ vpsllw xmm6,xmm4,7
+ vpsrad xmm6,xmm4,7
+ vpsraw xmm6,xmm4,7
+ vpsrld xmm6,xmm4,7
+ vpsrldq xmm6,xmm4,7
+ vpsrlq xmm6,xmm4,7
+ vpsrlw xmm6,xmm4,7
# Tests for op imm8, xmm, regl
- vpextrw ecx,xmm4,100
+ vpextrw ecx,xmm4,7
# Tests for op ymm, regl
vmovmskpd ecx,ymm4
vmovmskps ecx,ymm4
-
# Default instructions without suffixes.
vcvtpd2dq xmm6,xmm4
vcvtpd2dq xmm6,ymm4
vcvtdq2pd ymm0,XMMWORD PTR ds:0x1234
vcvtpd2ps xmm0,YMMWORD PTR ds:0x1234
vpavgb xmm7,xmm0,XMMWORD PTR ds:0x1234
- vaeskeygenassist xmm0,XMMWORD PTR ds:0x1234,100
- vpextrb ds:0x1234,xmm0,100
+ vaeskeygenassist xmm0,XMMWORD PTR ds:0x1234,7
+ vpextrb ds:0x1234,xmm0,7
vcvtsi2sd xmm7,xmm0,DWORD PTR ds:0x1234
vblendvps xmm6,xmm4,XMMWORD PTR ds:0x1234,xmm0
- vpinsrb xmm7,xmm0,ds:0x1234,100
+ vpinsrb xmm7,xmm0,ds:0x1234,7
vmovdqa ymm0,YMMWORD PTR ds:0x1234
vmovdqa YMMWORD PTR ds:0x1234,ymm0
vpermilpd ymm7,ymm0,YMMWORD PTR ds:0x1234
- vroundpd ymm0,YMMWORD PTR ds:0x1234,100
- vextractf128 XMMWORD PTR ds:0x1234,ymm0,100
- vperm2f128 ymm7,ymm0,YMMWORD PTR ds:0x1234,100
+ vroundpd ymm0,YMMWORD PTR ds:0x1234,7
+ vextractf128 XMMWORD PTR ds:0x1234,ymm0,7
+ vperm2f128 ymm7,ymm0,YMMWORD PTR ds:0x1234,7
vblendvpd ymm6,ymm4,YMMWORD PTR ds:0x1234,ymm0
vldmxcsr DWORD PTR [ebp]
vmovdqa xmm0,XMMWORD PTR [ebp]
vcvtdq2pd ymm0,XMMWORD PTR [ebp]
vcvtpd2ps xmm0,YMMWORD PTR [ebp]
vpavgb xmm7,xmm0,XMMWORD PTR [ebp]
- vaeskeygenassist xmm0,XMMWORD PTR [ebp],100
- vpextrb [ebp],xmm0,100
+ vaeskeygenassist xmm0,XMMWORD PTR [ebp],7
+ vpextrb [ebp],xmm0,7
vcvtsi2sd xmm7,xmm0,DWORD PTR [ebp]
vblendvps xmm6,xmm4,XMMWORD PTR [ebp],xmm0
- vpinsrb xmm7,xmm0,[ebp],100
+ vpinsrb xmm7,xmm0,[ebp],7
vmovdqa ymm0,YMMWORD PTR [ebp]
vmovdqa YMMWORD PTR [ebp],ymm0
vpermilpd ymm7,ymm0,YMMWORD PTR [ebp]
- vroundpd ymm0,YMMWORD PTR [ebp],100
- vextractf128 XMMWORD PTR [ebp],ymm0,100
- vperm2f128 ymm7,ymm0,YMMWORD PTR [ebp],100
+ vroundpd ymm0,YMMWORD PTR [ebp],7
+ vextractf128 XMMWORD PTR [ebp],ymm0,7
+ vperm2f128 ymm7,ymm0,YMMWORD PTR [ebp],7
vblendvpd ymm6,ymm4,YMMWORD PTR [ebp],ymm0
vldmxcsr DWORD PTR [ebp+0x99]
vmovdqa xmm0,XMMWORD PTR [ebp+0x99]
vcvtdq2pd ymm0,XMMWORD PTR [ebp+0x99]
vcvtpd2ps xmm0,YMMWORD PTR [ebp+0x99]
vpavgb xmm7,xmm0,XMMWORD PTR [ebp+0x99]
- vaeskeygenassist xmm0,XMMWORD PTR [ebp+0x99],100
- vpextrb [ebp+0x99],xmm0,100
+ vaeskeygenassist xmm0,XMMWORD PTR [ebp+0x99],7
+ vpextrb [ebp+0x99],xmm0,7
vcvtsi2sd xmm7,xmm0,DWORD PTR [ebp+0x99]
vblendvps xmm6,xmm4,XMMWORD PTR [ebp+0x99],xmm0
- vpinsrb xmm7,xmm0,[ebp+0x99],100
+ vpinsrb xmm7,xmm0,[ebp+0x99],7
vmovdqa ymm0,YMMWORD PTR [ebp+0x99]
vmovdqa YMMWORD PTR [ebp+0x99],ymm0
vpermilpd ymm7,ymm0,YMMWORD PTR [ebp+0x99]
- vroundpd ymm0,YMMWORD PTR [ebp+0x99],100
- vextractf128 XMMWORD PTR [ebp+0x99],ymm0,100
- vperm2f128 ymm7,ymm0,YMMWORD PTR [ebp+0x99],100
+ vroundpd ymm0,YMMWORD PTR [ebp+0x99],7
+ vextractf128 XMMWORD PTR [ebp+0x99],ymm0,7
+ vperm2f128 ymm7,ymm0,YMMWORD PTR [ebp+0x99],7
vblendvpd ymm6,ymm4,YMMWORD PTR [ebp+0x99],ymm0
vldmxcsr DWORD PTR [eiz*1+0x99]
vmovdqa xmm0,XMMWORD PTR [eiz*1+0x99]
vcvtdq2pd ymm0,XMMWORD PTR [eiz*1+0x99]
vcvtpd2ps xmm0,YMMWORD PTR [eiz*1+0x99]
vpavgb xmm7,xmm0,XMMWORD PTR [eiz*1+0x99]
- vaeskeygenassist xmm0,XMMWORD PTR [eiz*1+0x99],100
- vpextrb [eiz*1+0x99],xmm0,100
+ vaeskeygenassist xmm0,XMMWORD PTR [eiz*1+0x99],7
+ vpextrb [eiz*1+0x99],xmm0,7
vcvtsi2sd xmm7,xmm0,DWORD PTR [eiz*1+0x99]
vblendvps xmm6,xmm4,XMMWORD PTR [eiz*1+0x99],xmm0
- vpinsrb xmm7,xmm0,[eiz*1+0x99],100
+ vpinsrb xmm7,xmm0,[eiz*1+0x99],7
vmovdqa ymm0,YMMWORD PTR [eiz*1+0x99]
vmovdqa YMMWORD PTR [eiz*1+0x99],ymm0
vpermilpd ymm7,ymm0,YMMWORD PTR [eiz*1+0x99]
- vroundpd ymm0,YMMWORD PTR [eiz*1+0x99],100
- vextractf128 XMMWORD PTR [eiz*1+0x99],ymm0,100
- vperm2f128 ymm7,ymm0,YMMWORD PTR [eiz*1+0x99],100
+ vroundpd ymm0,YMMWORD PTR [eiz*1+0x99],7
+ vextractf128 XMMWORD PTR [eiz*1+0x99],ymm0,7
+ vperm2f128 ymm7,ymm0,YMMWORD PTR [eiz*1+0x99],7
vblendvpd ymm6,ymm4,YMMWORD PTR [eiz*1+0x99],ymm0
vldmxcsr DWORD PTR [eiz*2+0x99]
vmovdqa xmm0,XMMWORD PTR [eiz*2+0x99]
vcvtdq2pd ymm0,XMMWORD PTR [eiz*2+0x99]
vcvtpd2ps xmm0,YMMWORD PTR [eiz*2+0x99]
vpavgb xmm7,xmm0,XMMWORD PTR [eiz*2+0x99]
- vaeskeygenassist xmm0,XMMWORD PTR [eiz*2+0x99],100
- vpextrb [eiz*2+0x99],xmm0,100
+ vaeskeygenassist xmm0,XMMWORD PTR [eiz*2+0x99],7
+ vpextrb [eiz*2+0x99],xmm0,7
vcvtsi2sd xmm7,xmm0,DWORD PTR [eiz*2+0x99]
vblendvps xmm6,xmm4,XMMWORD PTR [eiz*2+0x99],xmm0
- vpinsrb xmm7,xmm0,[eiz*2+0x99],100
+ vpinsrb xmm7,xmm0,[eiz*2+0x99],7
vmovdqa ymm0,YMMWORD PTR [eiz*2+0x99]
vmovdqa YMMWORD PTR [eiz*2+0x99],ymm0
vpermilpd ymm7,ymm0,YMMWORD PTR [eiz*2+0x99]
- vroundpd ymm0,YMMWORD PTR [eiz*2+0x99],100
- vextractf128 XMMWORD PTR [eiz*2+0x99],ymm0,100
- vperm2f128 ymm7,ymm0,YMMWORD PTR [eiz*2+0x99],100
+ vroundpd ymm0,YMMWORD PTR [eiz*2+0x99],7
+ vextractf128 XMMWORD PTR [eiz*2+0x99],ymm0,7
+ vperm2f128 ymm7,ymm0,YMMWORD PTR [eiz*2+0x99],7
vblendvpd ymm6,ymm4,YMMWORD PTR [eiz*2+0x99],ymm0
vldmxcsr DWORD PTR [eax+eiz*1+0x99]
vmovdqa xmm0,XMMWORD PTR [eax+eiz*1+0x99]
vcvtdq2pd ymm0,XMMWORD PTR [eax+eiz*1+0x99]
vcvtpd2ps xmm0,YMMWORD PTR [eax+eiz*1+0x99]
vpavgb xmm7,xmm0,XMMWORD PTR [eax+eiz*1+0x99]
- vaeskeygenassist xmm0,XMMWORD PTR [eax+eiz*1+0x99],100
- vpextrb [eax+eiz*1+0x99],xmm0,100
+ vaeskeygenassist xmm0,XMMWORD PTR [eax+eiz*1+0x99],7
+ vpextrb [eax+eiz*1+0x99],xmm0,7
vcvtsi2sd xmm7,xmm0,DWORD PTR [eax+eiz*1+0x99]
vblendvps xmm6,xmm4,XMMWORD PTR [eax+eiz*1+0x99],xmm0
- vpinsrb xmm7,xmm0,[eax+eiz*1+0x99],100
+ vpinsrb xmm7,xmm0,[eax+eiz*1+0x99],7
vmovdqa ymm0,YMMWORD PTR [eax+eiz*1+0x99]
vmovdqa YMMWORD PTR [eax+eiz*1+0x99],ymm0
vpermilpd ymm7,ymm0,YMMWORD PTR [eax+eiz*1+0x99]
- vroundpd ymm0,YMMWORD PTR [eax+eiz*1+0x99],100
- vextractf128 XMMWORD PTR [eax+eiz*1+0x99],ymm0,100
- vperm2f128 ymm7,ymm0,YMMWORD PTR [eax+eiz*1+0x99],100
+ vroundpd ymm0,YMMWORD PTR [eax+eiz*1+0x99],7
+ vextractf128 XMMWORD PTR [eax+eiz*1+0x99],ymm0,7
+ vperm2f128 ymm7,ymm0,YMMWORD PTR [eax+eiz*1+0x99],7
vblendvpd ymm6,ymm4,YMMWORD PTR [eax+eiz*1+0x99],ymm0
vldmxcsr DWORD PTR [eax+eiz*2+0x99]
vmovdqa xmm0,XMMWORD PTR [eax+eiz*2+0x99]
vcvtdq2pd ymm0,XMMWORD PTR [eax+eiz*2+0x99]
vcvtpd2ps xmm0,YMMWORD PTR [eax+eiz*2+0x99]
vpavgb xmm7,xmm0,XMMWORD PTR [eax+eiz*2+0x99]
- vaeskeygenassist xmm0,XMMWORD PTR [eax+eiz*2+0x99],100
- vpextrb [eax+eiz*2+0x99],xmm0,100
+ vaeskeygenassist xmm0,XMMWORD PTR [eax+eiz*2+0x99],7
+ vpextrb [eax+eiz*2+0x99],xmm0,7
vcvtsi2sd xmm7,xmm0,DWORD PTR [eax+eiz*2+0x99]
vblendvps xmm6,xmm4,XMMWORD PTR [eax+eiz*2+0x99],xmm0
- vpinsrb xmm7,xmm0,[eax+eiz*2+0x99],100
+ vpinsrb xmm7,xmm0,[eax+eiz*2+0x99],7
vmovdqa ymm0,YMMWORD PTR [eax+eiz*2+0x99]
vmovdqa YMMWORD PTR [eax+eiz*2+0x99],ymm0
vpermilpd ymm7,ymm0,YMMWORD PTR [eax+eiz*2+0x99]
- vroundpd ymm0,YMMWORD PTR [eax+eiz*2+0x99],100
- vextractf128 XMMWORD PTR [eax+eiz*2+0x99],ymm0,100
- vperm2f128 ymm7,ymm0,YMMWORD PTR [eax+eiz*2+0x99],100
+ vroundpd ymm0,YMMWORD PTR [eax+eiz*2+0x99],7
+ vextractf128 XMMWORD PTR [eax+eiz*2+0x99],ymm0,7
+ vperm2f128 ymm7,ymm0,YMMWORD PTR [eax+eiz*2+0x99],7
vblendvpd ymm6,ymm4,YMMWORD PTR [eax+eiz*2+0x99],ymm0
vldmxcsr DWORD PTR [eax+ebx*4+0x99]
vmovdqa xmm0,XMMWORD PTR [eax+ebx*4+0x99]
vcvtdq2pd ymm0,XMMWORD PTR [eax+ebx*4+0x99]
vcvtpd2ps xmm0,YMMWORD PTR [eax+ebx*4+0x99]
vpavgb xmm7,xmm0,XMMWORD PTR [eax+ebx*4+0x99]
- vaeskeygenassist xmm0,XMMWORD PTR [eax+ebx*4+0x99],100
- vpextrb [eax+ebx*4+0x99],xmm0,100
+ vaeskeygenassist xmm0,XMMWORD PTR [eax+ebx*4+0x99],7
+ vpextrb [eax+ebx*4+0x99],xmm0,7
vcvtsi2sd xmm7,xmm0,DWORD PTR [eax+ebx*4+0x99]
vblendvps xmm6,xmm4,XMMWORD PTR [eax+ebx*4+0x99],xmm0
- vpinsrb xmm7,xmm0,[eax+ebx*4+0x99],100
+ vpinsrb xmm7,xmm0,[eax+ebx*4+0x99],7
vmovdqa ymm0,YMMWORD PTR [eax+ebx*4+0x99]
vmovdqa YMMWORD PTR [eax+ebx*4+0x99],ymm0
vpermilpd ymm7,ymm0,YMMWORD PTR [eax+ebx*4+0x99]
- vroundpd ymm0,YMMWORD PTR [eax+ebx*4+0x99],100
- vextractf128 XMMWORD PTR [eax+ebx*4+0x99],ymm0,100
- vperm2f128 ymm7,ymm0,YMMWORD PTR [eax+ebx*4+0x99],100
+ vroundpd ymm0,YMMWORD PTR [eax+ebx*4+0x99],7
+ vextractf128 XMMWORD PTR [eax+ebx*4+0x99],ymm0,7
+ vperm2f128 ymm7,ymm0,YMMWORD PTR [eax+ebx*4+0x99],7
vblendvpd ymm6,ymm4,YMMWORD PTR [eax+ebx*4+0x99],ymm0
vldmxcsr DWORD PTR [esp+ecx*8+0x99]
vmovdqa xmm0,XMMWORD PTR [esp+ecx*8+0x99]
vcvtdq2pd ymm0,XMMWORD PTR [esp+ecx*8+0x99]
vcvtpd2ps xmm0,YMMWORD PTR [esp+ecx*8+0x99]
vpavgb xmm7,xmm0,XMMWORD PTR [esp+ecx*8+0x99]
- vaeskeygenassist xmm0,XMMWORD PTR [esp+ecx*8+0x99],100
- vpextrb [esp+ecx*8+0x99],xmm0,100
+ vaeskeygenassist xmm0,XMMWORD PTR [esp+ecx*8+0x99],7
+ vpextrb [esp+ecx*8+0x99],xmm0,7
vcvtsi2sd xmm7,xmm0,DWORD PTR [esp+ecx*8+0x99]
vblendvps xmm6,xmm4,XMMWORD PTR [esp+ecx*8+0x99],xmm0
- vpinsrb xmm7,xmm0,[esp+ecx*8+0x99],100
+ vpinsrb xmm7,xmm0,[esp+ecx*8+0x99],7
vmovdqa ymm0,YMMWORD PTR [esp+ecx*8+0x99]
vmovdqa YMMWORD PTR [esp+ecx*8+0x99],ymm0
vpermilpd ymm7,ymm0,YMMWORD PTR [esp+ecx*8+0x99]
- vroundpd ymm0,YMMWORD PTR [esp+ecx*8+0x99],100
- vextractf128 XMMWORD PTR [esp+ecx*8+0x99],ymm0,100
- vperm2f128 ymm7,ymm0,YMMWORD PTR [esp+ecx*8+0x99],100
+ vroundpd ymm0,YMMWORD PTR [esp+ecx*8+0x99],7
+ vextractf128 XMMWORD PTR [esp+ecx*8+0x99],ymm0,7
+ vperm2f128 ymm7,ymm0,YMMWORD PTR [esp+ecx*8+0x99],7
vblendvpd ymm6,ymm4,YMMWORD PTR [esp+ecx*8+0x99],ymm0
vldmxcsr DWORD PTR [ebp+edx*1+0x99]
vmovdqa xmm0,XMMWORD PTR [ebp+edx*1+0x99]
vcvtdq2pd ymm0,XMMWORD PTR [ebp+edx*1+0x99]
vcvtpd2ps xmm0,YMMWORD PTR [ebp+edx*1+0x99]
vpavgb xmm7,xmm0,XMMWORD PTR [ebp+edx*1+0x99]
- vaeskeygenassist xmm0,XMMWORD PTR [ebp+edx*1+0x99],100
- vpextrb [ebp+edx*1+0x99],xmm0,100
+ vaeskeygenassist xmm0,XMMWORD PTR [ebp+edx*1+0x99],7
+ vpextrb [ebp+edx*1+0x99],xmm0,7
vcvtsi2sd xmm7,xmm0,DWORD PTR [ebp+edx*1+0x99]
vblendvps xmm6,xmm4,XMMWORD PTR [ebp+edx*1+0x99],xmm0
- vpinsrb xmm7,xmm0,[ebp+edx*1+0x99],100
+ vpinsrb xmm7,xmm0,[ebp+edx*1+0x99],7
vmovdqa ymm0,YMMWORD PTR [ebp+edx*1+0x99]
vmovdqa YMMWORD PTR [ebp+edx*1+0x99],ymm0
vpermilpd ymm7,ymm0,YMMWORD PTR [ebp+edx*1+0x99]
- vroundpd ymm0,YMMWORD PTR [ebp+edx*1+0x99],100
- vextractf128 XMMWORD PTR [ebp+edx*1+0x99],ymm0,100
- vperm2f128 ymm7,ymm0,YMMWORD PTR [ebp+edx*1+0x99],100
+ vroundpd ymm0,YMMWORD PTR [ebp+edx*1+0x99],7
+ vextractf128 XMMWORD PTR [ebp+edx*1+0x99],ymm0,7
+ vperm2f128 ymm7,ymm0,YMMWORD PTR [ebp+edx*1+0x99],7
vblendvpd ymm6,ymm4,YMMWORD PTR [ebp+edx*1+0x99],ymm0
# Tests for all register operands.
vmovmskpd eax,xmm0
- vpslld xmm7,xmm0,100
+ vpslld xmm7,xmm0,7
vmovmskps eax,ymm0
run_dump_test "opts-intel"
run_dump_test "sse2avx-opts"
run_dump_test "sse2avx-opts-intel"
+ run_dump_test "fma"
+ run_dump_test "fma-intel"
# These tests require support for 8 and 16 bit relocs,
# so we only run them for ELF and COFF targets.
run_dump_test "x86-64-sse2avx-opts-intel"
run_dump_test "x86-64-avx-swap"
run_dump_test "x86-64-avx-swap-intel"
+ run_dump_test "x86-64-fma"
+ run_dump_test "x86-64-fma-intel"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-beos*"]
.*:4: Error: .*
.*:5: Error: .*
.*:6: Error: .*
-.*:7: Error: .*
-.*:8: Error: .*
.*:9: Error: .*
.*:10: Error: .*
.*:11: Error: .*
-.*:12: Error: .*
-.*:13: Error: .*
-.*:14: Error: .*
-.*:15: Error: .*
-.*:16: Error: .*
-.*:17: Error: .*
-.*:18: Error: .*
-.*:19: Error: .*
-.*:20: Error: .*
-.*:21: Error: .*
-.*:22: Error: .*
-.*:23: Error: .*
-.*:24: Error: .*
-.*:25: Error: .*
-.*:26: Error: .*
-.*:27: Error: .*
-.*:28: Error: .*
-.*:31: Error: .*
-.*:32: Error: .*
-.*:33: Error: .*
-.*:34: Error: .*
-.*:35: Error: .*
-.*:36: Error: .*
-.*:37: Error: .*
-.*:38: Error: .*
-.*:39: Error: .*
-.*:40: Error: .*
-.*:41: Error: .*
-.*:42: Error: .*
-.*:43: Error: .*
-.*:44: Error: .*
-.*:45: Error: .*
-.*:46: Error: .*
-.*:47: Error: .*
-.*:48: Error: .*
-.*:49: Error: .*
-.*:50: Error: .*
-.*:51: Error: .*
-.*:52: Error: .*
-.*:53: Error: .*
-.*:54: Error: .*
-.*:55: Error: .*
GAS LISTING .*
[ ]*4[ ]+vcvtpd2dq \(%ecx\),%xmm2
[ ]*5[ ]+vcvtpd2ps \(%ecx\),%xmm2
[ ]*6[ ]+vcvttpd2dq \(%ecx\),%xmm2
-[ ]*7[ ]+vfmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*8[ ]+vfmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*9[ ]+vfmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*10[ ]+vfmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*11[ ]+vfmaddsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*12[ ]+vfmaddsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*13[ ]+vfmsubaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*14[ ]+vfmsubaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*15[ ]+vfmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*16[ ]+vfmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*17[ ]+vfmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*18[ ]+vfmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*19[ ]+vfnmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*20[ ]+vfnmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*21[ ]+vfnmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*22[ ]+vfnmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*23[ ]+vfnmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*24[ ]+vfnmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*25[ ]+vfnmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*26[ ]+vfnmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*27[ ]+vpermil2pd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*28[ ]+vpermil2ps \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*29[ ]+
-[ ]*30[ ]+\.intel_syntax noprefix
-[ ]*31[ ]+vcvtpd2dq xmm2,\[ecx\]
-[ ]*32[ ]+vcvtpd2ps xmm2,\[ecx\]
-[ ]*33[ ]+vcvttpd2dq xmm2,\[ecx\]
-[ ]*34[ ]+vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*35[ ]+vfmaddps xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*36[ ]+vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*37[ ]+vfmaddss xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*38[ ]+vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*39[ ]+vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*40[ ]+vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*41[ ]+vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*42[ ]+vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*43[ ]+vfmsubps xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*44[ ]+vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*45[ ]+vfmsubss xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*46[ ]+vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*47[ ]+vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*48[ ]+vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*49[ ]+vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*50[ ]+vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*51[ ]+vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*52[ ]+vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*53[ ]+vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*54[ ]+vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*55[ ]+vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10
+[ ]*7[ ]+
+[ ]*8[ ]+\.intel_syntax noprefix
+[ ]*9[ ]+vcvtpd2dq xmm2,\[ecx\]
+[ ]*10[ ]+vcvtpd2ps xmm2,\[ecx\]
+[ ]*11[ ]+vcvttpd2dq xmm2,\[ecx\]
vcvtpd2dq (%ecx),%xmm2
vcvtpd2ps (%ecx),%xmm2
vcvttpd2dq (%ecx),%xmm2
- vfmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmaddsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmaddsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmsubaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmsubaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3
- vpermil2pd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vpermil2ps $17,%xmm4,%xmm2,%xmm1,%xmm3
.intel_syntax noprefix
vcvtpd2dq xmm2,[ecx]
vcvtpd2ps xmm2,[ecx]
vcvttpd2dq xmm2,[ecx]
- vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10
- vfmaddps xmm3,xmm1,xmm2,xmm4,0x10
- vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10
- vfmaddss xmm3,xmm1,xmm2,xmm4,0x10
- vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10
- vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10
- vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10
- vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10
- vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10
- vfmsubps xmm3,xmm1,xmm2,xmm4,0x10
- vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10
- vfmsubss xmm3,xmm1,xmm2,xmm4,0x10
- vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10
- vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10
- vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10
- vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10
- vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10
- vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10
- vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10
- vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10
- vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10
- vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%rcx\),%xmm0
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
[ ]*[a-f0-9]+: c4 e2 79 dc 11 vaesenc \(%rcx\),%xmm0,%xmm2
-[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
+[ ]*[a-f0-9]+: c4 e2 c9 98 d4 vfmadd132pd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 0f 38 f0 19 movbe \(%rcx\),%ebx
[ ]*[a-f0-9]+: 66 0f 38 80 19 invept \(%rcx\),%rbx
[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
# AES + AVX
vaesenc (%rcx),%xmm0,%xmm2
# FMA
-vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
+vfmadd132pd %xmm4,%xmm6,%xmm2
# MOVBE
movbe (%rcx),%ebx
# EPT
[ ]*[a-f0-9]+: c4 e2 4d 2f 21 vmaskmovpd YMMWORD PTR \[rcx\],ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps ymm6,ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps YMMWORD PTR \[rcx\],ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps ymm6,YMMWORD PTR \[rcx\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 05 d6 07 vpermilpd ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 05 31 07 vpermilpd ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 04 d6 07 vpermilps ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 04 31 07 vpermilps ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 09 d6 07 vroundpd ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 09 31 07 vroundpd ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 08 d6 07 vroundps ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 08 31 07 vroundps ymm6,YMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd ymm2,ymm6,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 cc 58 d4 vaddps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2ps xmm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq xmm4,ymm4
[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dq xmm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 5b f4 vcvtdq2ps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 5b f4 vcvtps2dq ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 5b f4 vcvttps2dq ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup ymm4,ymm4
+[ ]*[a-f0-9]+: c5 ff 12 f4 vmovddup ymm6,ymm4
[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 16 f4 vmovshdup ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 12 f4 vmovsldup ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 10 21 vmovups ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest ymm4,ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 17 f4 vptest ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 53 f4 vrcpps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 52 f4 vrsqrtps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 51 f4 vsqrtpd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 51 f4 vsqrtps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd ymm4,ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0f f4 vtestpd ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps ymm4,ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0e f4 vtestps ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu ymm4,\[rcx\]
-[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
+[ ]*[a-f0-9]+: c4 e3 4d 0d d4 07 vblendpd ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0d 11 07 vblendpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0c d4 07 vblendps ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0c 11 07 vblendps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd ymm2,ymm6,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps ymm2,ymm6,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e3 4d 40 d4 07 vdpps ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 40 11 07 vdpps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 06 d4 07 vperm2f128 ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 06 11 07 vperm2f128 ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 cd c6 d4 07 vshufpd ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps ymm7,ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 69 39 20 vfmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 68 fc 20 vfmaddps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 68 39 20 vfmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5d fc 20 vfmaddsubpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5d 39 20 vfmaddsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5c fc 20 vfmaddsubps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5c 39 20 vfmaddsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5f fc 20 vfmsubaddpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5f 39 20 vfmsubaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5e fc 20 vfmsubaddps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5e 39 20 vfmsubaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 6d fc 20 vfmsubpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 6d 39 20 vfmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 6c fc 20 vfmsubps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 6c 39 20 vfmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 79 fc 20 vfnmaddpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 79 39 20 vfnmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 78 fc 20 vfnmaddps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 78 39 20 vfnmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 7d fc 20 vfnmsubpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 7d 39 20 vfnmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 7c fc 20 vfnmsubps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 7c 39 20 vfnmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd ymm7,ymm2,ymm6,ymm4,0xa
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\],0xa
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps ymm7,ymm2,ymm6,ymm4,0xa
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\],0xa
-[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 ymm6,ymm4,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 ymm6,ymm4,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 xmm4,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 XMMWORD PTR \[rcx\],ymm4,0x64
+[ ]*[a-f0-9]+: c4 e3 5d 18 f4 07 vinsertf128 ymm6,ymm4,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 5d 18 31 07 vinsertf128 ymm6,ymm4,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 e4 07 vextractf128 xmm4,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 21 07 vextractf128 XMMWORD PTR \[rcx\],ymm4,0x7
[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 ymm4,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps xmm6,xmm4
[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps xmm4,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 79 df f4 64 vaeskeygenassist xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 df 31 64 vaeskeygenassist xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps xmm6,XMMWORD PTR \[rcx\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 df 31 07 vaeskeygenassist xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 61 f4 07 vpcmpestri xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 61 31 07 vpcmpestri xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 60 f4 07 vpcmpestrm xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 60 31 07 vpcmpestrm xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 63 f4 07 vpcmpistri xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 63 31 07 vpcmpistri xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 62 f4 07 vpcmpistrm xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 62 31 07 vpcmpistrm xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 05 f4 07 vpermilpd xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 05 31 07 vpermilpd xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 04 f4 07 vpermilps xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 04 31 07 vpermilps xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 f9 70 f4 07 vpshufd xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 f9 70 31 07 vpshufd xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 fa 70 f4 07 vpshufhw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 fa 70 31 07 vpshufhw xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 fb 70 f4 07 vpshuflw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 fb 70 31 07 vpshuflw xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 09 f4 07 vroundpd xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 09 31 07 vroundpd xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 08 f4 07 vroundps xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 08 31 07 vroundps xmm6,XMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps XMMWORD PTR \[rcx\],xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd XMMWORD PTR \[rcx\],xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
+[ ]*[a-f0-9]+: c4 e3 49 0d d4 07 vblendpd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0d 11 07 vblendpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0c d4 07 vblendps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0c 11 07 vblendps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 c9 c2 11 07 vcmpordpd xmm2,xmm6,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 c8 c2 11 07 vcmpordps xmm2,xmm6,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e3 49 41 d4 07 vdppd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 41 11 07 vdppd xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 40 d4 07 vdpps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 40 11 07 vdpps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 42 d4 07 vmpsadbw xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 42 11 07 vmpsadbw xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0f d4 07 vpalignr xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0f 11 07 vpalignr xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0e d4 07 vpblendw xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0e 11 07 vpblendw xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 c9 c6 d4 07 vshufpd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps xmm7,xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c4 e3 69 4a 39 40 vblendvps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb xmm7,xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 69 fc 20 vfmaddpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 69 39 20 vfmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 69 39 20 vfmaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 68 fc 20 vfmaddps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 68 39 20 vfmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 68 39 20 vfmaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5d fc 20 vfmaddsubpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5d 39 20 vfmaddsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 5d 39 20 vfmaddsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5c fc 20 vfmaddsubps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5c 39 20 vfmaddsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 5c 39 20 vfmaddsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5f fc 20 vfmsubaddpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5f 39 20 vfmsubaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 5f 39 20 vfmsubaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5e fc 20 vfmsubaddps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5e 39 20 vfmsubaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 5e 39 20 vfmsubaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6d fc 20 vfmsubpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6d 39 20 vfmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6d 39 20 vfmsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6c fc 20 vfmsubps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6c 39 20 vfmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6c 39 20 vfmsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 79 fc 20 vfnmaddpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 79 39 20 vfnmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 79 39 20 vfnmaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 78 fc 20 vfnmaddps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 78 39 20 vfnmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 78 39 20 vfnmaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7d fc 20 vfnmsubpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7d 39 20 vfnmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7d 39 20 vfnmsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7c fc 20 vfnmsubps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7c 39 20 vfnmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7c 39 20 vfnmsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd xmm7,xmm2,xmm6,xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\],0xa
-[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps xmm7,xmm2,xmm6,xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\],0xa
-[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4,0xa
[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd ymm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd xmm6,xmm4
[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e1 db 2a 31 vcvtsi2sd xmm6,xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e1 da 2a f1 vcvtsi2ss xmm6,xmm4,rcx
[ ]*[a-f0-9]+: c4 e1 da 2a 31 vcvtsi2ss xmm6,xmm4,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 d9 22 f1 64 vpinsrq xmm6,xmm4,rcx,0x64
-[ ]*[a-f0-9]+: c4 e3 d9 22 31 64 vpinsrq xmm6,xmm4,QWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 f9 16 e1 64 vpextrq rcx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 f9 16 21 64 vpextrq QWORD PTR \[rcx\],xmm4,0x64
+[ ]*[a-f0-9]+: c4 e3 d9 22 f1 07 vpinsrq xmm6,xmm4,rcx,0x7
+[ ]*[a-f0-9]+: c4 e3 d9 22 31 07 vpinsrq xmm6,xmm4,QWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 f9 16 e1 07 vpextrq rcx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 f9 16 21 07 vpextrq QWORD PTR \[rcx\],xmm4,0x7
[ ]*[a-f0-9]+: c5 d9 12 31 vmovlpd xmm6,xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 d8 12 31 vmovlps xmm6,xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd xmm6,xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps xmm6,xmm4,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd xmm2,xmm6,QWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd xmm2,xmm6,QWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 c9 6b fc 20 vfmaddsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6b 39 20 vfmaddsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6b 39 20 vfmaddsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6f fc 20 vfmsubsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6f 39 20 vfmsubsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6f 39 20 vfmsubsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7b fc 20 vfnmaddsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7b 39 20 vfnmaddsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7b 39 20 vfnmaddsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7f fc 20 vfnmsubsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7f 39 20 vfnmsubsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7f 39 20 vfnmsubsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4
+[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd xmm2,xmm6,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e3 49 0b d4 07 vroundsd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0b 11 07 vroundsd xmm2,xmm6,QWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd xmm2,xmm6,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 cb 5a d4 vcvtsd2ss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 1e vcmpgt_oqsd xmm2,xmm6,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd xmm2,xmm6,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr DWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca 58 11 vaddss xmm2,xmm6,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 ca 5a d4 vcvtss2sd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd ecx,xmm4
[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps ecx,xmm4
[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb ecx,xmm4
-[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd DWORD PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[rcx\],xmm4,0x64
+[ ]*[a-f0-9]+: c4 e3 79 17 e1 07 vextractps ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps DWORD PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 16 e1 07 vpextrd ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 16 21 07 vpextrd DWORD PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 17 e1 07 vextractps ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps DWORD PTR \[rcx\],xmm4,0x7
[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd xmm6,xmm4,ecx
[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sd xmm6,xmm4,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss xmm6,xmm4,ecx
[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ss xmm6,xmm4,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss xmm2,xmm6,DWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps xmm2,xmm6,DWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss xmm2,xmm6,DWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 c9 6a fc 20 vfmaddss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6a 39 20 vfmaddss xmm7,xmm2,xmm6,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6a 39 20 vfmaddss xmm7,xmm2,DWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6e fc 20 vfmsubss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6e 39 20 vfmsubss xmm7,xmm2,xmm6,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6e 39 20 vfmsubss xmm7,xmm2,DWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7a fc 20 vfnmaddss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7a 39 20 vfnmaddss xmm7,xmm2,xmm6,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7a 39 20 vfnmaddss xmm7,xmm2,DWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7e fc 20 vfnmsubss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7e 39 20 vfnmsubss xmm7,xmm2,xmm6,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7e 39 20 vfnmsubss xmm7,xmm2,DWORD PTR \[rcx\],xmm4
+[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss xmm2,xmm6,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e3 49 21 d4 07 vinsertps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 21 11 07 vinsertps xmm2,xmm6,DWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0a d4 07 vroundss xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0a 11 07 vroundss xmm2,xmm6,DWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq xmm4,WORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq xmm4,WORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw xmm6,xmm4,ecx,0x64
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw xmm6,xmm4,ecx,0x64
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x64
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw WORD PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw WORD PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c5 d9 c4 f1 07 vpinsrw xmm6,xmm4,ecx,0x7
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 d9 c4 f1 07 vpinsrw xmm6,xmm4,ecx,0x7
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 e1 07 vpextrb ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb BYTE PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb xmm6,xmm4,ecx,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 e1 07 vpextrb ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb BYTE PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb xmm6,xmm4,ecx,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu xmm6,xmm4
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd ecx,xmm4
[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64
+[ ]*[a-f0-9]+: c5 c9 72 f4 07 vpslld xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 fc 07 vpslldq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 f4 07 vpsllq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 71 f4 07 vpsllw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 72 e4 07 vpsrad xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 71 e4 07 vpsraw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 72 d4 07 vpsrld xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 dc 07 vpsrldq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 d4 07 vpsrlq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 71 d4 07 vpsrlw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw ecx,xmm4,0x7
[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd ecx,ymm4
[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps ecx,ymm4
[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd ecx,ymm4
[ ]*[a-f0-9]+: c5 7e e6 04 25 78 56 34 12 vcvtdq2pd ymm8,XMMWORD PTR ds:0x12345678
[ ]*[a-f0-9]+: c5 7d 5a 04 25 78 56 34 12 vcvtpd2ps xmm8,YMMWORD PTR ds:0x12345678
[ ]*[a-f0-9]+: c5 39 e0 3c 25 78 56 34 12 vpavgb xmm15,xmm8,XMMWORD PTR ds:0x12345678
-[ ]*[a-f0-9]+: c4 63 79 df 04 25 78 56 34 12 64 vaeskeygenassist xmm8,XMMWORD PTR ds:0x12345678,0x64
-[ ]*[a-f0-9]+: c4 63 79 14 04 25 78 56 34 12 64 vpextrb BYTE PTR ds:0x12345678,xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 04 25 78 56 34 12 07 vaeskeygenassist xmm8,XMMWORD PTR ds:0x12345678,0x7
+[ ]*[a-f0-9]+: c4 63 79 14 04 25 78 56 34 12 07 vpextrb BYTE PTR ds:0x12345678,xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a 3c 25 78 56 34 12 vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0x12345678
[ ]*[a-f0-9]+: c4 63 19 4a 34 25 78 56 34 12 80 vblendvps xmm14,xmm12,XMMWORD PTR ds:0x12345678,xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 3c 25 78 56 34 12 64 vpinsrb xmm15,xmm8,BYTE PTR ds:0x12345678,0x64
+[ ]*[a-f0-9]+: c4 63 39 20 3c 25 78 56 34 12 07 vpinsrb xmm15,xmm8,BYTE PTR ds:0x12345678,0x7
[ ]*[a-f0-9]+: c5 7d 6f 04 25 78 56 34 12 vmovdqa ymm8,YMMWORD PTR ds:0x12345678
[ ]*[a-f0-9]+: c5 7d 7f 04 25 78 56 34 12 vmovdqa YMMWORD PTR ds:0x12345678,ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 78 56 34 12 vpermilpd ymm15,ymm8,YMMWORD PTR ds:0x12345678
-[ ]*[a-f0-9]+: c4 63 7d 09 04 25 78 56 34 12 64 vroundpd ymm8,YMMWORD PTR ds:0x12345678,0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 04 25 78 56 34 12 64 vextractf128 XMMWORD PTR ds:0x12345678,ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 78 56 34 12 64 vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0x12345678,0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 04 25 78 56 34 12 07 vroundpd ymm8,YMMWORD PTR ds:0x12345678,0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 04 25 78 56 34 12 07 vextractf128 XMMWORD PTR ds:0x12345678,ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 78 56 34 12 07 vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0x12345678,0x7
[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 78 56 34 12 80 vblendvpd ymm14,ymm12,YMMWORD PTR ds:0x12345678,ymm8
[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr DWORD PTR \[rbp\+0x0\]
[ ]*[a-f0-9]+: c5 79 6f 45 00 vmovdqa xmm8,XMMWORD PTR \[rbp\+0x0\]
[ ]*[a-f0-9]+: c5 7e e6 45 00 vcvtdq2pd ymm8,XMMWORD PTR \[rbp\+0x0\]
[ ]*[a-f0-9]+: c5 7d 5a 45 00 vcvtpd2ps xmm8,YMMWORD PTR \[rbp\+0x0\]
[ ]*[a-f0-9]+: c5 39 e0 7d 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rbp\+0x0\]
-[ ]*[a-f0-9]+: c4 63 79 df 45 00 64 vaeskeygenassist xmm8,XMMWORD PTR \[rbp\+0x0\],0x64
-[ ]*[a-f0-9]+: c4 63 79 14 45 00 64 vpextrb BYTE PTR \[rbp\+0x0\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 45 00 07 vaeskeygenassist xmm8,XMMWORD PTR \[rbp\+0x0\],0x7
+[ ]*[a-f0-9]+: c4 63 79 14 45 00 07 vpextrb BYTE PTR \[rbp\+0x0\],xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a 7d 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+0x0\]
[ ]*[a-f0-9]+: c4 63 19 4a 75 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbp\+0x0\],xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 7d 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+0x0\],0x64
+[ ]*[a-f0-9]+: c4 63 39 20 7d 00 07 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+0x0\],0x7
[ ]*[a-f0-9]+: c5 7d 6f 45 00 vmovdqa ymm8,YMMWORD PTR \[rbp\+0x0\]
[ ]*[a-f0-9]+: c5 7d 7f 45 00 vmovdqa YMMWORD PTR \[rbp\+0x0\],ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d 7d 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rbp\+0x0\]
-[ ]*[a-f0-9]+: c4 63 7d 09 45 00 64 vroundpd ymm8,YMMWORD PTR \[rbp\+0x0\],0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 45 00 64 vextractf128 XMMWORD PTR \[rbp\+0x0\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 7d 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+0x0\],0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 45 00 07 vroundpd ymm8,YMMWORD PTR \[rbp\+0x0\],0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 45 00 07 vextractf128 XMMWORD PTR \[rbp\+0x0\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 7d 00 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+0x0\],0x7
[ ]*[a-f0-9]+: c4 63 1d 4b 75 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbp\+0x0\],ymm8
[ ]*[a-f0-9]+: c5 f8 ae 14 24 vldmxcsr DWORD PTR \[rsp\]
[ ]*[a-f0-9]+: c5 79 6f 04 24 vmovdqa xmm8,XMMWORD PTR \[rsp\]
[ ]*[a-f0-9]+: c5 7e e6 04 24 vcvtdq2pd ymm8,XMMWORD PTR \[rsp\]
[ ]*[a-f0-9]+: c5 7d 5a 04 24 vcvtpd2ps xmm8,YMMWORD PTR \[rsp\]
[ ]*[a-f0-9]+: c5 39 e0 3c 24 vpavgb xmm15,xmm8,XMMWORD PTR \[rsp\]
-[ ]*[a-f0-9]+: c4 63 79 df 04 24 64 vaeskeygenassist xmm8,XMMWORD PTR \[rsp\],0x64
-[ ]*[a-f0-9]+: c4 63 79 14 04 24 64 vpextrb BYTE PTR \[rsp\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 04 24 07 vaeskeygenassist xmm8,XMMWORD PTR \[rsp\],0x7
+[ ]*[a-f0-9]+: c4 63 79 14 04 24 07 vpextrb BYTE PTR \[rsp\],xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a 3c 24 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\]
[ ]*[a-f0-9]+: c4 63 19 4a 34 24 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rsp\],xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 3c 24 64 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\],0x64
+[ ]*[a-f0-9]+: c4 63 39 20 3c 24 07 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\],0x7
[ ]*[a-f0-9]+: c5 7d 6f 04 24 vmovdqa ymm8,YMMWORD PTR \[rsp\]
[ ]*[a-f0-9]+: c5 7d 7f 04 24 vmovdqa YMMWORD PTR \[rsp\],ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d 3c 24 vpermilpd ymm15,ymm8,YMMWORD PTR \[rsp\]
-[ ]*[a-f0-9]+: c4 63 7d 09 04 24 64 vroundpd ymm8,YMMWORD PTR \[rsp\],0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 04 24 64 vextractf128 XMMWORD PTR \[rsp\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 3c 24 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\],0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 04 24 07 vroundpd ymm8,YMMWORD PTR \[rsp\],0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 04 24 07 vextractf128 XMMWORD PTR \[rsp\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 3c 24 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\],0x7
[ ]*[a-f0-9]+: c4 63 1d 4b 34 24 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rsp\],ymm8
[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr DWORD PTR \[rbp\+0x99\]
[ ]*[a-f0-9]+: c5 79 6f 85 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[rbp\+0x99\]
[ ]*[a-f0-9]+: c5 7e e6 85 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[rbp\+0x99\]
[ ]*[a-f0-9]+: c5 7d 5a 85 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[rbp\+0x99\]
[ ]*[a-f0-9]+: c5 39 e0 bd 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rbp\+0x99\]
-[ ]*[a-f0-9]+: c4 63 79 df 85 99 00 00 00 64 vaeskeygenassist xmm8,XMMWORD PTR \[rbp\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 79 14 85 99 00 00 00 64 vpextrb BYTE PTR \[rbp\+0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 85 99 00 00 00 07 vaeskeygenassist xmm8,XMMWORD PTR \[rbp\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 79 14 85 99 00 00 00 07 vpextrb BYTE PTR \[rbp\+0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a bd 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+0x99\]
[ ]*[a-f0-9]+: c4 63 19 4a b5 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbp\+0x99\],xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 bd 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 39 20 bd 99 00 00 00 07 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+0x99\],0x7
[ ]*[a-f0-9]+: c5 7d 6f 85 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[rbp\+0x99\]
[ ]*[a-f0-9]+: c5 7d 7f 85 99 00 00 00 vmovdqa YMMWORD PTR \[rbp\+0x99\],ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d bd 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rbp\+0x99\]
-[ ]*[a-f0-9]+: c4 63 7d 09 85 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[rbp\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 85 99 00 00 00 64 vextractf128 XMMWORD PTR \[rbp\+0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 bd 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 85 99 00 00 00 07 vroundpd ymm8,YMMWORD PTR \[rbp\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 85 99 00 00 00 07 vextractf128 XMMWORD PTR \[rbp\+0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 bd 99 00 00 00 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+0x99\],0x7
[ ]*[a-f0-9]+: c4 63 1d 4b b5 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbp\+0x99\],ymm8
[ ]*[a-f0-9]+: c4 c1 78 ae 97 99 00 00 00 vldmxcsr DWORD PTR \[r15\+0x99\]
[ ]*[a-f0-9]+: c4 41 79 6f 87 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[r15\+0x99\]
[ ]*[a-f0-9]+: c4 41 7e e6 87 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[r15\+0x99\]
[ ]*[a-f0-9]+: c4 41 7d 5a 87 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[r15\+0x99\]
[ ]*[a-f0-9]+: c4 41 39 e0 bf 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[r15\+0x99\]
-[ ]*[a-f0-9]+: c4 43 79 df 87 99 00 00 00 64 vaeskeygenassist xmm8,XMMWORD PTR \[r15\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 43 79 14 87 99 00 00 00 64 vpextrb BYTE PTR \[r15\+0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 43 79 df 87 99 00 00 00 07 vaeskeygenassist xmm8,XMMWORD PTR \[r15\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 43 79 14 87 99 00 00 00 07 vpextrb BYTE PTR \[r15\+0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c4 41 3b 2a bf 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[r15\+0x99\]
[ ]*[a-f0-9]+: c4 43 19 4a b7 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r15\+0x99\],xmm8
-[ ]*[a-f0-9]+: c4 43 39 20 bf 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[r15\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 43 39 20 bf 99 00 00 00 07 vpinsrb xmm15,xmm8,BYTE PTR \[r15\+0x99\],0x7
[ ]*[a-f0-9]+: c4 41 7d 6f 87 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[r15\+0x99\]
[ ]*[a-f0-9]+: c4 41 7d 7f 87 99 00 00 00 vmovdqa YMMWORD PTR \[r15\+0x99\],ymm8
[ ]*[a-f0-9]+: c4 42 3d 0d bf 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[r15\+0x99\]
-[ ]*[a-f0-9]+: c4 43 7d 09 87 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[r15\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 43 7d 19 87 99 00 00 00 64 vextractf128 XMMWORD PTR \[r15\+0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 43 3d 06 bf 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r15\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 43 7d 09 87 99 00 00 00 07 vroundpd ymm8,YMMWORD PTR \[r15\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 43 7d 19 87 99 00 00 00 07 vextractf128 XMMWORD PTR \[r15\+0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 43 3d 06 bf 99 00 00 00 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r15\+0x99\],0x7
[ ]*[a-f0-9]+: c4 43 1d 4b b7 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r15\+0x99\],ymm8
-[ ]*[a-f0-9]+: c5 f8 ae 15 99 00 00 00 vldmxcsr DWORD PTR \[rip\+0x99\] # 1a9c <_start\+0x1a9c>
-[ ]*[a-f0-9]+: c5 79 6f 05 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[rip\+0x99\] # 1aa4 <_start\+0x1aa4>
-[ ]*[a-f0-9]+: c5 79 7f 05 99 00 00 00 vmovdqa XMMWORD PTR \[rip\+0x99\],xmm8 # 1aac <_start\+0x1aac>
-[ ]*[a-f0-9]+: c5 79 7e 05 99 00 00 00 vmovd DWORD PTR \[rip\+0x99\],xmm8 # 1ab4 <_start\+0x1ab4>
-[ ]*[a-f0-9]+: c5 7b 2d 05 99 00 00 00 vcvtsd2si r8d,QWORD PTR \[rip\+0x99\] # 1abc <_start\+0x1abc>
-[ ]*[a-f0-9]+: c5 7e e6 05 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[rip\+0x99\] # 1ac4 <_start\+0x1ac4>
-[ ]*[a-f0-9]+: c5 7d 5a 05 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[rip\+0x99\] # 1acc <_start\+0x1acc>
-[ ]*[a-f0-9]+: c5 39 e0 3d 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rip\+0x99\] # 1ad4 <_start\+0x1ad4>
-[ ]*[a-f0-9]+: c4 63 79 df 05 99 00 00 00 64 vaeskeygenassist xmm8,XMMWORD PTR \[rip\+0x99\],0x64 # 1ade <_start\+0x1ade>
-[ ]*[a-f0-9]+: c4 63 79 14 05 99 00 00 00 64 vpextrb BYTE PTR \[rip\+0x99\],xmm8,0x64 # 1ae8 <_start\+0x1ae8>
-[ ]*[a-f0-9]+: c5 3b 2a 3d 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rip\+0x99\] # 1af0 <_start\+0x1af0>
-[ ]*[a-f0-9]+: c4 63 19 4a 35 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rip\+0x99\],xmm8 # 1afa <_start\+0x1afa>
-[ ]*[a-f0-9]+: c4 63 39 20 3d 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rip\+0x99\],0x64 # 1b04 <_start\+0x1b04>
-[ ]*[a-f0-9]+: c5 7d 6f 05 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[rip\+0x99\] # 1b0c <_start\+0x1b0c>
-[ ]*[a-f0-9]+: c5 7d 7f 05 99 00 00 00 vmovdqa YMMWORD PTR \[rip\+0x99\],ymm8 # 1b14 <_start\+0x1b14>
-[ ]*[a-f0-9]+: c4 62 3d 0d 3d 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rip\+0x99\] # 1b1d <_start\+0x1b1d>
-[ ]*[a-f0-9]+: c4 63 7d 09 05 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[rip\+0x99\],0x64 # 1b27 <_start\+0x1b27>
-[ ]*[a-f0-9]+: c4 63 7d 19 05 99 00 00 00 64 vextractf128 XMMWORD PTR \[rip\+0x99\],ymm8,0x64 # 1b31 <_start\+0x1b31>
-[ ]*[a-f0-9]+: c4 63 3d 06 3d 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rip\+0x99\],0x64 # 1b3b <_start\+0x1b3b>
-[ ]*[a-f0-9]+: c4 63 1d 4b 35 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rip\+0x99\],ymm8 # 1b45 <_start\+0x1b45>
+[ ]*[a-f0-9]+: c5 f8 ae 15 99 00 00 00 vldmxcsr DWORD PTR \[rip\+0x99\] # 17bc <_start\+0x17bc>
+[ ]*[a-f0-9]+: c5 79 6f 05 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[rip\+0x99\] # 17c4 <_start\+0x17c4>
+[ ]*[a-f0-9]+: c5 79 7f 05 99 00 00 00 vmovdqa XMMWORD PTR \[rip\+0x99\],xmm8 # 17cc <_start\+0x17cc>
+[ ]*[a-f0-9]+: c5 79 7e 05 99 00 00 00 vmovd DWORD PTR \[rip\+0x99\],xmm8 # 17d4 <_start\+0x17d4>
+[ ]*[a-f0-9]+: c5 7b 2d 05 99 00 00 00 vcvtsd2si r8d,QWORD PTR \[rip\+0x99\] # 17dc <_start\+0x17dc>
+[ ]*[a-f0-9]+: c5 7e e6 05 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[rip\+0x99\] # 17e4 <_start\+0x17e4>
+[ ]*[a-f0-9]+: c5 7d 5a 05 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[rip\+0x99\] # 17ec <_start\+0x17ec>
+[ ]*[a-f0-9]+: c5 39 e0 3d 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rip\+0x99\] # 17f4 <_start\+0x17f4>
+[ ]*[a-f0-9]+: c4 63 79 df 05 99 00 00 00 07 vaeskeygenassist xmm8,XMMWORD PTR \[rip\+0x99\],0x7 # 17fe <_start\+0x17fe>
+[ ]*[a-f0-9]+: c4 63 79 14 05 99 00 00 00 07 vpextrb BYTE PTR \[rip\+0x99\],xmm8,0x7 # 1808 <_start\+0x1808>
+[ ]*[a-f0-9]+: c5 3b 2a 3d 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rip\+0x99\] # 1810 <_start\+0x1810>
+[ ]*[a-f0-9]+: c4 63 19 4a 35 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rip\+0x99\],xmm8 # 181a <_start\+0x181a>
+[ ]*[a-f0-9]+: c4 63 39 20 3d 99 00 00 00 07 vpinsrb xmm15,xmm8,BYTE PTR \[rip\+0x99\],0x7 # 1824 <_start\+0x1824>
+[ ]*[a-f0-9]+: c5 7d 6f 05 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[rip\+0x99\] # 182c <_start\+0x182c>
+[ ]*[a-f0-9]+: c5 7d 7f 05 99 00 00 00 vmovdqa YMMWORD PTR \[rip\+0x99\],ymm8 # 1834 <_start\+0x1834>
+[ ]*[a-f0-9]+: c4 62 3d 0d 3d 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rip\+0x99\] # 183d <_start\+0x183d>
+[ ]*[a-f0-9]+: c4 63 7d 09 05 99 00 00 00 07 vroundpd ymm8,YMMWORD PTR \[rip\+0x99\],0x7 # 1847 <_start\+0x1847>
+[ ]*[a-f0-9]+: c4 63 7d 19 05 99 00 00 00 07 vextractf128 XMMWORD PTR \[rip\+0x99\],ymm8,0x7 # 1851 <_start\+0x1851>
+[ ]*[a-f0-9]+: c4 63 3d 06 3d 99 00 00 00 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rip\+0x99\],0x7 # 185b <_start\+0x185b>
+[ ]*[a-f0-9]+: c4 63 1d 4b 35 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rip\+0x99\],ymm8 # 1865 <_start\+0x1865>
[ ]*[a-f0-9]+: c5 f8 ae 94 24 99 00 00 00 vldmxcsr DWORD PTR \[rsp\+0x99\]
[ ]*[a-f0-9]+: c5 79 6f 84 24 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[rsp\+0x99\]
[ ]*[a-f0-9]+: c5 79 7f 84 24 99 00 00 00 vmovdqa XMMWORD PTR \[rsp\+0x99\],xmm8
[ ]*[a-f0-9]+: c5 7e e6 84 24 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[rsp\+0x99\]
[ ]*[a-f0-9]+: c5 7d 5a 84 24 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[rsp\+0x99\]
[ ]*[a-f0-9]+: c5 39 e0 bc 24 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rsp\+0x99\]
-[ ]*[a-f0-9]+: c4 63 79 df 84 24 99 00 00 00 64 vaeskeygenassist xmm8,XMMWORD PTR \[rsp\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 79 14 84 24 99 00 00 00 64 vpextrb BYTE PTR \[rsp\+0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 84 24 99 00 00 00 07 vaeskeygenassist xmm8,XMMWORD PTR \[rsp\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 79 14 84 24 99 00 00 00 07 vpextrb BYTE PTR \[rsp\+0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a bc 24 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\+0x99\]
[ ]*[a-f0-9]+: c4 63 19 4a b4 24 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rsp\+0x99\],xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 bc 24 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 39 20 bc 24 99 00 00 00 07 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\+0x99\],0x7
[ ]*[a-f0-9]+: c5 7d 6f 84 24 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[rsp\+0x99\]
[ ]*[a-f0-9]+: c5 7d 7f 84 24 99 00 00 00 vmovdqa YMMWORD PTR \[rsp\+0x99\],ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d bc 24 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rsp\+0x99\]
-[ ]*[a-f0-9]+: c4 63 7d 09 84 24 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[rsp\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 84 24 99 00 00 00 64 vextractf128 XMMWORD PTR \[rsp\+0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 bc 24 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 84 24 99 00 00 00 07 vroundpd ymm8,YMMWORD PTR \[rsp\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 84 24 99 00 00 00 07 vextractf128 XMMWORD PTR \[rsp\+0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 bc 24 99 00 00 00 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\+0x99\],0x7
[ ]*[a-f0-9]+: c4 63 1d 4b b4 24 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rsp\+0x99\],ymm8
[ ]*[a-f0-9]+: c4 c1 78 ae 94 24 99 00 00 00 vldmxcsr DWORD PTR \[r12\+0x99\]
[ ]*[a-f0-9]+: c4 41 79 6f 84 24 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[r12\+0x99\]
[ ]*[a-f0-9]+: c4 41 7e e6 84 24 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[r12\+0x99\]
[ ]*[a-f0-9]+: c4 41 7d 5a 84 24 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[r12\+0x99\]
[ ]*[a-f0-9]+: c4 41 39 e0 bc 24 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[r12\+0x99\]
-[ ]*[a-f0-9]+: c4 43 79 df 84 24 99 00 00 00 64 vaeskeygenassist xmm8,XMMWORD PTR \[r12\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 43 79 14 84 24 99 00 00 00 64 vpextrb BYTE PTR \[r12\+0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 43 79 df 84 24 99 00 00 00 07 vaeskeygenassist xmm8,XMMWORD PTR \[r12\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 43 79 14 84 24 99 00 00 00 07 vpextrb BYTE PTR \[r12\+0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c4 41 3b 2a bc 24 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[r12\+0x99\]
[ ]*[a-f0-9]+: c4 43 19 4a b4 24 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r12\+0x99\],xmm8
-[ ]*[a-f0-9]+: c4 43 39 20 bc 24 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[r12\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 43 39 20 bc 24 99 00 00 00 07 vpinsrb xmm15,xmm8,BYTE PTR \[r12\+0x99\],0x7
[ ]*[a-f0-9]+: c4 41 7d 6f 84 24 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[r12\+0x99\]
[ ]*[a-f0-9]+: c4 41 7d 7f 84 24 99 00 00 00 vmovdqa YMMWORD PTR \[r12\+0x99\],ymm8
[ ]*[a-f0-9]+: c4 42 3d 0d bc 24 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[r12\+0x99\]
-[ ]*[a-f0-9]+: c4 43 7d 09 84 24 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[r12\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 43 7d 19 84 24 99 00 00 00 64 vextractf128 XMMWORD PTR \[r12\+0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 43 3d 06 bc 24 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r12\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 43 7d 09 84 24 99 00 00 00 07 vroundpd ymm8,YMMWORD PTR \[r12\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 43 7d 19 84 24 99 00 00 00 07 vextractf128 XMMWORD PTR \[r12\+0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 43 3d 06 bc 24 99 00 00 00 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r12\+0x99\],0x7
[ ]*[a-f0-9]+: c4 43 1d 4b b4 24 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r12\+0x99\],ymm8
[ ]*[a-f0-9]+: c5 f8 ae 14 25 67 ff ff ff vldmxcsr DWORD PTR ds:0xffffffffffffff67
[ ]*[a-f0-9]+: c5 79 6f 04 25 67 ff ff ff vmovdqa xmm8,XMMWORD PTR ds:0xffffffffffffff67
[ ]*[a-f0-9]+: c5 7e e6 04 25 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR ds:0xffffffffffffff67
[ ]*[a-f0-9]+: c5 7d 5a 04 25 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR ds:0xffffffffffffff67
[ ]*[a-f0-9]+: c5 39 e0 3c 25 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR ds:0xffffffffffffff67
-[ ]*[a-f0-9]+: c4 63 79 df 04 25 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR ds:0xffffffffffffff67,0x64
-[ ]*[a-f0-9]+: c4 63 79 14 04 25 67 ff ff ff 64 vpextrb BYTE PTR ds:0xffffffffffffff67,xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 04 25 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR ds:0xffffffffffffff67,0x7
+[ ]*[a-f0-9]+: c4 63 79 14 04 25 67 ff ff ff 07 vpextrb BYTE PTR ds:0xffffffffffffff67,xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a 3c 25 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0xffffffffffffff67
[ ]*[a-f0-9]+: c4 63 19 4a 34 25 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR ds:0xffffffffffffff67,xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 3c 25 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR ds:0xffffffffffffff67,0x64
+[ ]*[a-f0-9]+: c4 63 39 20 3c 25 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR ds:0xffffffffffffff67,0x7
[ ]*[a-f0-9]+: c5 7d 6f 04 25 67 ff ff ff vmovdqa ymm8,YMMWORD PTR ds:0xffffffffffffff67
[ ]*[a-f0-9]+: c5 7d 7f 04 25 67 ff ff ff vmovdqa YMMWORD PTR ds:0xffffffffffffff67,ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR ds:0xffffffffffffff67
-[ ]*[a-f0-9]+: c4 63 7d 09 04 25 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR ds:0xffffffffffffff67,0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 04 25 67 ff ff ff 64 vextractf128 XMMWORD PTR ds:0xffffffffffffff67,ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0xffffffffffffff67,0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 04 25 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR ds:0xffffffffffffff67,0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 04 25 67 ff ff ff 07 vextractf128 XMMWORD PTR ds:0xffffffffffffff67,ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0xffffffffffffff67,0x7
[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR ds:0xffffffffffffff67,ymm8
[ ]*[a-f0-9]+: c5 f8 ae 14 65 67 ff ff ff vldmxcsr DWORD PTR \[riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 79 6f 04 65 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 7e e6 04 65 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 7d 5a 04 65 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 39 e0 3c 65 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[riz\*2-0x99\]
-[ ]*[a-f0-9]+: c4 63 79 df 04 65 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR \[riz\*2-0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 79 14 04 65 67 ff ff ff 64 vpextrb BYTE PTR \[riz\*2-0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 04 65 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR \[riz\*2-0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 79 14 04 65 67 ff ff ff 07 vpextrb BYTE PTR \[riz\*2-0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a 3c 65 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[riz\*2-0x99\]
[ ]*[a-f0-9]+: c4 63 19 4a 34 65 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[riz\*2-0x99\],xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 3c 65 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[riz\*2-0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 39 20 3c 65 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR \[riz\*2-0x99\],0x7
[ ]*[a-f0-9]+: c5 7d 6f 04 65 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 7d 7f 04 65 67 ff ff ff vmovdqa YMMWORD PTR \[riz\*2-0x99\],ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d 3c 65 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[riz\*2-0x99\]
-[ ]*[a-f0-9]+: c4 63 7d 09 04 65 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[riz\*2-0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 04 65 67 ff ff ff 64 vextractf128 XMMWORD PTR \[riz\*2-0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 3c 65 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[riz\*2-0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 04 65 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR \[riz\*2-0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 04 65 67 ff ff ff 07 vextractf128 XMMWORD PTR \[riz\*2-0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 3c 65 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[riz\*2-0x99\],0x7
[ ]*[a-f0-9]+: c4 63 1d 4b 34 65 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[riz\*2-0x99\],ymm8
[ ]*[a-f0-9]+: c5 f8 ae 94 23 67 ff ff ff vldmxcsr DWORD PTR \[rbx\+riz\*1-0x99\]
[ ]*[a-f0-9]+: c5 79 6f 84 23 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rbx\+riz\*1-0x99\]
[ ]*[a-f0-9]+: c5 7e e6 84 23 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rbx\+riz\*1-0x99\]
[ ]*[a-f0-9]+: c5 7d 5a 84 23 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rbx\+riz\*1-0x99\]
[ ]*[a-f0-9]+: c5 39 e0 bc 23 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rbx\+riz\*1-0x99\]
-[ ]*[a-f0-9]+: c4 63 79 df 84 23 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR \[rbx\+riz\*1-0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 79 14 84 23 67 ff ff ff 64 vpextrb BYTE PTR \[rbx\+riz\*1-0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 84 23 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR \[rbx\+riz\*1-0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 79 14 84 23 67 ff ff ff 07 vpextrb BYTE PTR \[rbx\+riz\*1-0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a bc 23 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbx\+riz\*1-0x99\]
[ ]*[a-f0-9]+: c4 63 19 4a b4 23 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbx\+riz\*1-0x99\],xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 bc 23 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbx\+riz\*1-0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 39 20 bc 23 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR \[rbx\+riz\*1-0x99\],0x7
[ ]*[a-f0-9]+: c5 7d 6f 84 23 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\]
[ ]*[a-f0-9]+: c5 7d 7f 84 23 67 ff ff ff vmovdqa YMMWORD PTR \[rbx\+riz\*1-0x99\],ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d bc 23 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\]
-[ ]*[a-f0-9]+: c4 63 7d 09 84 23 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 84 23 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rbx\+riz\*1-0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 bc 23 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 84 23 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 84 23 67 ff ff ff 07 vextractf128 XMMWORD PTR \[rbx\+riz\*1-0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 bc 23 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\],0x7
[ ]*[a-f0-9]+: c4 63 1d 4b b4 23 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbx\+riz\*1-0x99\],ymm8
[ ]*[a-f0-9]+: c5 f8 ae 94 63 67 ff ff ff vldmxcsr DWORD PTR \[rbx\+riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 79 6f 84 63 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rbx\+riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 7e e6 84 63 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rbx\+riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 7d 5a 84 63 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rbx\+riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 39 e0 bc 63 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rbx\+riz\*2-0x99\]
-[ ]*[a-f0-9]+: c4 63 79 df 84 63 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR \[rbx\+riz\*2-0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 79 14 84 63 67 ff ff ff 64 vpextrb BYTE PTR \[rbx\+riz\*2-0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 84 63 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR \[rbx\+riz\*2-0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 79 14 84 63 67 ff ff ff 07 vpextrb BYTE PTR \[rbx\+riz\*2-0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a bc 63 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbx\+riz\*2-0x99\]
[ ]*[a-f0-9]+: c4 63 19 4a b4 63 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbx\+riz\*2-0x99\],xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 bc 63 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbx\+riz\*2-0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 39 20 bc 63 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR \[rbx\+riz\*2-0x99\],0x7
[ ]*[a-f0-9]+: c5 7d 6f 84 63 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 7d 7f 84 63 67 ff ff ff vmovdqa YMMWORD PTR \[rbx\+riz\*2-0x99\],ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d bc 63 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\]
-[ ]*[a-f0-9]+: c4 63 7d 09 84 63 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 84 63 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rbx\+riz\*2-0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 bc 63 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 84 63 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 84 63 67 ff ff ff 07 vextractf128 XMMWORD PTR \[rbx\+riz\*2-0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 bc 63 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\],0x7
[ ]*[a-f0-9]+: c4 63 1d 4b b4 63 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbx\+riz\*2-0x99\],ymm8
[ ]*[a-f0-9]+: c4 81 78 ae 94 bc 67 ff ff ff vldmxcsr DWORD PTR \[r12\+r15\*4-0x99\]
[ ]*[a-f0-9]+: c4 01 79 6f 84 bc 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[r12\+r15\*4-0x99\]
[ ]*[a-f0-9]+: c4 01 7e e6 84 bc 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[r12\+r15\*4-0x99\]
[ ]*[a-f0-9]+: c4 01 7d 5a 84 bc 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[r12\+r15\*4-0x99\]
[ ]*[a-f0-9]+: c4 01 39 e0 bc bc 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[r12\+r15\*4-0x99\]
-[ ]*[a-f0-9]+: c4 03 79 df 84 bc 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR \[r12\+r15\*4-0x99\],0x64
-[ ]*[a-f0-9]+: c4 03 79 14 84 bc 67 ff ff ff 64 vpextrb BYTE PTR \[r12\+r15\*4-0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 03 79 df 84 bc 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR \[r12\+r15\*4-0x99\],0x7
+[ ]*[a-f0-9]+: c4 03 79 14 84 bc 67 ff ff ff 07 vpextrb BYTE PTR \[r12\+r15\*4-0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c4 01 3b 2a bc bc 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[r12\+r15\*4-0x99\]
[ ]*[a-f0-9]+: c4 03 19 4a b4 bc 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r12\+r15\*4-0x99\],xmm8
-[ ]*[a-f0-9]+: c4 03 39 20 bc bc 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[r12\+r15\*4-0x99\],0x64
+[ ]*[a-f0-9]+: c4 03 39 20 bc bc 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR \[r12\+r15\*4-0x99\],0x7
[ ]*[a-f0-9]+: c4 01 7d 6f 84 bc 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\]
[ ]*[a-f0-9]+: c4 01 7d 7f 84 bc 67 ff ff ff vmovdqa YMMWORD PTR \[r12\+r15\*4-0x99\],ymm8
[ ]*[a-f0-9]+: c4 02 3d 0d bc bc 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\]
-[ ]*[a-f0-9]+: c4 03 7d 09 84 bc 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\],0x64
-[ ]*[a-f0-9]+: c4 03 7d 19 84 bc 67 ff ff ff 64 vextractf128 XMMWORD PTR \[r12\+r15\*4-0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 03 3d 06 bc bc 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\],0x64
+[ ]*[a-f0-9]+: c4 03 7d 09 84 bc 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\],0x7
+[ ]*[a-f0-9]+: c4 03 7d 19 84 bc 67 ff ff ff 07 vextractf128 XMMWORD PTR \[r12\+r15\*4-0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 03 3d 06 bc bc 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\],0x7
[ ]*[a-f0-9]+: c4 03 1d 4b b4 bc 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r12\+r15\*4-0x99\],ymm8
[ ]*[a-f0-9]+: c4 81 78 ae 94 f8 67 ff ff ff vldmxcsr DWORD PTR \[r8\+r15\*8-0x99\]
[ ]*[a-f0-9]+: c4 01 79 6f 84 f8 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[r8\+r15\*8-0x99\]
[ ]*[a-f0-9]+: c4 01 7e e6 84 f8 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[r8\+r15\*8-0x99\]
[ ]*[a-f0-9]+: c4 01 7d 5a 84 f8 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[r8\+r15\*8-0x99\]
[ ]*[a-f0-9]+: c4 01 39 e0 bc f8 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[r8\+r15\*8-0x99\]
-[ ]*[a-f0-9]+: c4 03 79 df 84 f8 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR \[r8\+r15\*8-0x99\],0x64
-[ ]*[a-f0-9]+: c4 03 79 14 84 f8 67 ff ff ff 64 vpextrb BYTE PTR \[r8\+r15\*8-0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 03 79 df 84 f8 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR \[r8\+r15\*8-0x99\],0x7
+[ ]*[a-f0-9]+: c4 03 79 14 84 f8 67 ff ff ff 07 vpextrb BYTE PTR \[r8\+r15\*8-0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c4 01 3b 2a bc f8 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[r8\+r15\*8-0x99\]
[ ]*[a-f0-9]+: c4 03 19 4a b4 f8 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r8\+r15\*8-0x99\],xmm8
-[ ]*[a-f0-9]+: c4 03 39 20 bc f8 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[r8\+r15\*8-0x99\],0x64
+[ ]*[a-f0-9]+: c4 03 39 20 bc f8 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR \[r8\+r15\*8-0x99\],0x7
[ ]*[a-f0-9]+: c4 01 7d 6f 84 f8 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\]
[ ]*[a-f0-9]+: c4 01 7d 7f 84 f8 67 ff ff ff vmovdqa YMMWORD PTR \[r8\+r15\*8-0x99\],ymm8
[ ]*[a-f0-9]+: c4 02 3d 0d bc f8 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\]
-[ ]*[a-f0-9]+: c4 03 7d 09 84 f8 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\],0x64
-[ ]*[a-f0-9]+: c4 03 7d 19 84 f8 67 ff ff ff 64 vextractf128 XMMWORD PTR \[r8\+r15\*8-0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 03 3d 06 bc f8 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\],0x64
+[ ]*[a-f0-9]+: c4 03 7d 09 84 f8 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\],0x7
+[ ]*[a-f0-9]+: c4 03 7d 19 84 f8 67 ff ff ff 07 vextractf128 XMMWORD PTR \[r8\+r15\*8-0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 03 3d 06 bc f8 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\],0x7
[ ]*[a-f0-9]+: c4 03 1d 4b b4 f8 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r8\+r15\*8-0x99\],ymm8
[ ]*[a-f0-9]+: c4 a1 78 ae 94 ad 67 ff ff ff vldmxcsr DWORD PTR \[rbp\+r13\*4-0x99\]
[ ]*[a-f0-9]+: c4 21 79 6f 84 ad 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rbp\+r13\*4-0x99\]
[ ]*[a-f0-9]+: c4 21 7e e6 84 ad 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rbp\+r13\*4-0x99\]
[ ]*[a-f0-9]+: c4 21 7d 5a 84 ad 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rbp\+r13\*4-0x99\]
[ ]*[a-f0-9]+: c4 21 39 e0 bc ad 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rbp\+r13\*4-0x99\]
-[ ]*[a-f0-9]+: c4 23 79 df 84 ad 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR \[rbp\+r13\*4-0x99\],0x64
-[ ]*[a-f0-9]+: c4 23 79 14 84 ad 67 ff ff ff 64 vpextrb BYTE PTR \[rbp\+r13\*4-0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 23 79 df 84 ad 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR \[rbp\+r13\*4-0x99\],0x7
+[ ]*[a-f0-9]+: c4 23 79 14 84 ad 67 ff ff ff 07 vpextrb BYTE PTR \[rbp\+r13\*4-0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c4 21 3b 2a bc ad 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+r13\*4-0x99\]
[ ]*[a-f0-9]+: c4 23 19 4a b4 ad 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbp\+r13\*4-0x99\],xmm8
-[ ]*[a-f0-9]+: c4 23 39 20 bc ad 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+r13\*4-0x99\],0x64
+[ ]*[a-f0-9]+: c4 23 39 20 bc ad 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+r13\*4-0x99\],0x7
[ ]*[a-f0-9]+: c4 21 7d 6f 84 ad 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rbp\+r13\*4-0x99\]
[ ]*[a-f0-9]+: c4 21 7d 7f 84 ad 67 ff ff ff vmovdqa YMMWORD PTR \[rbp\+r13\*4-0x99\],ymm8
[ ]*[a-f0-9]+: c4 22 3d 0d bc ad 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rbp\+r13\*4-0x99\]
-[ ]*[a-f0-9]+: c4 23 7d 09 84 ad 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rbp\+r13\*4-0x99\],0x64
-[ ]*[a-f0-9]+: c4 23 7d 19 84 ad 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rbp\+r13\*4-0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 23 3d 06 bc ad 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+r13\*4-0x99\],0x64
+[ ]*[a-f0-9]+: c4 23 7d 09 84 ad 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR \[rbp\+r13\*4-0x99\],0x7
+[ ]*[a-f0-9]+: c4 23 7d 19 84 ad 67 ff ff ff 07 vextractf128 XMMWORD PTR \[rbp\+r13\*4-0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 23 3d 06 bc ad 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+r13\*4-0x99\],0x7
[ ]*[a-f0-9]+: c4 23 1d 4b b4 ad 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbp\+r13\*4-0x99\],ymm8
[ ]*[a-f0-9]+: c4 a1 78 ae 94 24 67 ff ff ff vldmxcsr DWORD PTR \[rsp\+r12\*1-0x99\]
[ ]*[a-f0-9]+: c4 21 79 6f 84 24 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rsp\+r12\*1-0x99\]
[ ]*[a-f0-9]+: c4 21 7e e6 84 24 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rsp\+r12\*1-0x99\]
[ ]*[a-f0-9]+: c4 21 7d 5a 84 24 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rsp\+r12\*1-0x99\]
[ ]*[a-f0-9]+: c4 21 39 e0 bc 24 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rsp\+r12\*1-0x99\]
-[ ]*[a-f0-9]+: c4 23 79 df 84 24 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR \[rsp\+r12\*1-0x99\],0x64
-[ ]*[a-f0-9]+: c4 23 79 14 84 24 67 ff ff ff 64 vpextrb BYTE PTR \[rsp\+r12\*1-0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 23 79 df 84 24 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR \[rsp\+r12\*1-0x99\],0x7
+[ ]*[a-f0-9]+: c4 23 79 14 84 24 67 ff ff ff 07 vpextrb BYTE PTR \[rsp\+r12\*1-0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c4 21 3b 2a bc 24 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\+r12\*1-0x99\]
[ ]*[a-f0-9]+: c4 23 19 4a b4 24 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rsp\+r12\*1-0x99\],xmm8
-[ ]*[a-f0-9]+: c4 23 39 20 bc 24 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\+r12\*1-0x99\],0x64
+[ ]*[a-f0-9]+: c4 23 39 20 bc 24 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\+r12\*1-0x99\],0x7
[ ]*[a-f0-9]+: c4 21 7d 6f 84 24 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rsp\+r12\*1-0x99\]
[ ]*[a-f0-9]+: c4 21 7d 7f 84 24 67 ff ff ff vmovdqa YMMWORD PTR \[rsp\+r12\*1-0x99\],ymm8
[ ]*[a-f0-9]+: c4 22 3d 0d bc 24 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rsp\+r12\*1-0x99\]
-[ ]*[a-f0-9]+: c4 23 7d 09 84 24 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rsp\+r12\*1-0x99\],0x64
-[ ]*[a-f0-9]+: c4 23 7d 19 84 24 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rsp\+r12\*1-0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 23 3d 06 bc 24 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\+r12\*1-0x99\],0x64
+[ ]*[a-f0-9]+: c4 23 7d 09 84 24 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR \[rsp\+r12\*1-0x99\],0x7
+[ ]*[a-f0-9]+: c4 23 7d 19 84 24 67 ff ff ff 07 vextractf128 XMMWORD PTR \[rsp\+r12\*1-0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 23 3d 06 bc 24 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\+r12\*1-0x99\],0x7
[ ]*[a-f0-9]+: c4 23 1d 4b b4 24 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rsp\+r12\*1-0x99\],ymm8
[ ]*[a-f0-9]+: c4 41 79 50 c0 vmovmskpd r8d,xmm8
-[ ]*[a-f0-9]+: c4 c1 01 72 f0 64 vpslld xmm15,xmm8,0x64
+[ ]*[a-f0-9]+: c4 c1 01 72 f0 07 vpslld xmm15,xmm8,0x7
[ ]*[a-f0-9]+: c4 41 7c 50 c0 vmovmskps r8d,ymm8
[ ]*[a-f0-9]+: c4 41 79 6f f8 vmovdqa xmm15,xmm8
[ ]*[a-f0-9]+: c4 41 79 7e c0 vmovd r8d,xmm8
[ ]*[a-f0-9]+: c4 41 7b 2d c0 vcvtsd2si r8d,xmm8
[ ]*[a-f0-9]+: c4 41 7e e6 c0 vcvtdq2pd ymm8,xmm8
[ ]*[a-f0-9]+: c4 41 7d 5a c0 vcvtpd2ps xmm8,ymm8
-[ ]*[a-f0-9]+: c4 43 79 df f8 64 vaeskeygenassist xmm15,xmm8,0x64
-[ ]*[a-f0-9]+: c4 43 79 14 c0 64 vpextrb r8d,xmm8,0x64
+[ ]*[a-f0-9]+: c4 43 79 df f8 07 vaeskeygenassist xmm15,xmm8,0x7
+[ ]*[a-f0-9]+: c4 43 79 14 c0 07 vpextrb r8d,xmm8,0x7
[ ]*[a-f0-9]+: c4 41 3b 2a f8 vcvtsi2sd xmm15,xmm8,r8d
[ ]*[a-f0-9]+: c4 43 19 4a f0 80 vblendvps xmm14,xmm12,xmm8,xmm8
-[ ]*[a-f0-9]+: c4 43 39 20 f8 64 vpinsrb xmm15,xmm8,r8d,0x64
+[ ]*[a-f0-9]+: c4 43 39 20 f8 07 vpinsrb xmm15,xmm8,r8d,0x7
[ ]*[a-f0-9]+: c4 41 7d 6f f8 vmovdqa ymm15,ymm8
[ ]*[a-f0-9]+: c4 42 05 0d e0 vpermilpd ymm12,ymm15,ymm8
-[ ]*[a-f0-9]+: c4 43 7d 09 f8 64 vroundpd ymm15,ymm8,0x64
-[ ]*[a-f0-9]+: c4 43 7d 19 c0 64 vextractf128 xmm8,ymm8,0x64
-[ ]*[a-f0-9]+: c4 43 05 06 e0 64 vperm2f128 ymm12,ymm15,ymm8,0x64
+[ ]*[a-f0-9]+: c4 43 7d 09 f8 07 vroundpd ymm15,ymm8,0x7
+[ ]*[a-f0-9]+: c4 43 7d 19 c0 07 vextractf128 xmm8,ymm8,0x7
+[ ]*[a-f0-9]+: c4 43 05 06 e0 07 vperm2f128 ymm12,ymm15,ymm8,0x7
[ ]*[a-f0-9]+: c4 43 1d 4b f7 80 vblendvpd ymm14,ymm12,ymm15,ymm8
-[ ]*[a-f0-9]+: c4 43 3d 18 f8 64 vinsertf128 ymm15,ymm8,xmm8,0x64
+[ ]*[a-f0-9]+: c4 43 3d 18 f8 07 vinsertf128 ymm15,ymm8,xmm8,0x7
[ ]*[a-f0-9]+: c4 61 fb 2d 01 vcvtsd2si r8,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 43 79 17 c0 0a vextractps r8d,xmm8,0xa
[ ]*[a-f0-9]+: c4 61 fa 2d 01 vcvtss2si r8,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 41 01 c4 c0 64 vpinsrw xmm8,xmm15,r8d,0x64
+[ ]*[a-f0-9]+: c4 41 01 c4 c0 07 vpinsrw xmm8,xmm15,r8d,0x7
[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr DWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr DWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr DWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps YMMWORD PTR \[rcx\],ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps ymm6,ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps YMMWORD PTR \[rcx\],ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps ymm2,ymm6,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps ymm6,YMMWORD PTR \[rcx\],0x64
+[ ]*[a-f0-9]+: c4 e3 7d 05 d6 07 vpermilpd ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 05 31 07 vpermilpd ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 05 31 07 vpermilpd ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 04 d6 07 vpermilps ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 04 31 07 vpermilps ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 04 31 07 vpermilps ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 09 d6 07 vroundpd ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 09 31 07 vroundpd ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 09 31 07 vroundpd ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 08 d6 07 vroundps ymm2,ymm6,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 08 31 07 vroundps ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 08 31 07 vroundps ymm6,YMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd ymm2,ymm6,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd ymm2,ymm6,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2ps xmm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq xmm4,ymm4
[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dq xmm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 5b f4 vcvtdq2ps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 5b f4 vcvtps2dq ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 5b f4 vcvttps2dq ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup ymm4,ymm4
+[ ]*[a-f0-9]+: c5 ff 12 f4 vmovddup ymm6,ymm4
[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 16 f4 vmovshdup ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fe 12 f4 vmovsldup ymm6,ymm4
[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 10 21 vmovups ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fc 10 21 vmovups ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest ymm4,ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 17 f4 vptest ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 53 f4 vrcpps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 52 f4 vrsqrtps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fd 51 f4 vsqrtpd ymm6,ymm4
[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps ymm4,ymm4
+[ ]*[a-f0-9]+: c5 fc 51 f4 vsqrtps ymm6,ymm4
[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd ymm4,ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0f f4 vtestpd ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd ymm4,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps ymm4,ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0e f4 vtestps ymm6,ymm4
[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps ymm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu ymm4,\[rcx\]
[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu ymm4,\[rcx\]
-[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps ymm2,ymm6,ymm4,0x64
-[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x64
+[ ]*[a-f0-9]+: c4 e3 4d 0d d4 07 vblendpd ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0d 11 07 vblendpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0d 11 07 vblendpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0c d4 07 vblendps ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0c 11 07 vblendps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 0c 11 07 vblendps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd ymm2,ymm6,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd ymm2,ymm6,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps ymm2,ymm6,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps ymm2,ymm6,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e3 4d 40 d4 07 vdpps ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 40 11 07 vdpps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 40 11 07 vdpps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 06 d4 07 vperm2f128 ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 4d 06 11 07 vperm2f128 ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 4d 06 11 07 vperm2f128 ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 cd c6 d4 07 vshufpd ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps ymm2,ymm6,ymm4,0x7
+[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps ymm7,ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 69 39 20 vfmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 69 39 20 vfmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 68 fc 20 vfmaddps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 68 39 20 vfmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 68 39 20 vfmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5d fc 20 vfmaddsubpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5d 39 20 vfmaddsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5d 39 20 vfmaddsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5c fc 20 vfmaddsubps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5c 39 20 vfmaddsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5c 39 20 vfmaddsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5f fc 20 vfmsubaddpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5f 39 20 vfmsubaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5f 39 20 vfmsubaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5e fc 20 vfmsubaddps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 5e 39 20 vfmsubaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 5e 39 20 vfmsubaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 6d fc 20 vfmsubpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 6d 39 20 vfmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 6d 39 20 vfmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 6c fc 20 vfmsubps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 6c 39 20 vfmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 6c 39 20 vfmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 79 fc 20 vfnmaddpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 79 39 20 vfnmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 79 39 20 vfnmaddpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 78 fc 20 vfnmaddps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 78 39 20 vfnmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 78 39 20 vfnmaddps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 7d fc 20 vfnmsubpd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 7d 39 20 vfnmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 7d 39 20 vfnmsubpd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 7c fc 20 vfnmsubps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 cd 7c 39 20 vfnmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 cd 7c 39 20 vfnmsubps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps ymm7,ymm2,ymm6,ymm4
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd ymm7,ymm2,ymm6,ymm4,0xa
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\],0xa
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\],0xa
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps ymm7,ymm2,ymm6,ymm4,0xa
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\],0xa
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps ymm7,ymm2,ymm6,YMMWORD PTR \[rcx\],0xa
-[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 ymm6,ymm4,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 ymm6,ymm4,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 ymm6,ymm4,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 xmm4,ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 XMMWORD PTR \[rcx\],ymm4,0x64
-[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 XMMWORD PTR \[rcx\],ymm4,0x64
+[ ]*[a-f0-9]+: c4 e3 5d 18 f4 07 vinsertf128 ymm6,ymm4,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 5d 18 31 07 vinsertf128 ymm6,ymm4,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 5d 18 31 07 vinsertf128 ymm6,ymm4,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 e4 07 vextractf128 xmm4,ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 21 07 vextractf128 XMMWORD PTR \[rcx\],ymm4,0x7
+[ ]*[a-f0-9]+: c4 e3 7d 19 21 07 vextractf128 XMMWORD PTR \[rcx\],ymm4,0x7
[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 ymm4,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 ymm4,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 79 df f4 64 vaeskeygenassist xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 df 31 64 vaeskeygenassist xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 df 31 64 vaeskeygenassist xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps xmm6,XMMWORD PTR \[rcx\],0x64
+[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 df 31 07 vaeskeygenassist xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 df 31 07 vaeskeygenassist xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 61 f4 07 vpcmpestri xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 61 31 07 vpcmpestri xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 61 31 07 vpcmpestri xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 60 f4 07 vpcmpestrm xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 60 31 07 vpcmpestrm xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 60 31 07 vpcmpestrm xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 63 f4 07 vpcmpistri xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 63 31 07 vpcmpistri xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 63 31 07 vpcmpistri xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 62 f4 07 vpcmpistrm xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 62 31 07 vpcmpistrm xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 62 31 07 vpcmpistrm xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 05 f4 07 vpermilpd xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 05 31 07 vpermilpd xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 05 31 07 vpermilpd xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 04 f4 07 vpermilps xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 04 31 07 vpermilps xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 04 31 07 vpermilps xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 f9 70 f4 07 vpshufd xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 f9 70 31 07 vpshufd xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 f9 70 31 07 vpshufd xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 fa 70 f4 07 vpshufhw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 fa 70 31 07 vpshufhw xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 fa 70 31 07 vpshufhw xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 fb 70 f4 07 vpshuflw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 fb 70 31 07 vpshuflw xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 fb 70 31 07 vpshuflw xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 09 f4 07 vroundpd xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 09 31 07 vroundpd xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 09 31 07 vroundpd xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 08 f4 07 vroundps xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 08 31 07 vroundps xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 08 31 07 vroundps xmm6,XMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps XMMWORD PTR \[rcx\],xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps XMMWORD PTR \[rcx\],xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd XMMWORD PTR \[rcx\],xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd XMMWORD PTR \[rcx\],xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x64
+[ ]*[a-f0-9]+: c4 e3 49 0d d4 07 vblendpd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0d 11 07 vblendpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0d 11 07 vblendpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0c d4 07 vblendps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0c 11 07 vblendps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0c 11 07 vblendps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 c9 c2 11 07 vcmpordpd xmm2,xmm6,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 c9 c2 11 07 vcmpordpd xmm2,xmm6,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 c8 c2 11 07 vcmpordps xmm2,xmm6,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 c8 c2 11 07 vcmpordps xmm2,xmm6,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e3 49 41 d4 07 vdppd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 41 11 07 vdppd xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 41 11 07 vdppd xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 40 d4 07 vdpps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 40 11 07 vdpps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 40 11 07 vdpps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 42 d4 07 vmpsadbw xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 42 11 07 vmpsadbw xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 42 11 07 vmpsadbw xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0f d4 07 vpalignr xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0f 11 07 vpalignr xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0f 11 07 vpalignr xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0e d4 07 vpblendw xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0e 11 07 vpblendw xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0e 11 07 vpblendw xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 c9 c6 d4 07 vshufpd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb xmm7,xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 69 fc 20 vfmaddpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 69 39 20 vfmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 69 39 20 vfmaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 69 39 20 vfmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 69 39 20 vfmaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 68 fc 20 vfmaddps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 68 39 20 vfmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 68 39 20 vfmaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 68 39 20 vfmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 68 39 20 vfmaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5d fc 20 vfmaddsubpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5d 39 20 vfmaddsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 5d 39 20 vfmaddsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5d 39 20 vfmaddsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 5d 39 20 vfmaddsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5c fc 20 vfmaddsubps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5c 39 20 vfmaddsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 5c 39 20 vfmaddsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5c 39 20 vfmaddsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 5c 39 20 vfmaddsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5f fc 20 vfmsubaddpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5f 39 20 vfmsubaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 5f 39 20 vfmsubaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5f 39 20 vfmsubaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 5f 39 20 vfmsubaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5e fc 20 vfmsubaddps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5e 39 20 vfmsubaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 5e 39 20 vfmsubaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 5e 39 20 vfmsubaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 5e 39 20 vfmsubaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6d fc 20 vfmsubpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6d 39 20 vfmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6d 39 20 vfmsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6d 39 20 vfmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6d 39 20 vfmsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6c fc 20 vfmsubps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6c 39 20 vfmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6c 39 20 vfmsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6c 39 20 vfmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6c 39 20 vfmsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 79 fc 20 vfnmaddpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 79 39 20 vfnmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 79 39 20 vfnmaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 79 39 20 vfnmaddpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 79 39 20 vfnmaddpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 78 fc 20 vfnmaddps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 78 39 20 vfnmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 78 39 20 vfnmaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 78 39 20 vfnmaddps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 78 39 20 vfnmaddps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7d fc 20 vfnmsubpd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7d 39 20 vfnmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7d 39 20 vfnmsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7d 39 20 vfnmsubpd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7d 39 20 vfnmsubpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7c fc 20 vfnmsubps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7c 39 20 vfnmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7c 39 20 vfnmsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7c 39 20 vfnmsubps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7c 39 20 vfnmsubps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd xmm7,xmm2,xmm6,xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\],0xa
-[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\],0xa
-[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps xmm7,xmm2,xmm6,xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\],0xa
-[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4,0xa
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps xmm7,xmm2,xmm6,XMMWORD PTR \[rcx\],0xa
-[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4,0xa
[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd ymm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd ymm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd xmm6,xmm4
[ ]*[a-f0-9]+: c4 e1 da 2a f1 vcvtsi2ss xmm6,xmm4,rcx
[ ]*[a-f0-9]+: c4 e1 da 2a 31 vcvtsi2ss xmm6,xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e1 da 2a 31 vcvtsi2ss xmm6,xmm4,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 d9 22 f1 64 vpinsrq xmm6,xmm4,rcx,0x64
-[ ]*[a-f0-9]+: c4 e3 d9 22 31 64 vpinsrq xmm6,xmm4,QWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 d9 22 31 64 vpinsrq xmm6,xmm4,QWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 f9 16 e1 64 vpextrq rcx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 f9 16 21 64 vpextrq QWORD PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 f9 16 21 64 vpextrq QWORD PTR \[rcx\],xmm4,0x64
+[ ]*[a-f0-9]+: c4 e3 d9 22 f1 07 vpinsrq xmm6,xmm4,rcx,0x7
+[ ]*[a-f0-9]+: c4 e3 d9 22 31 07 vpinsrq xmm6,xmm4,QWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 d9 22 31 07 vpinsrq xmm6,xmm4,QWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 f9 16 e1 07 vpextrq rcx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 f9 16 21 07 vpextrq QWORD PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 f9 16 21 07 vpextrq QWORD PTR \[rcx\],xmm4,0x7
[ ]*[a-f0-9]+: c5 d9 12 31 vmovlpd xmm6,xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 d9 12 31 vmovlpd xmm6,xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 d8 12 31 vmovlps xmm6,xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd xmm6,xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps xmm6,xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps xmm6,xmm4,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd xmm2,xmm6,QWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd xmm2,xmm6,QWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd xmm2,xmm6,QWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd xmm2,xmm6,QWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 c9 6b fc 20 vfmaddsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6b 39 20 vfmaddsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6b 39 20 vfmaddsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6b 39 20 vfmaddsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6b 39 20 vfmaddsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6f fc 20 vfmsubsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6f 39 20 vfmsubsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6f 39 20 vfmsubsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6f 39 20 vfmsubsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6f 39 20 vfmsubsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7b fc 20 vfnmaddsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7b 39 20 vfnmaddsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7b 39 20 vfnmaddsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7b 39 20 vfnmaddsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7b 39 20 vfnmaddsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7f fc 20 vfnmsubsd xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7f 39 20 vfnmsubsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7f 39 20 vfnmsubsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7f 39 20 vfnmsubsd xmm7,xmm2,xmm6,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7f 39 20 vfnmsubsd xmm7,xmm2,QWORD PTR \[rcx\],xmm4
+[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd xmm2,xmm6,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd xmm2,xmm6,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e3 49 0b d4 07 vroundsd xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0b 11 07 vroundsd xmm2,xmm6,QWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0b 11 07 vroundsd xmm2,xmm6,QWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd xmm2,xmm6,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd xmm2,xmm6,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd xmm2,xmm6,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd xmm2,xmm6,QWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr DWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca 58 11 vaddss xmm2,xmm6,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 ca 58 11 vaddss xmm2,xmm6,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd ecx,xmm4
[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps ecx,xmm4
[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb ecx,xmm4
-[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd DWORD PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd DWORD PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps DWORD PTR \[rcx\],xmm4,0x64
+[ ]*[a-f0-9]+: c4 e3 79 17 e1 07 vextractps ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps DWORD PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps DWORD PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 16 e1 07 vpextrd ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 16 21 07 vpextrd DWORD PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 16 21 07 vpextrd DWORD PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 17 e1 07 vextractps ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps DWORD PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps DWORD PTR \[rcx\],xmm4,0x7
[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd xmm6,xmm4,ecx
[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sd xmm6,xmm4,DWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss xmm6,xmm4,ecx
[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ss xmm6,xmm4,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss xmm2,xmm6,DWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss xmm2,xmm6,DWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps xmm2,xmm6,DWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps xmm2,xmm6,DWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss xmm2,xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss xmm2,xmm6,DWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss xmm2,xmm6,DWORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 c9 6a fc 20 vfmaddss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6a 39 20 vfmaddss xmm7,xmm2,xmm6,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6a 39 20 vfmaddss xmm7,xmm2,DWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6a 39 20 vfmaddss xmm7,xmm2,xmm6,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6a 39 20 vfmaddss xmm7,xmm2,DWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6e fc 20 vfmsubss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6e 39 20 vfmsubss xmm7,xmm2,xmm6,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6e 39 20 vfmsubss xmm7,xmm2,DWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 6e 39 20 vfmsubss xmm7,xmm2,xmm6,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 6e 39 20 vfmsubss xmm7,xmm2,DWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7a fc 20 vfnmaddss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7a 39 20 vfnmaddss xmm7,xmm2,xmm6,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7a 39 20 vfnmaddss xmm7,xmm2,DWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7a 39 20 vfnmaddss xmm7,xmm2,xmm6,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7a 39 20 vfnmaddss xmm7,xmm2,DWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7e fc 20 vfnmsubss xmm7,xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7e 39 20 vfnmsubss xmm7,xmm2,xmm6,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7e 39 20 vfnmsubss xmm7,xmm2,DWORD PTR \[rcx\],xmm4
-[ ]*[a-f0-9]+: c4 e3 c9 7e 39 20 vfnmsubss xmm7,xmm2,xmm6,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e3 59 7e 39 20 vfnmsubss xmm7,xmm2,DWORD PTR \[rcx\],xmm4
+[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss xmm2,xmm6,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss xmm2,xmm6,DWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e3 49 21 d4 07 vinsertps xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 21 11 07 vinsertps xmm2,xmm6,DWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 21 11 07 vinsertps xmm2,xmm6,DWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0a d4 07 vroundss xmm2,xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 49 0a 11 07 vroundss xmm2,xmm6,DWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 49 0a 11 07 vroundss xmm2,xmm6,DWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq xmm4,WORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq xmm4,WORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq xmm6,xmm4
[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq xmm4,WORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq xmm4,WORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw WORD PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw xmm6,xmm4,ecx,0x64
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw xmm6,xmm4,ecx,0x64
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb ecx,xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb BYTE PTR \[rcx\],xmm4,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb xmm6,xmm4,ecx,0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x64
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x64
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw WORD PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw WORD PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw WORD PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw WORD PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c5 d9 c4 f1 07 vpinsrw xmm6,xmm4,ecx,0x7
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 d9 c4 f1 07 vpinsrw xmm6,xmm4,ecx,0x7
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw xmm6,xmm4,WORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 e1 07 vpextrb ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb BYTE PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb BYTE PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb xmm6,xmm4,ecx,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 e1 07 vpextrb ecx,xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb BYTE PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb BYTE PTR \[rcx\],xmm4,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb xmm6,xmm4,ecx,0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb xmm6,xmm4,BYTE PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu xmm6,xmm4
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd ecx,xmm4
[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss xmm2,xmm6,xmm4
-[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw xmm6,xmm4,0x64
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw ecx,xmm4,0x64
+[ ]*[a-f0-9]+: c5 c9 72 f4 07 vpslld xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 fc 07 vpslldq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 f4 07 vpsllq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 71 f4 07 vpsllw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 72 e4 07 vpsrad xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 71 e4 07 vpsraw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 72 d4 07 vpsrld xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 dc 07 vpsrldq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 73 d4 07 vpsrlq xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 c9 71 d4 07 vpsrlw xmm6,xmm4,0x7
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw ecx,xmm4,0x7
[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd ecx,ymm4
[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps ecx,ymm4
[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd ecx,ymm4
[ ]*[a-f0-9]+: c5 7e e6 04 25 78 56 34 12 vcvtdq2pd ymm8,XMMWORD PTR ds:0x12345678
[ ]*[a-f0-9]+: c5 7d 5a 04 25 78 56 34 12 vcvtpd2ps xmm8,YMMWORD PTR ds:0x12345678
[ ]*[a-f0-9]+: c5 39 e0 3c 25 78 56 34 12 vpavgb xmm15,xmm8,XMMWORD PTR ds:0x12345678
-[ ]*[a-f0-9]+: c4 63 79 df 04 25 78 56 34 12 64 vaeskeygenassist xmm8,XMMWORD PTR ds:0x12345678,0x64
-[ ]*[a-f0-9]+: c4 63 79 14 04 25 78 56 34 12 64 vpextrb BYTE PTR ds:0x12345678,xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 04 25 78 56 34 12 07 vaeskeygenassist xmm8,XMMWORD PTR ds:0x12345678,0x7
+[ ]*[a-f0-9]+: c4 63 79 14 04 25 78 56 34 12 07 vpextrb BYTE PTR ds:0x12345678,xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a 3c 25 78 56 34 12 vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0x12345678
[ ]*[a-f0-9]+: c4 63 19 4a 34 25 78 56 34 12 80 vblendvps xmm14,xmm12,XMMWORD PTR ds:0x12345678,xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 3c 25 78 56 34 12 64 vpinsrb xmm15,xmm8,BYTE PTR ds:0x12345678,0x64
+[ ]*[a-f0-9]+: c4 63 39 20 3c 25 78 56 34 12 07 vpinsrb xmm15,xmm8,BYTE PTR ds:0x12345678,0x7
[ ]*[a-f0-9]+: c5 7d 6f 04 25 78 56 34 12 vmovdqa ymm8,YMMWORD PTR ds:0x12345678
[ ]*[a-f0-9]+: c5 7d 7f 04 25 78 56 34 12 vmovdqa YMMWORD PTR ds:0x12345678,ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 78 56 34 12 vpermilpd ymm15,ymm8,YMMWORD PTR ds:0x12345678
-[ ]*[a-f0-9]+: c4 63 7d 09 04 25 78 56 34 12 64 vroundpd ymm8,YMMWORD PTR ds:0x12345678,0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 04 25 78 56 34 12 64 vextractf128 XMMWORD PTR ds:0x12345678,ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 78 56 34 12 64 vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0x12345678,0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 04 25 78 56 34 12 07 vroundpd ymm8,YMMWORD PTR ds:0x12345678,0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 04 25 78 56 34 12 07 vextractf128 XMMWORD PTR ds:0x12345678,ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 78 56 34 12 07 vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0x12345678,0x7
[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 78 56 34 12 80 vblendvpd ymm14,ymm12,YMMWORD PTR ds:0x12345678,ymm8
[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr DWORD PTR \[rbp\+0x0\]
[ ]*[a-f0-9]+: c5 79 6f 45 00 vmovdqa xmm8,XMMWORD PTR \[rbp\+0x0\]
[ ]*[a-f0-9]+: c5 7e e6 45 00 vcvtdq2pd ymm8,XMMWORD PTR \[rbp\+0x0\]
[ ]*[a-f0-9]+: c5 7d 5a 45 00 vcvtpd2ps xmm8,YMMWORD PTR \[rbp\+0x0\]
[ ]*[a-f0-9]+: c5 39 e0 7d 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rbp\+0x0\]
-[ ]*[a-f0-9]+: c4 63 79 df 45 00 64 vaeskeygenassist xmm8,XMMWORD PTR \[rbp\+0x0\],0x64
-[ ]*[a-f0-9]+: c4 63 79 14 45 00 64 vpextrb BYTE PTR \[rbp\+0x0\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 45 00 07 vaeskeygenassist xmm8,XMMWORD PTR \[rbp\+0x0\],0x7
+[ ]*[a-f0-9]+: c4 63 79 14 45 00 07 vpextrb BYTE PTR \[rbp\+0x0\],xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a 7d 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+0x0\]
[ ]*[a-f0-9]+: c4 63 19 4a 75 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbp\+0x0\],xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 7d 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+0x0\],0x64
+[ ]*[a-f0-9]+: c4 63 39 20 7d 00 07 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+0x0\],0x7
[ ]*[a-f0-9]+: c5 7d 6f 45 00 vmovdqa ymm8,YMMWORD PTR \[rbp\+0x0\]
[ ]*[a-f0-9]+: c5 7d 7f 45 00 vmovdqa YMMWORD PTR \[rbp\+0x0\],ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d 7d 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rbp\+0x0\]
-[ ]*[a-f0-9]+: c4 63 7d 09 45 00 64 vroundpd ymm8,YMMWORD PTR \[rbp\+0x0\],0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 45 00 64 vextractf128 XMMWORD PTR \[rbp\+0x0\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 7d 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+0x0\],0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 45 00 07 vroundpd ymm8,YMMWORD PTR \[rbp\+0x0\],0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 45 00 07 vextractf128 XMMWORD PTR \[rbp\+0x0\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 7d 00 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+0x0\],0x7
[ ]*[a-f0-9]+: c4 63 1d 4b 75 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbp\+0x0\],ymm8
[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr DWORD PTR \[rbp\+0x99\]
[ ]*[a-f0-9]+: c5 79 6f 85 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[rbp\+0x99\]
[ ]*[a-f0-9]+: c5 7e e6 85 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[rbp\+0x99\]
[ ]*[a-f0-9]+: c5 7d 5a 85 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[rbp\+0x99\]
[ ]*[a-f0-9]+: c5 39 e0 bd 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rbp\+0x99\]
-[ ]*[a-f0-9]+: c4 63 79 df 85 99 00 00 00 64 vaeskeygenassist xmm8,XMMWORD PTR \[rbp\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 79 14 85 99 00 00 00 64 vpextrb BYTE PTR \[rbp\+0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 85 99 00 00 00 07 vaeskeygenassist xmm8,XMMWORD PTR \[rbp\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 79 14 85 99 00 00 00 07 vpextrb BYTE PTR \[rbp\+0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a bd 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+0x99\]
[ ]*[a-f0-9]+: c4 63 19 4a b5 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbp\+0x99\],xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 bd 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 39 20 bd 99 00 00 00 07 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+0x99\],0x7
[ ]*[a-f0-9]+: c5 7d 6f 85 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[rbp\+0x99\]
[ ]*[a-f0-9]+: c5 7d 7f 85 99 00 00 00 vmovdqa YMMWORD PTR \[rbp\+0x99\],ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d bd 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rbp\+0x99\]
-[ ]*[a-f0-9]+: c4 63 7d 09 85 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[rbp\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 85 99 00 00 00 64 vextractf128 XMMWORD PTR \[rbp\+0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 bd 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 85 99 00 00 00 07 vroundpd ymm8,YMMWORD PTR \[rbp\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 85 99 00 00 00 07 vextractf128 XMMWORD PTR \[rbp\+0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 bd 99 00 00 00 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+0x99\],0x7
[ ]*[a-f0-9]+: c4 63 1d 4b b5 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbp\+0x99\],ymm8
[ ]*[a-f0-9]+: c4 c1 78 ae 97 99 00 00 00 vldmxcsr DWORD PTR \[r15\+0x99\]
[ ]*[a-f0-9]+: c4 41 79 6f 87 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[r15\+0x99\]
[ ]*[a-f0-9]+: c4 41 7e e6 87 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[r15\+0x99\]
[ ]*[a-f0-9]+: c4 41 7d 5a 87 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[r15\+0x99\]
[ ]*[a-f0-9]+: c4 41 39 e0 bf 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[r15\+0x99\]
-[ ]*[a-f0-9]+: c4 43 79 df 87 99 00 00 00 64 vaeskeygenassist xmm8,XMMWORD PTR \[r15\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 43 79 14 87 99 00 00 00 64 vpextrb BYTE PTR \[r15\+0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 43 79 df 87 99 00 00 00 07 vaeskeygenassist xmm8,XMMWORD PTR \[r15\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 43 79 14 87 99 00 00 00 07 vpextrb BYTE PTR \[r15\+0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c4 41 3b 2a bf 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[r15\+0x99\]
[ ]*[a-f0-9]+: c4 43 19 4a b7 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r15\+0x99\],xmm8
-[ ]*[a-f0-9]+: c4 43 39 20 bf 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[r15\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 43 39 20 bf 99 00 00 00 07 vpinsrb xmm15,xmm8,BYTE PTR \[r15\+0x99\],0x7
[ ]*[a-f0-9]+: c4 41 7d 6f 87 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[r15\+0x99\]
[ ]*[a-f0-9]+: c4 41 7d 7f 87 99 00 00 00 vmovdqa YMMWORD PTR \[r15\+0x99\],ymm8
[ ]*[a-f0-9]+: c4 42 3d 0d bf 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[r15\+0x99\]
-[ ]*[a-f0-9]+: c4 43 7d 09 87 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[r15\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 43 7d 19 87 99 00 00 00 64 vextractf128 XMMWORD PTR \[r15\+0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 43 3d 06 bf 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r15\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 43 7d 09 87 99 00 00 00 07 vroundpd ymm8,YMMWORD PTR \[r15\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 43 7d 19 87 99 00 00 00 07 vextractf128 XMMWORD PTR \[r15\+0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 43 3d 06 bf 99 00 00 00 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r15\+0x99\],0x7
[ ]*[a-f0-9]+: c4 43 1d 4b b7 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r15\+0x99\],ymm8
-[ ]*[a-f0-9]+: c5 f8 ae 15 99 00 00 00 vldmxcsr DWORD PTR \[rip\+0x99\] # 48da <_start\+0x48da>
-[ ]*[a-f0-9]+: c5 79 6f 05 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[rip\+0x99\] # 48e2 <_start\+0x48e2>
-[ ]*[a-f0-9]+: c5 79 7f 05 99 00 00 00 vmovdqa XMMWORD PTR \[rip\+0x99\],xmm8 # 48ea <_start\+0x48ea>
-[ ]*[a-f0-9]+: c5 79 7e 05 99 00 00 00 vmovd DWORD PTR \[rip\+0x99\],xmm8 # 48f2 <_start\+0x48f2>
-[ ]*[a-f0-9]+: c5 7b 2d 05 99 00 00 00 vcvtsd2si r8d,QWORD PTR \[rip\+0x99\] # 48fa <_start\+0x48fa>
-[ ]*[a-f0-9]+: c5 7e e6 05 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[rip\+0x99\] # 4902 <_start\+0x4902>
-[ ]*[a-f0-9]+: c5 7d 5a 05 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[rip\+0x99\] # 490a <_start\+0x490a>
-[ ]*[a-f0-9]+: c5 39 e0 3d 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rip\+0x99\] # 4912 <_start\+0x4912>
-[ ]*[a-f0-9]+: c4 63 79 df 05 99 00 00 00 64 vaeskeygenassist xmm8,XMMWORD PTR \[rip\+0x99\],0x64 # 491c <_start\+0x491c>
-[ ]*[a-f0-9]+: c4 63 79 14 05 99 00 00 00 64 vpextrb BYTE PTR \[rip\+0x99\],xmm8,0x64 # 4926 <_start\+0x4926>
-[ ]*[a-f0-9]+: c5 3b 2a 3d 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rip\+0x99\] # 492e <_start\+0x492e>
-[ ]*[a-f0-9]+: c4 63 19 4a 35 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rip\+0x99\],xmm8 # 4938 <_start\+0x4938>
-[ ]*[a-f0-9]+: c4 63 39 20 3d 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rip\+0x99\],0x64 # 4942 <_start\+0x4942>
-[ ]*[a-f0-9]+: c5 7d 6f 05 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[rip\+0x99\] # 494a <_start\+0x494a>
-[ ]*[a-f0-9]+: c5 7d 7f 05 99 00 00 00 vmovdqa YMMWORD PTR \[rip\+0x99\],ymm8 # 4952 <_start\+0x4952>
-[ ]*[a-f0-9]+: c4 62 3d 0d 3d 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rip\+0x99\] # 495b <_start\+0x495b>
-[ ]*[a-f0-9]+: c4 63 7d 09 05 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[rip\+0x99\],0x64 # 4965 <_start\+0x4965>
-[ ]*[a-f0-9]+: c4 63 7d 19 05 99 00 00 00 64 vextractf128 XMMWORD PTR \[rip\+0x99\],ymm8,0x64 # 496f <_start\+0x496f>
-[ ]*[a-f0-9]+: c4 63 3d 06 3d 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rip\+0x99\],0x64 # 4979 <_start\+0x4979>
-[ ]*[a-f0-9]+: c4 63 1d 4b 35 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rip\+0x99\],ymm8 # 4983 <_start\+0x4983>
+[ ]*[a-f0-9]+: c5 f8 ae 15 99 00 00 00 vldmxcsr DWORD PTR \[rip\+0x99\] # 415a <_start\+0x415a>
+[ ]*[a-f0-9]+: c5 79 6f 05 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[rip\+0x99\] # 4162 <_start\+0x4162>
+[ ]*[a-f0-9]+: c5 79 7f 05 99 00 00 00 vmovdqa XMMWORD PTR \[rip\+0x99\],xmm8 # 416a <_start\+0x416a>
+[ ]*[a-f0-9]+: c5 79 7e 05 99 00 00 00 vmovd DWORD PTR \[rip\+0x99\],xmm8 # 4172 <_start\+0x4172>
+[ ]*[a-f0-9]+: c5 7b 2d 05 99 00 00 00 vcvtsd2si r8d,QWORD PTR \[rip\+0x99\] # 417a <_start\+0x417a>
+[ ]*[a-f0-9]+: c5 7e e6 05 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[rip\+0x99\] # 4182 <_start\+0x4182>
+[ ]*[a-f0-9]+: c5 7d 5a 05 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[rip\+0x99\] # 418a <_start\+0x418a>
+[ ]*[a-f0-9]+: c5 39 e0 3d 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rip\+0x99\] # 4192 <_start\+0x4192>
+[ ]*[a-f0-9]+: c4 63 79 df 05 99 00 00 00 07 vaeskeygenassist xmm8,XMMWORD PTR \[rip\+0x99\],0x7 # 419c <_start\+0x419c>
+[ ]*[a-f0-9]+: c4 63 79 14 05 99 00 00 00 07 vpextrb BYTE PTR \[rip\+0x99\],xmm8,0x7 # 41a6 <_start\+0x41a6>
+[ ]*[a-f0-9]+: c5 3b 2a 3d 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rip\+0x99\] # 41ae <_start\+0x41ae>
+[ ]*[a-f0-9]+: c4 63 19 4a 35 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rip\+0x99\],xmm8 # 41b8 <_start\+0x41b8>
+[ ]*[a-f0-9]+: c4 63 39 20 3d 99 00 00 00 07 vpinsrb xmm15,xmm8,BYTE PTR \[rip\+0x99\],0x7 # 41c2 <_start\+0x41c2>
+[ ]*[a-f0-9]+: c5 7d 6f 05 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[rip\+0x99\] # 41ca <_start\+0x41ca>
+[ ]*[a-f0-9]+: c5 7d 7f 05 99 00 00 00 vmovdqa YMMWORD PTR \[rip\+0x99\],ymm8 # 41d2 <_start\+0x41d2>
+[ ]*[a-f0-9]+: c4 62 3d 0d 3d 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rip\+0x99\] # 41db <_start\+0x41db>
+[ ]*[a-f0-9]+: c4 63 7d 09 05 99 00 00 00 07 vroundpd ymm8,YMMWORD PTR \[rip\+0x99\],0x7 # 41e5 <_start\+0x41e5>
+[ ]*[a-f0-9]+: c4 63 7d 19 05 99 00 00 00 07 vextractf128 XMMWORD PTR \[rip\+0x99\],ymm8,0x7 # 41ef <_start\+0x41ef>
+[ ]*[a-f0-9]+: c4 63 3d 06 3d 99 00 00 00 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rip\+0x99\],0x7 # 41f9 <_start\+0x41f9>
+[ ]*[a-f0-9]+: c4 63 1d 4b 35 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rip\+0x99\],ymm8 # 4203 <_start\+0x4203>
[ ]*[a-f0-9]+: c5 f8 ae 94 24 99 00 00 00 vldmxcsr DWORD PTR \[rsp\+0x99\]
[ ]*[a-f0-9]+: c5 79 6f 84 24 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[rsp\+0x99\]
[ ]*[a-f0-9]+: c5 79 7f 84 24 99 00 00 00 vmovdqa XMMWORD PTR \[rsp\+0x99\],xmm8
[ ]*[a-f0-9]+: c5 7e e6 84 24 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[rsp\+0x99\]
[ ]*[a-f0-9]+: c5 7d 5a 84 24 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[rsp\+0x99\]
[ ]*[a-f0-9]+: c5 39 e0 bc 24 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[rsp\+0x99\]
-[ ]*[a-f0-9]+: c4 63 79 df 84 24 99 00 00 00 64 vaeskeygenassist xmm8,XMMWORD PTR \[rsp\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 79 14 84 24 99 00 00 00 64 vpextrb BYTE PTR \[rsp\+0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 84 24 99 00 00 00 07 vaeskeygenassist xmm8,XMMWORD PTR \[rsp\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 79 14 84 24 99 00 00 00 07 vpextrb BYTE PTR \[rsp\+0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a bc 24 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\+0x99\]
[ ]*[a-f0-9]+: c4 63 19 4a b4 24 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rsp\+0x99\],xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 bc 24 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 39 20 bc 24 99 00 00 00 07 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\+0x99\],0x7
[ ]*[a-f0-9]+: c5 7d 6f 84 24 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[rsp\+0x99\]
[ ]*[a-f0-9]+: c5 7d 7f 84 24 99 00 00 00 vmovdqa YMMWORD PTR \[rsp\+0x99\],ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d bc 24 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[rsp\+0x99\]
-[ ]*[a-f0-9]+: c4 63 7d 09 84 24 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[rsp\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 84 24 99 00 00 00 64 vextractf128 XMMWORD PTR \[rsp\+0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 bc 24 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 84 24 99 00 00 00 07 vroundpd ymm8,YMMWORD PTR \[rsp\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 84 24 99 00 00 00 07 vextractf128 XMMWORD PTR \[rsp\+0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 bc 24 99 00 00 00 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\+0x99\],0x7
[ ]*[a-f0-9]+: c4 63 1d 4b b4 24 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rsp\+0x99\],ymm8
[ ]*[a-f0-9]+: c4 c1 78 ae 94 24 99 00 00 00 vldmxcsr DWORD PTR \[r12\+0x99\]
[ ]*[a-f0-9]+: c4 41 79 6f 84 24 99 00 00 00 vmovdqa xmm8,XMMWORD PTR \[r12\+0x99\]
[ ]*[a-f0-9]+: c4 41 7e e6 84 24 99 00 00 00 vcvtdq2pd ymm8,XMMWORD PTR \[r12\+0x99\]
[ ]*[a-f0-9]+: c4 41 7d 5a 84 24 99 00 00 00 vcvtpd2ps xmm8,YMMWORD PTR \[r12\+0x99\]
[ ]*[a-f0-9]+: c4 41 39 e0 bc 24 99 00 00 00 vpavgb xmm15,xmm8,XMMWORD PTR \[r12\+0x99\]
-[ ]*[a-f0-9]+: c4 43 79 df 84 24 99 00 00 00 64 vaeskeygenassist xmm8,XMMWORD PTR \[r12\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 43 79 14 84 24 99 00 00 00 64 vpextrb BYTE PTR \[r12\+0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 43 79 df 84 24 99 00 00 00 07 vaeskeygenassist xmm8,XMMWORD PTR \[r12\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 43 79 14 84 24 99 00 00 00 07 vpextrb BYTE PTR \[r12\+0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c4 41 3b 2a bc 24 99 00 00 00 vcvtsi2sd xmm15,xmm8,DWORD PTR \[r12\+0x99\]
[ ]*[a-f0-9]+: c4 43 19 4a b4 24 99 00 00 00 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r12\+0x99\],xmm8
-[ ]*[a-f0-9]+: c4 43 39 20 bc 24 99 00 00 00 64 vpinsrb xmm15,xmm8,BYTE PTR \[r12\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 43 39 20 bc 24 99 00 00 00 07 vpinsrb xmm15,xmm8,BYTE PTR \[r12\+0x99\],0x7
[ ]*[a-f0-9]+: c4 41 7d 6f 84 24 99 00 00 00 vmovdqa ymm8,YMMWORD PTR \[r12\+0x99\]
[ ]*[a-f0-9]+: c4 41 7d 7f 84 24 99 00 00 00 vmovdqa YMMWORD PTR \[r12\+0x99\],ymm8
[ ]*[a-f0-9]+: c4 42 3d 0d bc 24 99 00 00 00 vpermilpd ymm15,ymm8,YMMWORD PTR \[r12\+0x99\]
-[ ]*[a-f0-9]+: c4 43 7d 09 84 24 99 00 00 00 64 vroundpd ymm8,YMMWORD PTR \[r12\+0x99\],0x64
-[ ]*[a-f0-9]+: c4 43 7d 19 84 24 99 00 00 00 64 vextractf128 XMMWORD PTR \[r12\+0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 43 3d 06 bc 24 99 00 00 00 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r12\+0x99\],0x64
+[ ]*[a-f0-9]+: c4 43 7d 09 84 24 99 00 00 00 07 vroundpd ymm8,YMMWORD PTR \[r12\+0x99\],0x7
+[ ]*[a-f0-9]+: c4 43 7d 19 84 24 99 00 00 00 07 vextractf128 XMMWORD PTR \[r12\+0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 43 3d 06 bc 24 99 00 00 00 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r12\+0x99\],0x7
[ ]*[a-f0-9]+: c4 43 1d 4b b4 24 99 00 00 00 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r12\+0x99\],ymm8
[ ]*[a-f0-9]+: c5 f8 ae 14 25 67 ff ff ff vldmxcsr DWORD PTR ds:0xffffffffffffff67
[ ]*[a-f0-9]+: c5 79 6f 04 25 67 ff ff ff vmovdqa xmm8,XMMWORD PTR ds:0xffffffffffffff67
[ ]*[a-f0-9]+: c5 7e e6 04 25 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR ds:0xffffffffffffff67
[ ]*[a-f0-9]+: c5 7d 5a 04 25 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR ds:0xffffffffffffff67
[ ]*[a-f0-9]+: c5 39 e0 3c 25 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR ds:0xffffffffffffff67
-[ ]*[a-f0-9]+: c4 63 79 df 04 25 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR ds:0xffffffffffffff67,0x64
-[ ]*[a-f0-9]+: c4 63 79 14 04 25 67 ff ff ff 64 vpextrb BYTE PTR ds:0xffffffffffffff67,xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 04 25 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR ds:0xffffffffffffff67,0x7
+[ ]*[a-f0-9]+: c4 63 79 14 04 25 67 ff ff ff 07 vpextrb BYTE PTR ds:0xffffffffffffff67,xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a 3c 25 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0xffffffffffffff67
[ ]*[a-f0-9]+: c4 63 19 4a 34 25 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR ds:0xffffffffffffff67,xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 3c 25 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR ds:0xffffffffffffff67,0x64
+[ ]*[a-f0-9]+: c4 63 39 20 3c 25 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR ds:0xffffffffffffff67,0x7
[ ]*[a-f0-9]+: c5 7d 6f 04 25 67 ff ff ff vmovdqa ymm8,YMMWORD PTR ds:0xffffffffffffff67
[ ]*[a-f0-9]+: c5 7d 7f 04 25 67 ff ff ff vmovdqa YMMWORD PTR ds:0xffffffffffffff67,ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR ds:0xffffffffffffff67
-[ ]*[a-f0-9]+: c4 63 7d 09 04 25 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR ds:0xffffffffffffff67,0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 04 25 67 ff ff ff 64 vextractf128 XMMWORD PTR ds:0xffffffffffffff67,ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0xffffffffffffff67,0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 04 25 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR ds:0xffffffffffffff67,0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 04 25 67 ff ff ff 07 vextractf128 XMMWORD PTR ds:0xffffffffffffff67,ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0xffffffffffffff67,0x7
[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR ds:0xffffffffffffff67,ymm8
[ ]*[a-f0-9]+: c5 f8 ae 14 65 67 ff ff ff vldmxcsr DWORD PTR \[riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 79 6f 04 65 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 7e e6 04 65 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 7d 5a 04 65 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 39 e0 3c 65 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[riz\*2-0x99\]
-[ ]*[a-f0-9]+: c4 63 79 df 04 65 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR \[riz\*2-0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 79 14 04 65 67 ff ff ff 64 vpextrb BYTE PTR \[riz\*2-0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 04 65 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR \[riz\*2-0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 79 14 04 65 67 ff ff ff 07 vpextrb BYTE PTR \[riz\*2-0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a 3c 65 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[riz\*2-0x99\]
[ ]*[a-f0-9]+: c4 63 19 4a 34 65 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[riz\*2-0x99\],xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 3c 65 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[riz\*2-0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 39 20 3c 65 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR \[riz\*2-0x99\],0x7
[ ]*[a-f0-9]+: c5 7d 6f 04 65 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 7d 7f 04 65 67 ff ff ff vmovdqa YMMWORD PTR \[riz\*2-0x99\],ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d 3c 65 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[riz\*2-0x99\]
-[ ]*[a-f0-9]+: c4 63 7d 09 04 65 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[riz\*2-0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 04 65 67 ff ff ff 64 vextractf128 XMMWORD PTR \[riz\*2-0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 3c 65 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[riz\*2-0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 04 65 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR \[riz\*2-0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 04 65 67 ff ff ff 07 vextractf128 XMMWORD PTR \[riz\*2-0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 3c 65 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[riz\*2-0x99\],0x7
[ ]*[a-f0-9]+: c4 63 1d 4b 34 65 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[riz\*2-0x99\],ymm8
[ ]*[a-f0-9]+: c5 f8 ae 94 23 67 ff ff ff vldmxcsr DWORD PTR \[rbx\+riz\*1-0x99\]
[ ]*[a-f0-9]+: c5 79 6f 84 23 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rbx\+riz\*1-0x99\]
[ ]*[a-f0-9]+: c5 7e e6 84 23 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rbx\+riz\*1-0x99\]
[ ]*[a-f0-9]+: c5 7d 5a 84 23 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rbx\+riz\*1-0x99\]
[ ]*[a-f0-9]+: c5 39 e0 bc 23 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rbx\+riz\*1-0x99\]
-[ ]*[a-f0-9]+: c4 63 79 df 84 23 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR \[rbx\+riz\*1-0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 79 14 84 23 67 ff ff ff 64 vpextrb BYTE PTR \[rbx\+riz\*1-0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 84 23 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR \[rbx\+riz\*1-0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 79 14 84 23 67 ff ff ff 07 vpextrb BYTE PTR \[rbx\+riz\*1-0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a bc 23 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbx\+riz\*1-0x99\]
[ ]*[a-f0-9]+: c4 63 19 4a b4 23 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbx\+riz\*1-0x99\],xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 bc 23 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbx\+riz\*1-0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 39 20 bc 23 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR \[rbx\+riz\*1-0x99\],0x7
[ ]*[a-f0-9]+: c5 7d 6f 84 23 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\]
[ ]*[a-f0-9]+: c5 7d 7f 84 23 67 ff ff ff vmovdqa YMMWORD PTR \[rbx\+riz\*1-0x99\],ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d bc 23 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\]
-[ ]*[a-f0-9]+: c4 63 7d 09 84 23 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 84 23 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rbx\+riz\*1-0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 bc 23 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 84 23 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 84 23 67 ff ff ff 07 vextractf128 XMMWORD PTR \[rbx\+riz\*1-0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 bc 23 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*1-0x99\],0x7
[ ]*[a-f0-9]+: c4 63 1d 4b b4 23 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbx\+riz\*1-0x99\],ymm8
[ ]*[a-f0-9]+: c5 f8 ae 94 63 67 ff ff ff vldmxcsr DWORD PTR \[rbx\+riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 79 6f 84 63 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rbx\+riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 7e e6 84 63 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rbx\+riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 7d 5a 84 63 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rbx\+riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 39 e0 bc 63 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rbx\+riz\*2-0x99\]
-[ ]*[a-f0-9]+: c4 63 79 df 84 63 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR \[rbx\+riz\*2-0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 79 14 84 63 67 ff ff ff 64 vpextrb BYTE PTR \[rbx\+riz\*2-0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 63 79 df 84 63 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR \[rbx\+riz\*2-0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 79 14 84 63 67 ff ff ff 07 vpextrb BYTE PTR \[rbx\+riz\*2-0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c5 3b 2a bc 63 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbx\+riz\*2-0x99\]
[ ]*[a-f0-9]+: c4 63 19 4a b4 63 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbx\+riz\*2-0x99\],xmm8
-[ ]*[a-f0-9]+: c4 63 39 20 bc 63 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbx\+riz\*2-0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 39 20 bc 63 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR \[rbx\+riz\*2-0x99\],0x7
[ ]*[a-f0-9]+: c5 7d 6f 84 63 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\]
[ ]*[a-f0-9]+: c5 7d 7f 84 63 67 ff ff ff vmovdqa YMMWORD PTR \[rbx\+riz\*2-0x99\],ymm8
[ ]*[a-f0-9]+: c4 62 3d 0d bc 63 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\]
-[ ]*[a-f0-9]+: c4 63 7d 09 84 63 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\],0x64
-[ ]*[a-f0-9]+: c4 63 7d 19 84 63 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rbx\+riz\*2-0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 63 3d 06 bc 63 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\],0x64
+[ ]*[a-f0-9]+: c4 63 7d 09 84 63 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\],0x7
+[ ]*[a-f0-9]+: c4 63 7d 19 84 63 67 ff ff ff 07 vextractf128 XMMWORD PTR \[rbx\+riz\*2-0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 63 3d 06 bc 63 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbx\+riz\*2-0x99\],0x7
[ ]*[a-f0-9]+: c4 63 1d 4b b4 63 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbx\+riz\*2-0x99\],ymm8
[ ]*[a-f0-9]+: c4 81 78 ae 94 bc 67 ff ff ff vldmxcsr DWORD PTR \[r12\+r15\*4-0x99\]
[ ]*[a-f0-9]+: c4 01 79 6f 84 bc 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[r12\+r15\*4-0x99\]
[ ]*[a-f0-9]+: c4 01 7e e6 84 bc 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[r12\+r15\*4-0x99\]
[ ]*[a-f0-9]+: c4 01 7d 5a 84 bc 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[r12\+r15\*4-0x99\]
[ ]*[a-f0-9]+: c4 01 39 e0 bc bc 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[r12\+r15\*4-0x99\]
-[ ]*[a-f0-9]+: c4 03 79 df 84 bc 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR \[r12\+r15\*4-0x99\],0x64
-[ ]*[a-f0-9]+: c4 03 79 14 84 bc 67 ff ff ff 64 vpextrb BYTE PTR \[r12\+r15\*4-0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 03 79 df 84 bc 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR \[r12\+r15\*4-0x99\],0x7
+[ ]*[a-f0-9]+: c4 03 79 14 84 bc 67 ff ff ff 07 vpextrb BYTE PTR \[r12\+r15\*4-0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c4 01 3b 2a bc bc 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[r12\+r15\*4-0x99\]
[ ]*[a-f0-9]+: c4 03 19 4a b4 bc 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r12\+r15\*4-0x99\],xmm8
-[ ]*[a-f0-9]+: c4 03 39 20 bc bc 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[r12\+r15\*4-0x99\],0x64
+[ ]*[a-f0-9]+: c4 03 39 20 bc bc 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR \[r12\+r15\*4-0x99\],0x7
[ ]*[a-f0-9]+: c4 01 7d 6f 84 bc 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\]
[ ]*[a-f0-9]+: c4 01 7d 7f 84 bc 67 ff ff ff vmovdqa YMMWORD PTR \[r12\+r15\*4-0x99\],ymm8
[ ]*[a-f0-9]+: c4 02 3d 0d bc bc 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\]
-[ ]*[a-f0-9]+: c4 03 7d 09 84 bc 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\],0x64
-[ ]*[a-f0-9]+: c4 03 7d 19 84 bc 67 ff ff ff 64 vextractf128 XMMWORD PTR \[r12\+r15\*4-0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 03 3d 06 bc bc 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\],0x64
+[ ]*[a-f0-9]+: c4 03 7d 09 84 bc 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\],0x7
+[ ]*[a-f0-9]+: c4 03 7d 19 84 bc 67 ff ff ff 07 vextractf128 XMMWORD PTR \[r12\+r15\*4-0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 03 3d 06 bc bc 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r12\+r15\*4-0x99\],0x7
[ ]*[a-f0-9]+: c4 03 1d 4b b4 bc 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r12\+r15\*4-0x99\],ymm8
[ ]*[a-f0-9]+: c4 81 78 ae 94 f8 67 ff ff ff vldmxcsr DWORD PTR \[r8\+r15\*8-0x99\]
[ ]*[a-f0-9]+: c4 01 79 6f 84 f8 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[r8\+r15\*8-0x99\]
[ ]*[a-f0-9]+: c4 01 7e e6 84 f8 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[r8\+r15\*8-0x99\]
[ ]*[a-f0-9]+: c4 01 7d 5a 84 f8 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[r8\+r15\*8-0x99\]
[ ]*[a-f0-9]+: c4 01 39 e0 bc f8 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[r8\+r15\*8-0x99\]
-[ ]*[a-f0-9]+: c4 03 79 df 84 f8 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR \[r8\+r15\*8-0x99\],0x64
-[ ]*[a-f0-9]+: c4 03 79 14 84 f8 67 ff ff ff 64 vpextrb BYTE PTR \[r8\+r15\*8-0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 03 79 df 84 f8 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR \[r8\+r15\*8-0x99\],0x7
+[ ]*[a-f0-9]+: c4 03 79 14 84 f8 67 ff ff ff 07 vpextrb BYTE PTR \[r8\+r15\*8-0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c4 01 3b 2a bc f8 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[r8\+r15\*8-0x99\]
[ ]*[a-f0-9]+: c4 03 19 4a b4 f8 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[r8\+r15\*8-0x99\],xmm8
-[ ]*[a-f0-9]+: c4 03 39 20 bc f8 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[r8\+r15\*8-0x99\],0x64
+[ ]*[a-f0-9]+: c4 03 39 20 bc f8 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR \[r8\+r15\*8-0x99\],0x7
[ ]*[a-f0-9]+: c4 01 7d 6f 84 f8 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\]
[ ]*[a-f0-9]+: c4 01 7d 7f 84 f8 67 ff ff ff vmovdqa YMMWORD PTR \[r8\+r15\*8-0x99\],ymm8
[ ]*[a-f0-9]+: c4 02 3d 0d bc f8 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\]
-[ ]*[a-f0-9]+: c4 03 7d 09 84 f8 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\],0x64
-[ ]*[a-f0-9]+: c4 03 7d 19 84 f8 67 ff ff ff 64 vextractf128 XMMWORD PTR \[r8\+r15\*8-0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 03 3d 06 bc f8 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\],0x64
+[ ]*[a-f0-9]+: c4 03 7d 09 84 f8 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\],0x7
+[ ]*[a-f0-9]+: c4 03 7d 19 84 f8 67 ff ff ff 07 vextractf128 XMMWORD PTR \[r8\+r15\*8-0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 03 3d 06 bc f8 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[r8\+r15\*8-0x99\],0x7
[ ]*[a-f0-9]+: c4 03 1d 4b b4 f8 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[r8\+r15\*8-0x99\],ymm8
[ ]*[a-f0-9]+: c4 a1 78 ae 94 a5 67 ff ff ff vldmxcsr DWORD PTR \[rbp\+r12\*4-0x99\]
[ ]*[a-f0-9]+: c4 21 79 6f 84 a5 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rbp\+r12\*4-0x99\]
[ ]*[a-f0-9]+: c4 21 7e e6 84 a5 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rbp\+r12\*4-0x99\]
[ ]*[a-f0-9]+: c4 21 7d 5a 84 a5 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rbp\+r12\*4-0x99\]
[ ]*[a-f0-9]+: c4 21 39 e0 bc a5 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rbp\+r12\*4-0x99\]
-[ ]*[a-f0-9]+: c4 23 79 df 84 a5 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR \[rbp\+r12\*4-0x99\],0x64
-[ ]*[a-f0-9]+: c4 23 79 14 84 a5 67 ff ff ff 64 vpextrb BYTE PTR \[rbp\+r12\*4-0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 23 79 df 84 a5 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR \[rbp\+r12\*4-0x99\],0x7
+[ ]*[a-f0-9]+: c4 23 79 14 84 a5 67 ff ff ff 07 vpextrb BYTE PTR \[rbp\+r12\*4-0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c4 21 3b 2a bc a5 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rbp\+r12\*4-0x99\]
[ ]*[a-f0-9]+: c4 23 19 4a b4 a5 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rbp\+r12\*4-0x99\],xmm8
-[ ]*[a-f0-9]+: c4 23 39 20 bc a5 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+r12\*4-0x99\],0x64
+[ ]*[a-f0-9]+: c4 23 39 20 bc a5 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR \[rbp\+r12\*4-0x99\],0x7
[ ]*[a-f0-9]+: c4 21 7d 6f 84 a5 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rbp\+r12\*4-0x99\]
[ ]*[a-f0-9]+: c4 21 7d 7f 84 a5 67 ff ff ff vmovdqa YMMWORD PTR \[rbp\+r12\*4-0x99\],ymm8
[ ]*[a-f0-9]+: c4 22 3d 0d bc a5 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rbp\+r12\*4-0x99\]
-[ ]*[a-f0-9]+: c4 23 7d 09 84 a5 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rbp\+r12\*4-0x99\],0x64
-[ ]*[a-f0-9]+: c4 23 7d 19 84 a5 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rbp\+r12\*4-0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 23 3d 06 bc a5 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+r12\*4-0x99\],0x64
+[ ]*[a-f0-9]+: c4 23 7d 09 84 a5 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR \[rbp\+r12\*4-0x99\],0x7
+[ ]*[a-f0-9]+: c4 23 7d 19 84 a5 67 ff ff ff 07 vextractf128 XMMWORD PTR \[rbp\+r12\*4-0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 23 3d 06 bc a5 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rbp\+r12\*4-0x99\],0x7
[ ]*[a-f0-9]+: c4 23 1d 4b b4 a5 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rbp\+r12\*4-0x99\],ymm8
[ ]*[a-f0-9]+: c4 a1 78 ae 94 2c 67 ff ff ff vldmxcsr DWORD PTR \[rsp\+r13\*1-0x99\]
[ ]*[a-f0-9]+: c4 21 79 6f 84 2c 67 ff ff ff vmovdqa xmm8,XMMWORD PTR \[rsp\+r13\*1-0x99\]
[ ]*[a-f0-9]+: c4 21 7e e6 84 2c 67 ff ff ff vcvtdq2pd ymm8,XMMWORD PTR \[rsp\+r13\*1-0x99\]
[ ]*[a-f0-9]+: c4 21 7d 5a 84 2c 67 ff ff ff vcvtpd2ps xmm8,YMMWORD PTR \[rsp\+r13\*1-0x99\]
[ ]*[a-f0-9]+: c4 21 39 e0 bc 2c 67 ff ff ff vpavgb xmm15,xmm8,XMMWORD PTR \[rsp\+r13\*1-0x99\]
-[ ]*[a-f0-9]+: c4 23 79 df 84 2c 67 ff ff ff 64 vaeskeygenassist xmm8,XMMWORD PTR \[rsp\+r13\*1-0x99\],0x64
-[ ]*[a-f0-9]+: c4 23 79 14 84 2c 67 ff ff ff 64 vpextrb BYTE PTR \[rsp\+r13\*1-0x99\],xmm8,0x64
+[ ]*[a-f0-9]+: c4 23 79 df 84 2c 67 ff ff ff 07 vaeskeygenassist xmm8,XMMWORD PTR \[rsp\+r13\*1-0x99\],0x7
+[ ]*[a-f0-9]+: c4 23 79 14 84 2c 67 ff ff ff 07 vpextrb BYTE PTR \[rsp\+r13\*1-0x99\],xmm8,0x7
[ ]*[a-f0-9]+: c4 21 3b 2a bc 2c 67 ff ff ff vcvtsi2sd xmm15,xmm8,DWORD PTR \[rsp\+r13\*1-0x99\]
[ ]*[a-f0-9]+: c4 23 19 4a b4 2c 67 ff ff ff 80 vblendvps xmm14,xmm12,XMMWORD PTR \[rsp\+r13\*1-0x99\],xmm8
-[ ]*[a-f0-9]+: c4 23 39 20 bc 2c 67 ff ff ff 64 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\+r13\*1-0x99\],0x64
+[ ]*[a-f0-9]+: c4 23 39 20 bc 2c 67 ff ff ff 07 vpinsrb xmm15,xmm8,BYTE PTR \[rsp\+r13\*1-0x99\],0x7
[ ]*[a-f0-9]+: c4 21 7d 6f 84 2c 67 ff ff ff vmovdqa ymm8,YMMWORD PTR \[rsp\+r13\*1-0x99\]
[ ]*[a-f0-9]+: c4 21 7d 7f 84 2c 67 ff ff ff vmovdqa YMMWORD PTR \[rsp\+r13\*1-0x99\],ymm8
[ ]*[a-f0-9]+: c4 22 3d 0d bc 2c 67 ff ff ff vpermilpd ymm15,ymm8,YMMWORD PTR \[rsp\+r13\*1-0x99\]
-[ ]*[a-f0-9]+: c4 23 7d 09 84 2c 67 ff ff ff 64 vroundpd ymm8,YMMWORD PTR \[rsp\+r13\*1-0x99\],0x64
-[ ]*[a-f0-9]+: c4 23 7d 19 84 2c 67 ff ff ff 64 vextractf128 XMMWORD PTR \[rsp\+r13\*1-0x99\],ymm8,0x64
-[ ]*[a-f0-9]+: c4 23 3d 06 bc 2c 67 ff ff ff 64 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\+r13\*1-0x99\],0x64
+[ ]*[a-f0-9]+: c4 23 7d 09 84 2c 67 ff ff ff 07 vroundpd ymm8,YMMWORD PTR \[rsp\+r13\*1-0x99\],0x7
+[ ]*[a-f0-9]+: c4 23 7d 19 84 2c 67 ff ff ff 07 vextractf128 XMMWORD PTR \[rsp\+r13\*1-0x99\],ymm8,0x7
+[ ]*[a-f0-9]+: c4 23 3d 06 bc 2c 67 ff ff ff 07 vperm2f128 ymm15,ymm8,YMMWORD PTR \[rsp\+r13\*1-0x99\],0x7
[ ]*[a-f0-9]+: c4 23 1d 4b b4 2c 67 ff ff ff 80 vblendvpd ymm14,ymm12,YMMWORD PTR \[rsp\+r13\*1-0x99\],ymm8
[ ]*[a-f0-9]+: c4 41 79 50 c0 vmovmskpd r8d,xmm8
-[ ]*[a-f0-9]+: c4 c1 01 72 f0 64 vpslld xmm15,xmm8,0x64
+[ ]*[a-f0-9]+: c4 c1 01 72 f0 07 vpslld xmm15,xmm8,0x7
[ ]*[a-f0-9]+: c4 41 7c 50 c0 vmovmskps r8d,ymm8
[ ]*[a-f0-9]+: c4 41 79 6f f8 vmovdqa xmm15,xmm8
[ ]*[a-f0-9]+: c4 41 79 7e c0 vmovd r8d,xmm8
[ ]*[a-f0-9]+: c4 41 7b 2d c0 vcvtsd2si r8d,xmm8
[ ]*[a-f0-9]+: c4 41 7e e6 c0 vcvtdq2pd ymm8,xmm8
[ ]*[a-f0-9]+: c4 41 7d 5a c0 vcvtpd2ps xmm8,ymm8
-[ ]*[a-f0-9]+: c4 43 79 df f8 64 vaeskeygenassist xmm15,xmm8,0x64
-[ ]*[a-f0-9]+: c4 43 79 14 c0 64 vpextrb r8d,xmm8,0x64
+[ ]*[a-f0-9]+: c4 43 79 df f8 07 vaeskeygenassist xmm15,xmm8,0x7
+[ ]*[a-f0-9]+: c4 43 79 14 c0 07 vpextrb r8d,xmm8,0x7
[ ]*[a-f0-9]+: c4 41 3b 2a f8 vcvtsi2sd xmm15,xmm8,r8d
[ ]*[a-f0-9]+: c4 43 19 4a f0 80 vblendvps xmm14,xmm12,xmm8,xmm8
-[ ]*[a-f0-9]+: c4 43 39 20 f8 64 vpinsrb xmm15,xmm8,r8d,0x64
+[ ]*[a-f0-9]+: c4 43 39 20 f8 07 vpinsrb xmm15,xmm8,r8d,0x7
[ ]*[a-f0-9]+: c4 41 7d 6f f8 vmovdqa ymm15,ymm8
[ ]*[a-f0-9]+: c4 42 05 0d e0 vpermilpd ymm12,ymm15,ymm8
-[ ]*[a-f0-9]+: c4 43 7d 09 f8 64 vroundpd ymm15,ymm8,0x64
-[ ]*[a-f0-9]+: c4 43 7d 19 c0 64 vextractf128 xmm8,ymm8,0x64
-[ ]*[a-f0-9]+: c4 43 05 06 e0 64 vperm2f128 ymm12,ymm15,ymm8,0x64
+[ ]*[a-f0-9]+: c4 43 7d 09 f8 07 vroundpd ymm15,ymm8,0x7
+[ ]*[a-f0-9]+: c4 43 7d 19 c0 07 vextractf128 xmm8,ymm8,0x7
+[ ]*[a-f0-9]+: c4 43 05 06 e0 07 vperm2f128 ymm12,ymm15,ymm8,0x7
[ ]*[a-f0-9]+: c4 43 1d 4b f7 80 vblendvpd ymm14,ymm12,ymm15,ymm8
-[ ]*[a-f0-9]+: c4 43 3d 18 f8 64 vinsertf128 ymm15,ymm8,xmm8,0x64
+[ ]*[a-f0-9]+: c4 43 3d 18 f8 07 vinsertf128 ymm15,ymm8,xmm8,0x7
[ ]*[a-f0-9]+: c4 61 fb 2d 01 vcvtsd2si r8,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 43 79 17 c0 0a vextractps r8d,xmm8,0xa
[ ]*[a-f0-9]+: c4 61 fa 2d 01 vcvtss2si r8,DWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 41 01 c4 c0 64 vpinsrw xmm8,xmm15,r8d,0x64
+[ ]*[a-f0-9]+: c4 41 01 c4 c0 07 vpinsrw xmm8,xmm15,r8d,0x7
#pass
[ ]*[a-f0-9]+: c4 e2 4d 2f 21 vmaskmovpd %ymm4,%ymm6,\(%rcx\)
[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps \(%rcx\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps %ymm4,%ymm6,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd \$0x64,\(%rcx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps \$0x64,\(%rcx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd \$0x64,\(%rcx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps \$0x64,\(%rcx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 05 d6 07 vpermilpd \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 05 31 07 vpermilpd \$0x7,\(%rcx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 04 d6 07 vpermilps \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 04 31 07 vpermilps \$0x7,\(%rcx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 09 d6 07 vroundpd \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 09 31 07 vroundpd \$0x7,\(%rcx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 08 d6 07 vroundps \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 08 31 07 vroundps \$0x7,\(%rcx\),%ymm6
[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd \(%rcx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc 58 d4 vaddps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2psy \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq %ymm4,%xmm4
[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dqy \(%rcx\),%xmm4
-[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 5b f4 vcvtdq2ps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 5b f4 vcvtps2dq %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 5b f4 vcvttps2dq %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 ff 12 f4 vmovddup %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 16 f4 vmovshdup %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 12 f4 vmovsldup %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 10 21 vmovups \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest %ymm4,%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 17 f4 vptest %ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 53 f4 vrcpps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 52 f4 vrsqrtps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 51 f4 vsqrtpd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 51 f4 vsqrtps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0f f4 vtestpd %ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0e f4 vtestps %ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps \$0x64,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0d d4 07 vblendpd \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0d 11 07 vblendpd \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0c d4 07 vblendps \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0c 11 07 vblendps \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd \(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps \(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 40 d4 07 vdpps \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 40 11 07 vdpps \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 06 d4 07 vperm2f128 \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 06 11 07 vperm2f128 \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c6 d4 07 vshufpd \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%rcx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%rcx\),%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps %ymm4,%ymm6,%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps %ymm4,\(%rcx\),%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 69 39 20 vfmaddpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 68 fc 20 vfmaddps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 68 39 20 vfmaddps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5d fc 20 vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5d 39 20 vfmaddsubpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5c fc 20 vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5c 39 20 vfmaddsubps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5f fc 20 vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5f 39 20 vfmsubaddpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5e fc 20 vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5e 39 20 vfmsubaddps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6d fc 20 vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6d 39 20 vfmsubpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6c fc 20 vfmsubps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6c 39 20 vfmsubps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 79 fc 20 vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 79 39 20 vfnmaddpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 78 fc 20 vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 78 39 20 vfnmaddps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7d fc 20 vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7d 39 20 vfnmsubpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7c fc 20 vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7c 39 20 vfnmsubps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd \$0xa,%ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd \$0xa,\(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps \$0xa,%ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps \$0xa,\(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 \$0x64,%xmm4,%ymm4,%ymm6
-[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 \$0x64,\(%rcx\),%ymm4,%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 \$0x64,%ymm4,%xmm4
-[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 \$0x64,%ymm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 5d 18 f4 07 vinsertf128 \$0x7,%xmm4,%ymm4,%ymm6
+[ ]*[a-f0-9]+: c4 e3 5d 18 31 07 vinsertf128 \$0x7,\(%rcx\),%ymm4,%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 19 e4 07 vextractf128 \$0x7,%ymm4,%xmm4
+[ ]*[a-f0-9]+: c4 e3 7d 19 21 07 vextractf128 \$0x7,%ymm4,\(%rcx\)
[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%rcx\),%xmm6,%xmm7
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 df f4 64 vaeskeygenassist \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 df 31 64 vaeskeygenassist \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps \$0x64,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 df 31 07 vaeskeygenassist \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 61 f4 07 vpcmpestri \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 61 31 07 vpcmpestri \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 60 f4 07 vpcmpestrm \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 60 31 07 vpcmpestrm \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 63 f4 07 vpcmpistri \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 63 31 07 vpcmpistri \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 62 f4 07 vpcmpistrm \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 62 31 07 vpcmpistrm \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 05 f4 07 vpermilpd \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 05 31 07 vpermilpd \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 04 f4 07 vpermilps \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 04 31 07 vpermilps \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c5 f9 70 f4 07 vpshufd \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 f9 70 31 07 vpshufd \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c5 fa 70 f4 07 vpshufhw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 fa 70 31 07 vpshufhw \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c5 fb 70 f4 07 vpshuflw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 fb 70 31 07 vpshuflw \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 09 f4 07 vroundpd \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 09 31 07 vroundpd \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 08 f4 07 vroundps \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 08 31 07 vroundps \$0x7,\(%rcx\),%xmm6
[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps %xmm4,%xmm6,\(%rcx\)
[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd %xmm4,%xmm6,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps \$0x64,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0d d4 07 vblendpd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0d 11 07 vblendpd \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0c d4 07 vblendps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0c 11 07 vblendps \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c2 11 07 vcmpordpd \(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c2 11 07 vcmpordps \(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 41 d4 07 vdppd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 41 11 07 vdppd \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 40 d4 07 vdpps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 40 11 07 vdpps \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 42 d4 07 vmpsadbw \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 42 11 07 vmpsadbw \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0f d4 07 vpalignr \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0f 11 07 vpalignr \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0e d4 07 vpblendw \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0e 11 07 vpblendw \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c6 d4 07 vshufpd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%rcx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps %xmm4,%xmm6,%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4a 39 40 vblendvps %xmm4,\(%rcx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb %xmm4,%xmm6,%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 69 fc 20 vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 69 39 20 vfmaddpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 69 39 20 vfmaddpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 68 fc 20 vfmaddps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 68 39 20 vfmaddps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 68 39 20 vfmaddps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5d fc 20 vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5d 39 20 vfmaddsubpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5d 39 20 vfmaddsubpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5c fc 20 vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5c 39 20 vfmaddsubps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5c 39 20 vfmaddsubps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5f fc 20 vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5f 39 20 vfmsubaddpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5f 39 20 vfmsubaddpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5e fc 20 vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5e 39 20 vfmsubaddps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5e 39 20 vfmsubaddps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6d fc 20 vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6d 39 20 vfmsubpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6d 39 20 vfmsubpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6c fc 20 vfmsubps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6c 39 20 vfmsubps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6c 39 20 vfmsubps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 79 fc 20 vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 79 39 20 vfnmaddpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 79 39 20 vfnmaddpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 78 fc 20 vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 78 39 20 vfnmaddps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 78 39 20 vfnmaddps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7d fc 20 vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7d 39 20 vfnmsubpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7d 39 20 vfnmsubpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7c fc 20 vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7c 39 20 vfnmsubps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7c 39 20 vfnmsubps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd \$0xa,%xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd \$0xa,\(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd \$0xa,%xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps \$0xa,%xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps \$0xa,\(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps \$0xa,%xmm4,\(%rcx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c4 e1 db 2a 31 vcvtsi2sdq \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e1 da 2a f1 vcvtsi2ss %rcx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e1 da 2a 31 vcvtsi2ssq \(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 d9 22 f1 64 vpinsrq \$0x64,%rcx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 d9 22 31 64 vpinsrq \$0x64,\(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 f9 16 e1 64 vpextrq \$0x64,%xmm4,%rcx
-[ ]*[a-f0-9]+: c4 e3 f9 16 21 64 vpextrq \$0x64,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 d9 22 f1 07 vpinsrq \$0x7,%rcx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d9 22 31 07 vpinsrq \$0x7,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 f9 16 e1 07 vpextrq \$0x7,%xmm4,%rcx
+[ ]*[a-f0-9]+: c4 e3 f9 16 21 07 vpextrq \$0x7,%xmm4,\(%rcx\)
[ ]*[a-f0-9]+: c5 d9 12 31 vmovlpd \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 d8 12 31 vmovlps \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps \(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 c9 6b fc 20 vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6b 39 20 vfmaddsd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6b 39 20 vfmaddsd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6f fc 20 vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6f 39 20 vfmsubsd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6f 39 20 vfmsubsd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7b fc 20 vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7b 39 20 vfnmaddsd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7b 39 20 vfnmaddsd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7f fc 20 vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7f 39 20 vfnmsubsd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7f 39 20 vfnmsubsd %xmm4,\(%rcx\),%xmm2,%xmm7
+[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd \(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0b d4 07 vroundsd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0b 11 07 vroundsd \$0x7,\(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd \(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 5a d4 vcvtsd2ss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 1e vcmpgt_oqsd \(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd \(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%rcx\)
+[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%rcx\)
[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca 58 11 vaddss \(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca 5a d4 vcvtss2sd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx
[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps %xmm4,%ecx
[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb %xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 79 17 e1 07 vextractps \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 79 16 e1 07 vpextrd \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 16 21 07 vpextrd \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 79 17 e1 07 vextractps \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps \$0x7,%xmm4,\(%rcx\)
[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd %ecx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sdl \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss %ecx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ssl \(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 c9 6a fc 20 vfmaddss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6a 39 20 vfmaddss \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6a 39 20 vfmaddss %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6e fc 20 vfmsubss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6e 39 20 vfmsubss \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6e 39 20 vfmsubss %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7a fc 20 vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7a 39 20 vfnmaddss \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7a 39 20 vfnmaddss %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7e fc 20 vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7e 39 20 vfnmsubss \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7e 39 20 vfnmsubss %xmm4,\(%rcx\),%xmm2,%xmm7
+[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss \(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 21 d4 07 vinsertps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 21 11 07 vinsertps \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0a d4 07 vroundss \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0a 11 07 vroundss \$0x7,\(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq \(%rcx\),%xmm4
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c5 d9 c4 f1 07 vpinsrw \$0x7,%ecx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw \$0x7,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 d9 c4 f1 07 vpinsrw \$0x7,%ecx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw \$0x7,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 14 e1 07 vpextrb \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb \$0x7,%ecx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb \$0x7,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 14 e1 07 vpextrb \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb \$0x7,%ecx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb \$0x7,\(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx
[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
+[ ]*[a-f0-9]+: c5 c9 72 f4 07 vpslld \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 fc 07 vpslldq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 f4 07 vpsllq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 71 f4 07 vpsllw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 72 e4 07 vpsrad \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 71 e4 07 vpsraw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 72 d4 07 vpsrld \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 dc 07 vpsrldq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 d4 07 vpsrlq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 71 d4 07 vpsrlw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw \$0x7,%xmm4,%ecx
[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd %ymm4,%ecx
[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps %ymm4,%ecx
[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd %ymm4,%ecx
[ ]*[a-f0-9]+: c5 7e e6 04 25 78 56 34 12 vcvtdq2pd 0x12345678,%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 04 25 78 56 34 12 vcvtpd2psy 0x12345678,%xmm8
[ ]*[a-f0-9]+: c5 39 e0 3c 25 78 56 34 12 vpavgb 0x12345678,%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 04 25 78 56 34 12 64 vaeskeygenassist \$0x64,0x12345678,%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 04 25 78 56 34 12 64 vpextrb \$0x64,%xmm8,0x12345678
+[ ]*[a-f0-9]+: c4 63 79 df 04 25 78 56 34 12 07 vaeskeygenassist \$0x7,0x12345678,%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 04 25 78 56 34 12 07 vpextrb \$0x7,%xmm8,0x12345678
[ ]*[a-f0-9]+: c5 3b 2a 3c 25 78 56 34 12 vcvtsi2sdl 0x12345678,%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a 34 25 78 56 34 12 80 vblendvps %xmm8,0x12345678,%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 3c 25 78 56 34 12 64 vpinsrb \$0x64,0x12345678,%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 3c 25 78 56 34 12 07 vpinsrb \$0x7,0x12345678,%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 04 25 78 56 34 12 vmovdqa 0x12345678,%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 04 25 78 56 34 12 vmovdqa %ymm8,0x12345678
[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 78 56 34 12 vpermilpd 0x12345678,%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 04 25 78 56 34 12 64 vroundpd \$0x64,0x12345678,%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 04 25 78 56 34 12 64 vextractf128 \$0x64,%ymm8,0x12345678
-[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 78 56 34 12 64 vperm2f128 \$0x64,0x12345678,%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 04 25 78 56 34 12 07 vroundpd \$0x7,0x12345678,%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 04 25 78 56 34 12 07 vextractf128 \$0x7,%ymm8,0x12345678
+[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 78 56 34 12 07 vperm2f128 \$0x7,0x12345678,%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 78 56 34 12 80 vblendvpd %ymm8,0x12345678,%ymm12,%ymm14
[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr 0x0\(%rbp\)
[ ]*[a-f0-9]+: c5 79 6f 45 00 vmovdqa 0x0\(%rbp\),%xmm8
[ ]*[a-f0-9]+: c5 7e e6 45 00 vcvtdq2pd 0x0\(%rbp\),%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 45 00 vcvtpd2psy 0x0\(%rbp\),%xmm8
[ ]*[a-f0-9]+: c5 39 e0 7d 00 vpavgb 0x0\(%rbp\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 45 00 64 vaeskeygenassist \$0x64,0x0\(%rbp\),%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 45 00 64 vpextrb \$0x64,%xmm8,0x0\(%rbp\)
+[ ]*[a-f0-9]+: c4 63 79 df 45 00 07 vaeskeygenassist \$0x7,0x0\(%rbp\),%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 45 00 07 vpextrb \$0x7,%xmm8,0x0\(%rbp\)
[ ]*[a-f0-9]+: c5 3b 2a 7d 00 vcvtsi2sdl 0x0\(%rbp\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a 75 00 80 vblendvps %xmm8,0x0\(%rbp\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 7d 00 64 vpinsrb \$0x64,0x0\(%rbp\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 7d 00 07 vpinsrb \$0x7,0x0\(%rbp\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 45 00 vmovdqa 0x0\(%rbp\),%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 45 00 vmovdqa %ymm8,0x0\(%rbp\)
[ ]*[a-f0-9]+: c4 62 3d 0d 7d 00 vpermilpd 0x0\(%rbp\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 45 00 64 vroundpd \$0x64,0x0\(%rbp\),%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 45 00 64 vextractf128 \$0x64,%ymm8,0x0\(%rbp\)
-[ ]*[a-f0-9]+: c4 63 3d 06 7d 00 64 vperm2f128 \$0x64,0x0\(%rbp\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 45 00 07 vroundpd \$0x7,0x0\(%rbp\),%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 45 00 07 vextractf128 \$0x7,%ymm8,0x0\(%rbp\)
+[ ]*[a-f0-9]+: c4 63 3d 06 7d 00 07 vperm2f128 \$0x7,0x0\(%rbp\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b 75 00 80 vblendvpd %ymm8,0x0\(%rbp\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c5 f8 ae 14 24 vldmxcsr \(%rsp\)
[ ]*[a-f0-9]+: c5 79 6f 04 24 vmovdqa \(%rsp\),%xmm8
[ ]*[a-f0-9]+: c5 7e e6 04 24 vcvtdq2pd \(%rsp\),%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 04 24 vcvtpd2psy \(%rsp\),%xmm8
[ ]*[a-f0-9]+: c5 39 e0 3c 24 vpavgb \(%rsp\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 04 24 64 vaeskeygenassist \$0x64,\(%rsp\),%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 04 24 64 vpextrb \$0x64,%xmm8,\(%rsp\)
+[ ]*[a-f0-9]+: c4 63 79 df 04 24 07 vaeskeygenassist \$0x7,\(%rsp\),%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 04 24 07 vpextrb \$0x7,%xmm8,\(%rsp\)
[ ]*[a-f0-9]+: c5 3b 2a 3c 24 vcvtsi2sdl \(%rsp\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a 34 24 80 vblendvps %xmm8,\(%rsp\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 3c 24 64 vpinsrb \$0x64,\(%rsp\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 3c 24 07 vpinsrb \$0x7,\(%rsp\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 04 24 vmovdqa \(%rsp\),%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 04 24 vmovdqa %ymm8,\(%rsp\)
[ ]*[a-f0-9]+: c4 62 3d 0d 3c 24 vpermilpd \(%rsp\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 04 24 64 vroundpd \$0x64,\(%rsp\),%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 04 24 64 vextractf128 \$0x64,%ymm8,\(%rsp\)
-[ ]*[a-f0-9]+: c4 63 3d 06 3c 24 64 vperm2f128 \$0x64,\(%rsp\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 04 24 07 vroundpd \$0x7,\(%rsp\),%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 04 24 07 vextractf128 \$0x7,%ymm8,\(%rsp\)
+[ ]*[a-f0-9]+: c4 63 3d 06 3c 24 07 vperm2f128 \$0x7,\(%rsp\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b 34 24 80 vblendvpd %ymm8,\(%rsp\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr 0x99\(%rbp\)
[ ]*[a-f0-9]+: c5 79 6f 85 99 00 00 00 vmovdqa 0x99\(%rbp\),%xmm8
[ ]*[a-f0-9]+: c5 7e e6 85 99 00 00 00 vcvtdq2pd 0x99\(%rbp\),%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 85 99 00 00 00 vcvtpd2psy 0x99\(%rbp\),%xmm8
[ ]*[a-f0-9]+: c5 39 e0 bd 99 00 00 00 vpavgb 0x99\(%rbp\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 85 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%rbp\),%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 85 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%rbp\)
+[ ]*[a-f0-9]+: c4 63 79 df 85 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%rbp\),%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 85 99 00 00 00 07 vpextrb \$0x7,%xmm8,0x99\(%rbp\)
[ ]*[a-f0-9]+: c5 3b 2a bd 99 00 00 00 vcvtsi2sdl 0x99\(%rbp\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a b5 99 00 00 00 80 vblendvps %xmm8,0x99\(%rbp\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 bd 99 00 00 00 64 vpinsrb \$0x64,0x99\(%rbp\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 bd 99 00 00 00 07 vpinsrb \$0x7,0x99\(%rbp\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 85 99 00 00 00 vmovdqa 0x99\(%rbp\),%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 85 99 00 00 00 vmovdqa %ymm8,0x99\(%rbp\)
[ ]*[a-f0-9]+: c4 62 3d 0d bd 99 00 00 00 vpermilpd 0x99\(%rbp\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 85 99 00 00 00 64 vroundpd \$0x64,0x99\(%rbp\),%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 85 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%rbp\)
-[ ]*[a-f0-9]+: c4 63 3d 06 bd 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%rbp\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 85 99 00 00 00 07 vroundpd \$0x7,0x99\(%rbp\),%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 85 99 00 00 00 07 vextractf128 \$0x7,%ymm8,0x99\(%rbp\)
+[ ]*[a-f0-9]+: c4 63 3d 06 bd 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%rbp\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b b5 99 00 00 00 80 vblendvpd %ymm8,0x99\(%rbp\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c4 c1 78 ae 97 99 00 00 00 vldmxcsr 0x99\(%r15\)
[ ]*[a-f0-9]+: c4 41 79 6f 87 99 00 00 00 vmovdqa 0x99\(%r15\),%xmm8
[ ]*[a-f0-9]+: c4 41 7e e6 87 99 00 00 00 vcvtdq2pd 0x99\(%r15\),%ymm8
[ ]*[a-f0-9]+: c4 41 7d 5a 87 99 00 00 00 vcvtpd2psy 0x99\(%r15\),%xmm8
[ ]*[a-f0-9]+: c4 41 39 e0 bf 99 00 00 00 vpavgb 0x99\(%r15\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 43 79 df 87 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%r15\),%xmm8
-[ ]*[a-f0-9]+: c4 43 79 14 87 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%r15\)
+[ ]*[a-f0-9]+: c4 43 79 df 87 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%r15\),%xmm8
+[ ]*[a-f0-9]+: c4 43 79 14 87 99 00 00 00 07 vpextrb \$0x7,%xmm8,0x99\(%r15\)
[ ]*[a-f0-9]+: c4 41 3b 2a bf 99 00 00 00 vcvtsi2sdl 0x99\(%r15\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 43 19 4a b7 99 00 00 00 80 vblendvps %xmm8,0x99\(%r15\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 43 39 20 bf 99 00 00 00 64 vpinsrb \$0x64,0x99\(%r15\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 43 39 20 bf 99 00 00 00 07 vpinsrb \$0x7,0x99\(%r15\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 41 7d 6f 87 99 00 00 00 vmovdqa 0x99\(%r15\),%ymm8
[ ]*[a-f0-9]+: c4 41 7d 7f 87 99 00 00 00 vmovdqa %ymm8,0x99\(%r15\)
[ ]*[a-f0-9]+: c4 42 3d 0d bf 99 00 00 00 vpermilpd 0x99\(%r15\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 43 7d 09 87 99 00 00 00 64 vroundpd \$0x64,0x99\(%r15\),%ymm8
-[ ]*[a-f0-9]+: c4 43 7d 19 87 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%r15\)
-[ ]*[a-f0-9]+: c4 43 3d 06 bf 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%r15\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 43 7d 09 87 99 00 00 00 07 vroundpd \$0x7,0x99\(%r15\),%ymm8
+[ ]*[a-f0-9]+: c4 43 7d 19 87 99 00 00 00 07 vextractf128 \$0x7,%ymm8,0x99\(%r15\)
+[ ]*[a-f0-9]+: c4 43 3d 06 bf 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%r15\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 43 1d 4b b7 99 00 00 00 80 vblendvpd %ymm8,0x99\(%r15\),%ymm12,%ymm14
-[ ]*[a-f0-9]+: c5 f8 ae 15 99 00 00 00 vldmxcsr 0x99\(%rip\) # 1a9c <_start\+0x1a9c>
-[ ]*[a-f0-9]+: c5 79 6f 05 99 00 00 00 vmovdqa 0x99\(%rip\),%xmm8 # 1aa4 <_start\+0x1aa4>
-[ ]*[a-f0-9]+: c5 79 7f 05 99 00 00 00 vmovdqa %xmm8,0x99\(%rip\) # 1aac <_start\+0x1aac>
-[ ]*[a-f0-9]+: c5 79 7e 05 99 00 00 00 vmovd %xmm8,0x99\(%rip\) # 1ab4 <_start\+0x1ab4>
-[ ]*[a-f0-9]+: c5 7b 2d 05 99 00 00 00 vcvtsd2si 0x99\(%rip\),%r8d # 1abc <_start\+0x1abc>
-[ ]*[a-f0-9]+: c5 7e e6 05 99 00 00 00 vcvtdq2pd 0x99\(%rip\),%ymm8 # 1ac4 <_start\+0x1ac4>
-[ ]*[a-f0-9]+: c5 7d 5a 05 99 00 00 00 vcvtpd2psy 0x99\(%rip\),%xmm8 # 1acc <_start\+0x1acc>
-[ ]*[a-f0-9]+: c5 39 e0 3d 99 00 00 00 vpavgb 0x99\(%rip\),%xmm8,%xmm15 # 1ad4 <_start\+0x1ad4>
-[ ]*[a-f0-9]+: c4 63 79 df 05 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%rip\),%xmm8 # 1ade <_start\+0x1ade>
-[ ]*[a-f0-9]+: c4 63 79 14 05 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%rip\) # 1ae8 <_start\+0x1ae8>
-[ ]*[a-f0-9]+: c5 3b 2a 3d 99 00 00 00 vcvtsi2sdl 0x99\(%rip\),%xmm8,%xmm15 # 1af0 <_start\+0x1af0>
-[ ]*[a-f0-9]+: c4 63 19 4a 35 99 00 00 00 80 vblendvps %xmm8,0x99\(%rip\),%xmm12,%xmm14 # 1afa <_start\+0x1afa>
-[ ]*[a-f0-9]+: c4 63 39 20 3d 99 00 00 00 64 vpinsrb \$0x64,0x99\(%rip\),%xmm8,%xmm15 # 1b04 <_start\+0x1b04>
-[ ]*[a-f0-9]+: c5 7d 6f 05 99 00 00 00 vmovdqa 0x99\(%rip\),%ymm8 # 1b0c <_start\+0x1b0c>
-[ ]*[a-f0-9]+: c5 7d 7f 05 99 00 00 00 vmovdqa %ymm8,0x99\(%rip\) # 1b14 <_start\+0x1b14>
-[ ]*[a-f0-9]+: c4 62 3d 0d 3d 99 00 00 00 vpermilpd 0x99\(%rip\),%ymm8,%ymm15 # 1b1d <_start\+0x1b1d>
-[ ]*[a-f0-9]+: c4 63 7d 09 05 99 00 00 00 64 vroundpd \$0x64,0x99\(%rip\),%ymm8 # 1b27 <_start\+0x1b27>
-[ ]*[a-f0-9]+: c4 63 7d 19 05 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%rip\) # 1b31 <_start\+0x1b31>
-[ ]*[a-f0-9]+: c4 63 3d 06 3d 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%rip\),%ymm8,%ymm15 # 1b3b <_start\+0x1b3b>
-[ ]*[a-f0-9]+: c4 63 1d 4b 35 99 00 00 00 80 vblendvpd %ymm8,0x99\(%rip\),%ymm12,%ymm14 # 1b45 <_start\+0x1b45>
+[ ]*[a-f0-9]+: c5 f8 ae 15 99 00 00 00 vldmxcsr 0x99\(%rip\) # 17bc <_start\+0x17bc>
+[ ]*[a-f0-9]+: c5 79 6f 05 99 00 00 00 vmovdqa 0x99\(%rip\),%xmm8 # 17c4 <_start\+0x17c4>
+[ ]*[a-f0-9]+: c5 79 7f 05 99 00 00 00 vmovdqa %xmm8,0x99\(%rip\) # 17cc <_start\+0x17cc>
+[ ]*[a-f0-9]+: c5 79 7e 05 99 00 00 00 vmovd %xmm8,0x99\(%rip\) # 17d4 <_start\+0x17d4>
+[ ]*[a-f0-9]+: c5 7b 2d 05 99 00 00 00 vcvtsd2si 0x99\(%rip\),%r8d # 17dc <_start\+0x17dc>
+[ ]*[a-f0-9]+: c5 7e e6 05 99 00 00 00 vcvtdq2pd 0x99\(%rip\),%ymm8 # 17e4 <_start\+0x17e4>
+[ ]*[a-f0-9]+: c5 7d 5a 05 99 00 00 00 vcvtpd2psy 0x99\(%rip\),%xmm8 # 17ec <_start\+0x17ec>
+[ ]*[a-f0-9]+: c5 39 e0 3d 99 00 00 00 vpavgb 0x99\(%rip\),%xmm8,%xmm15 # 17f4 <_start\+0x17f4>
+[ ]*[a-f0-9]+: c4 63 79 df 05 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%rip\),%xmm8 # 17fe <_start\+0x17fe>
+[ ]*[a-f0-9]+: c4 63 79 14 05 99 00 00 00 07 vpextrb \$0x7,%xmm8,0x99\(%rip\) # 1808 <_start\+0x1808>
+[ ]*[a-f0-9]+: c5 3b 2a 3d 99 00 00 00 vcvtsi2sdl 0x99\(%rip\),%xmm8,%xmm15 # 1810 <_start\+0x1810>
+[ ]*[a-f0-9]+: c4 63 19 4a 35 99 00 00 00 80 vblendvps %xmm8,0x99\(%rip\),%xmm12,%xmm14 # 181a <_start\+0x181a>
+[ ]*[a-f0-9]+: c4 63 39 20 3d 99 00 00 00 07 vpinsrb \$0x7,0x99\(%rip\),%xmm8,%xmm15 # 1824 <_start\+0x1824>
+[ ]*[a-f0-9]+: c5 7d 6f 05 99 00 00 00 vmovdqa 0x99\(%rip\),%ymm8 # 182c <_start\+0x182c>
+[ ]*[a-f0-9]+: c5 7d 7f 05 99 00 00 00 vmovdqa %ymm8,0x99\(%rip\) # 1834 <_start\+0x1834>
+[ ]*[a-f0-9]+: c4 62 3d 0d 3d 99 00 00 00 vpermilpd 0x99\(%rip\),%ymm8,%ymm15 # 183d <_start\+0x183d>
+[ ]*[a-f0-9]+: c4 63 7d 09 05 99 00 00 00 07 vroundpd \$0x7,0x99\(%rip\),%ymm8 # 1847 <_start\+0x1847>
+[ ]*[a-f0-9]+: c4 63 7d 19 05 99 00 00 00 07 vextractf128 \$0x7,%ymm8,0x99\(%rip\) # 1851 <_start\+0x1851>
+[ ]*[a-f0-9]+: c4 63 3d 06 3d 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%rip\),%ymm8,%ymm15 # 185b <_start\+0x185b>
+[ ]*[a-f0-9]+: c4 63 1d 4b 35 99 00 00 00 80 vblendvpd %ymm8,0x99\(%rip\),%ymm12,%ymm14 # 1865 <_start\+0x1865>
[ ]*[a-f0-9]+: c5 f8 ae 94 24 99 00 00 00 vldmxcsr 0x99\(%rsp\)
[ ]*[a-f0-9]+: c5 79 6f 84 24 99 00 00 00 vmovdqa 0x99\(%rsp\),%xmm8
[ ]*[a-f0-9]+: c5 79 7f 84 24 99 00 00 00 vmovdqa %xmm8,0x99\(%rsp\)
[ ]*[a-f0-9]+: c5 7e e6 84 24 99 00 00 00 vcvtdq2pd 0x99\(%rsp\),%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 84 24 99 00 00 00 vcvtpd2psy 0x99\(%rsp\),%xmm8
[ ]*[a-f0-9]+: c5 39 e0 bc 24 99 00 00 00 vpavgb 0x99\(%rsp\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 84 24 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%rsp\),%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 84 24 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%rsp\)
+[ ]*[a-f0-9]+: c4 63 79 df 84 24 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%rsp\),%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 84 24 99 00 00 00 07 vpextrb \$0x7,%xmm8,0x99\(%rsp\)
[ ]*[a-f0-9]+: c5 3b 2a bc 24 99 00 00 00 vcvtsi2sdl 0x99\(%rsp\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a b4 24 99 00 00 00 80 vblendvps %xmm8,0x99\(%rsp\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 bc 24 99 00 00 00 64 vpinsrb \$0x64,0x99\(%rsp\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 bc 24 99 00 00 00 07 vpinsrb \$0x7,0x99\(%rsp\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 84 24 99 00 00 00 vmovdqa 0x99\(%rsp\),%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 84 24 99 00 00 00 vmovdqa %ymm8,0x99\(%rsp\)
[ ]*[a-f0-9]+: c4 62 3d 0d bc 24 99 00 00 00 vpermilpd 0x99\(%rsp\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 84 24 99 00 00 00 64 vroundpd \$0x64,0x99\(%rsp\),%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 84 24 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%rsp\)
-[ ]*[a-f0-9]+: c4 63 3d 06 bc 24 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%rsp\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 84 24 99 00 00 00 07 vroundpd \$0x7,0x99\(%rsp\),%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 84 24 99 00 00 00 07 vextractf128 \$0x7,%ymm8,0x99\(%rsp\)
+[ ]*[a-f0-9]+: c4 63 3d 06 bc 24 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%rsp\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b b4 24 99 00 00 00 80 vblendvpd %ymm8,0x99\(%rsp\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c4 c1 78 ae 94 24 99 00 00 00 vldmxcsr 0x99\(%r12\)
[ ]*[a-f0-9]+: c4 41 79 6f 84 24 99 00 00 00 vmovdqa 0x99\(%r12\),%xmm8
[ ]*[a-f0-9]+: c4 41 7e e6 84 24 99 00 00 00 vcvtdq2pd 0x99\(%r12\),%ymm8
[ ]*[a-f0-9]+: c4 41 7d 5a 84 24 99 00 00 00 vcvtpd2psy 0x99\(%r12\),%xmm8
[ ]*[a-f0-9]+: c4 41 39 e0 bc 24 99 00 00 00 vpavgb 0x99\(%r12\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 43 79 df 84 24 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%r12\),%xmm8
-[ ]*[a-f0-9]+: c4 43 79 14 84 24 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%r12\)
+[ ]*[a-f0-9]+: c4 43 79 df 84 24 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%r12\),%xmm8
+[ ]*[a-f0-9]+: c4 43 79 14 84 24 99 00 00 00 07 vpextrb \$0x7,%xmm8,0x99\(%r12\)
[ ]*[a-f0-9]+: c4 41 3b 2a bc 24 99 00 00 00 vcvtsi2sdl 0x99\(%r12\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 43 19 4a b4 24 99 00 00 00 80 vblendvps %xmm8,0x99\(%r12\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 43 39 20 bc 24 99 00 00 00 64 vpinsrb \$0x64,0x99\(%r12\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 43 39 20 bc 24 99 00 00 00 07 vpinsrb \$0x7,0x99\(%r12\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 41 7d 6f 84 24 99 00 00 00 vmovdqa 0x99\(%r12\),%ymm8
[ ]*[a-f0-9]+: c4 41 7d 7f 84 24 99 00 00 00 vmovdqa %ymm8,0x99\(%r12\)
[ ]*[a-f0-9]+: c4 42 3d 0d bc 24 99 00 00 00 vpermilpd 0x99\(%r12\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 43 7d 09 84 24 99 00 00 00 64 vroundpd \$0x64,0x99\(%r12\),%ymm8
-[ ]*[a-f0-9]+: c4 43 7d 19 84 24 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%r12\)
-[ ]*[a-f0-9]+: c4 43 3d 06 bc 24 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%r12\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 43 7d 09 84 24 99 00 00 00 07 vroundpd \$0x7,0x99\(%r12\),%ymm8
+[ ]*[a-f0-9]+: c4 43 7d 19 84 24 99 00 00 00 07 vextractf128 \$0x7,%ymm8,0x99\(%r12\)
+[ ]*[a-f0-9]+: c4 43 3d 06 bc 24 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%r12\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 43 1d 4b b4 24 99 00 00 00 80 vblendvpd %ymm8,0x99\(%r12\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c5 f8 ae 14 25 67 ff ff ff vldmxcsr 0xffffffffffffff67
[ ]*[a-f0-9]+: c5 79 6f 04 25 67 ff ff ff vmovdqa 0xffffffffffffff67,%xmm8
[ ]*[a-f0-9]+: c5 7e e6 04 25 67 ff ff ff vcvtdq2pd 0xffffffffffffff67,%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 04 25 67 ff ff ff vcvtpd2psy 0xffffffffffffff67,%xmm8
[ ]*[a-f0-9]+: c5 39 e0 3c 25 67 ff ff ff vpavgb 0xffffffffffffff67,%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 04 25 67 ff ff ff 64 vaeskeygenassist \$0x64,0xffffffffffffff67,%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 04 25 67 ff ff ff 64 vpextrb \$0x64,%xmm8,0xffffffffffffff67
+[ ]*[a-f0-9]+: c4 63 79 df 04 25 67 ff ff ff 07 vaeskeygenassist \$0x7,0xffffffffffffff67,%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 04 25 67 ff ff ff 07 vpextrb \$0x7,%xmm8,0xffffffffffffff67
[ ]*[a-f0-9]+: c5 3b 2a 3c 25 67 ff ff ff vcvtsi2sdl 0xffffffffffffff67,%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a 34 25 67 ff ff ff 80 vblendvps %xmm8,0xffffffffffffff67,%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 3c 25 67 ff ff ff 64 vpinsrb \$0x64,0xffffffffffffff67,%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 3c 25 67 ff ff ff 07 vpinsrb \$0x7,0xffffffffffffff67,%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 04 25 67 ff ff ff vmovdqa 0xffffffffffffff67,%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 04 25 67 ff ff ff vmovdqa %ymm8,0xffffffffffffff67
[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 67 ff ff ff vpermilpd 0xffffffffffffff67,%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 04 25 67 ff ff ff 64 vroundpd \$0x64,0xffffffffffffff67,%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 04 25 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,0xffffffffffffff67
-[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 67 ff ff ff 64 vperm2f128 \$0x64,0xffffffffffffff67,%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 04 25 67 ff ff ff 07 vroundpd \$0x7,0xffffffffffffff67,%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 04 25 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,0xffffffffffffff67
+[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 67 ff ff ff 07 vperm2f128 \$0x7,0xffffffffffffff67,%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 67 ff ff ff 80 vblendvpd %ymm8,0xffffffffffffff67,%ymm12,%ymm14
[ ]*[a-f0-9]+: c5 f8 ae 14 65 67 ff ff ff vldmxcsr -0x99\(,%riz,2\)
[ ]*[a-f0-9]+: c5 79 6f 04 65 67 ff ff ff vmovdqa -0x99\(,%riz,2\),%xmm8
[ ]*[a-f0-9]+: c5 7e e6 04 65 67 ff ff ff vcvtdq2pd -0x99\(,%riz,2\),%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 04 65 67 ff ff ff vcvtpd2psy -0x99\(,%riz,2\),%xmm8
[ ]*[a-f0-9]+: c5 39 e0 3c 65 67 ff ff ff vpavgb -0x99\(,%riz,2\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 04 65 67 ff ff ff 64 vaeskeygenassist \$0x64,-0x99\(,%riz,2\),%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 04 65 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(,%riz,2\)
+[ ]*[a-f0-9]+: c4 63 79 df 04 65 67 ff ff ff 07 vaeskeygenassist \$0x7,-0x99\(,%riz,2\),%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 04 65 67 ff ff ff 07 vpextrb \$0x7,%xmm8,-0x99\(,%riz,2\)
[ ]*[a-f0-9]+: c5 3b 2a 3c 65 67 ff ff ff vcvtsi2sdl -0x99\(,%riz,2\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a 34 65 67 ff ff ff 80 vblendvps %xmm8,-0x99\(,%riz,2\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 3c 65 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(,%riz,2\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 3c 65 67 ff ff ff 07 vpinsrb \$0x7,-0x99\(,%riz,2\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 04 65 67 ff ff ff vmovdqa -0x99\(,%riz,2\),%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 04 65 67 ff ff ff vmovdqa %ymm8,-0x99\(,%riz,2\)
[ ]*[a-f0-9]+: c4 62 3d 0d 3c 65 67 ff ff ff vpermilpd -0x99\(,%riz,2\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 04 65 67 ff ff ff 64 vroundpd \$0x64,-0x99\(,%riz,2\),%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 04 65 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(,%riz,2\)
-[ ]*[a-f0-9]+: c4 63 3d 06 3c 65 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(,%riz,2\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 04 65 67 ff ff ff 07 vroundpd \$0x7,-0x99\(,%riz,2\),%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 04 65 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,-0x99\(,%riz,2\)
+[ ]*[a-f0-9]+: c4 63 3d 06 3c 65 67 ff ff ff 07 vperm2f128 \$0x7,-0x99\(,%riz,2\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b 34 65 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(,%riz,2\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c5 f8 ae 94 23 67 ff ff ff vldmxcsr -0x99\(%rbx,%riz,1\)
[ ]*[a-f0-9]+: c5 79 6f 84 23 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,1\),%xmm8
[ ]*[a-f0-9]+: c5 7e e6 84 23 67 ff ff ff vcvtdq2pd -0x99\(%rbx,%riz,1\),%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 84 23 67 ff ff ff vcvtpd2psy -0x99\(%rbx,%riz,1\),%xmm8
[ ]*[a-f0-9]+: c5 39 e0 bc 23 67 ff ff ff vpavgb -0x99\(%rbx,%riz,1\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 84 23 67 ff ff ff 64 vaeskeygenassist \$0x64,-0x99\(%rbx,%riz,1\),%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 84 23 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rbx,%riz,1\)
+[ ]*[a-f0-9]+: c4 63 79 df 84 23 67 ff ff ff 07 vaeskeygenassist \$0x7,-0x99\(%rbx,%riz,1\),%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 84 23 67 ff ff ff 07 vpextrb \$0x7,%xmm8,-0x99\(%rbx,%riz,1\)
[ ]*[a-f0-9]+: c5 3b 2a bc 23 67 ff ff ff vcvtsi2sdl -0x99\(%rbx,%riz,1\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a b4 23 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rbx,%riz,1\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 bc 23 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rbx,%riz,1\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 bc 23 67 ff ff ff 07 vpinsrb \$0x7,-0x99\(%rbx,%riz,1\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 84 23 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,1\),%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 84 23 67 ff ff ff vmovdqa %ymm8,-0x99\(%rbx,%riz,1\)
[ ]*[a-f0-9]+: c4 62 3d 0d bc 23 67 ff ff ff vpermilpd -0x99\(%rbx,%riz,1\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 84 23 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rbx,%riz,1\),%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 84 23 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rbx,%riz,1\)
-[ ]*[a-f0-9]+: c4 63 3d 06 bc 23 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rbx,%riz,1\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 84 23 67 ff ff ff 07 vroundpd \$0x7,-0x99\(%rbx,%riz,1\),%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 84 23 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,-0x99\(%rbx,%riz,1\)
+[ ]*[a-f0-9]+: c4 63 3d 06 bc 23 67 ff ff ff 07 vperm2f128 \$0x7,-0x99\(%rbx,%riz,1\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b b4 23 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rbx,%riz,1\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c5 f8 ae 94 63 67 ff ff ff vldmxcsr -0x99\(%rbx,%riz,2\)
[ ]*[a-f0-9]+: c5 79 6f 84 63 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,2\),%xmm8
[ ]*[a-f0-9]+: c5 7e e6 84 63 67 ff ff ff vcvtdq2pd -0x99\(%rbx,%riz,2\),%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 84 63 67 ff ff ff vcvtpd2psy -0x99\(%rbx,%riz,2\),%xmm8
[ ]*[a-f0-9]+: c5 39 e0 bc 63 67 ff ff ff vpavgb -0x99\(%rbx,%riz,2\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 84 63 67 ff ff ff 64 vaeskeygenassist \$0x64,-0x99\(%rbx,%riz,2\),%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 84 63 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rbx,%riz,2\)
+[ ]*[a-f0-9]+: c4 63 79 df 84 63 67 ff ff ff 07 vaeskeygenassist \$0x7,-0x99\(%rbx,%riz,2\),%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 84 63 67 ff ff ff 07 vpextrb \$0x7,%xmm8,-0x99\(%rbx,%riz,2\)
[ ]*[a-f0-9]+: c5 3b 2a bc 63 67 ff ff ff vcvtsi2sdl -0x99\(%rbx,%riz,2\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a b4 63 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rbx,%riz,2\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 bc 63 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rbx,%riz,2\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 bc 63 67 ff ff ff 07 vpinsrb \$0x7,-0x99\(%rbx,%riz,2\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 84 63 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,2\),%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 84 63 67 ff ff ff vmovdqa %ymm8,-0x99\(%rbx,%riz,2\)
[ ]*[a-f0-9]+: c4 62 3d 0d bc 63 67 ff ff ff vpermilpd -0x99\(%rbx,%riz,2\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 84 63 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rbx,%riz,2\),%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 84 63 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rbx,%riz,2\)
-[ ]*[a-f0-9]+: c4 63 3d 06 bc 63 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rbx,%riz,2\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 84 63 67 ff ff ff 07 vroundpd \$0x7,-0x99\(%rbx,%riz,2\),%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 84 63 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,-0x99\(%rbx,%riz,2\)
+[ ]*[a-f0-9]+: c4 63 3d 06 bc 63 67 ff ff ff 07 vperm2f128 \$0x7,-0x99\(%rbx,%riz,2\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b b4 63 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rbx,%riz,2\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c4 81 78 ae 94 bc 67 ff ff ff vldmxcsr -0x99\(%r12,%r15,4\)
[ ]*[a-f0-9]+: c4 01 79 6f 84 bc 67 ff ff ff vmovdqa -0x99\(%r12,%r15,4\),%xmm8
[ ]*[a-f0-9]+: c4 01 7e e6 84 bc 67 ff ff ff vcvtdq2pd -0x99\(%r12,%r15,4\),%ymm8
[ ]*[a-f0-9]+: c4 01 7d 5a 84 bc 67 ff ff ff vcvtpd2psy -0x99\(%r12,%r15,4\),%xmm8
[ ]*[a-f0-9]+: c4 01 39 e0 bc bc 67 ff ff ff vpavgb -0x99\(%r12,%r15,4\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 03 79 df 84 bc 67 ff ff ff 64 vaeskeygenassist \$0x64,-0x99\(%r12,%r15,4\),%xmm8
-[ ]*[a-f0-9]+: c4 03 79 14 84 bc 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%r12,%r15,4\)
+[ ]*[a-f0-9]+: c4 03 79 df 84 bc 67 ff ff ff 07 vaeskeygenassist \$0x7,-0x99\(%r12,%r15,4\),%xmm8
+[ ]*[a-f0-9]+: c4 03 79 14 84 bc 67 ff ff ff 07 vpextrb \$0x7,%xmm8,-0x99\(%r12,%r15,4\)
[ ]*[a-f0-9]+: c4 01 3b 2a bc bc 67 ff ff ff vcvtsi2sdl -0x99\(%r12,%r15,4\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 03 19 4a b4 bc 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%r12,%r15,4\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 03 39 20 bc bc 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%r12,%r15,4\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 03 39 20 bc bc 67 ff ff ff 07 vpinsrb \$0x7,-0x99\(%r12,%r15,4\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 01 7d 6f 84 bc 67 ff ff ff vmovdqa -0x99\(%r12,%r15,4\),%ymm8
[ ]*[a-f0-9]+: c4 01 7d 7f 84 bc 67 ff ff ff vmovdqa %ymm8,-0x99\(%r12,%r15,4\)
[ ]*[a-f0-9]+: c4 02 3d 0d bc bc 67 ff ff ff vpermilpd -0x99\(%r12,%r15,4\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 03 7d 09 84 bc 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%r12,%r15,4\),%ymm8
-[ ]*[a-f0-9]+: c4 03 7d 19 84 bc 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%r12,%r15,4\)
-[ ]*[a-f0-9]+: c4 03 3d 06 bc bc 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%r12,%r15,4\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 03 7d 09 84 bc 67 ff ff ff 07 vroundpd \$0x7,-0x99\(%r12,%r15,4\),%ymm8
+[ ]*[a-f0-9]+: c4 03 7d 19 84 bc 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,-0x99\(%r12,%r15,4\)
+[ ]*[a-f0-9]+: c4 03 3d 06 bc bc 67 ff ff ff 07 vperm2f128 \$0x7,-0x99\(%r12,%r15,4\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 03 1d 4b b4 bc 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%r12,%r15,4\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c4 81 78 ae 94 f8 67 ff ff ff vldmxcsr -0x99\(%r8,%r15,8\)
[ ]*[a-f0-9]+: c4 01 79 6f 84 f8 67 ff ff ff vmovdqa -0x99\(%r8,%r15,8\),%xmm8
[ ]*[a-f0-9]+: c4 01 7e e6 84 f8 67 ff ff ff vcvtdq2pd -0x99\(%r8,%r15,8\),%ymm8
[ ]*[a-f0-9]+: c4 01 7d 5a 84 f8 67 ff ff ff vcvtpd2psy -0x99\(%r8,%r15,8\),%xmm8
[ ]*[a-f0-9]+: c4 01 39 e0 bc f8 67 ff ff ff vpavgb -0x99\(%r8,%r15,8\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 03 79 df 84 f8 67 ff ff ff 64 vaeskeygenassist \$0x64,-0x99\(%r8,%r15,8\),%xmm8
-[ ]*[a-f0-9]+: c4 03 79 14 84 f8 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%r8,%r15,8\)
+[ ]*[a-f0-9]+: c4 03 79 df 84 f8 67 ff ff ff 07 vaeskeygenassist \$0x7,-0x99\(%r8,%r15,8\),%xmm8
+[ ]*[a-f0-9]+: c4 03 79 14 84 f8 67 ff ff ff 07 vpextrb \$0x7,%xmm8,-0x99\(%r8,%r15,8\)
[ ]*[a-f0-9]+: c4 01 3b 2a bc f8 67 ff ff ff vcvtsi2sdl -0x99\(%r8,%r15,8\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 03 19 4a b4 f8 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%r8,%r15,8\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 03 39 20 bc f8 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%r8,%r15,8\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 03 39 20 bc f8 67 ff ff ff 07 vpinsrb \$0x7,-0x99\(%r8,%r15,8\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 01 7d 6f 84 f8 67 ff ff ff vmovdqa -0x99\(%r8,%r15,8\),%ymm8
[ ]*[a-f0-9]+: c4 01 7d 7f 84 f8 67 ff ff ff vmovdqa %ymm8,-0x99\(%r8,%r15,8\)
[ ]*[a-f0-9]+: c4 02 3d 0d bc f8 67 ff ff ff vpermilpd -0x99\(%r8,%r15,8\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 03 7d 09 84 f8 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%r8,%r15,8\),%ymm8
-[ ]*[a-f0-9]+: c4 03 7d 19 84 f8 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%r8,%r15,8\)
-[ ]*[a-f0-9]+: c4 03 3d 06 bc f8 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%r8,%r15,8\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 03 7d 09 84 f8 67 ff ff ff 07 vroundpd \$0x7,-0x99\(%r8,%r15,8\),%ymm8
+[ ]*[a-f0-9]+: c4 03 7d 19 84 f8 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,-0x99\(%r8,%r15,8\)
+[ ]*[a-f0-9]+: c4 03 3d 06 bc f8 67 ff ff ff 07 vperm2f128 \$0x7,-0x99\(%r8,%r15,8\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 03 1d 4b b4 f8 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%r8,%r15,8\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c4 a1 78 ae 94 ad 67 ff ff ff vldmxcsr -0x99\(%rbp,%r13,4\)
[ ]*[a-f0-9]+: c4 21 79 6f 84 ad 67 ff ff ff vmovdqa -0x99\(%rbp,%r13,4\),%xmm8
[ ]*[a-f0-9]+: c4 21 7e e6 84 ad 67 ff ff ff vcvtdq2pd -0x99\(%rbp,%r13,4\),%ymm8
[ ]*[a-f0-9]+: c4 21 7d 5a 84 ad 67 ff ff ff vcvtpd2psy -0x99\(%rbp,%r13,4\),%xmm8
[ ]*[a-f0-9]+: c4 21 39 e0 bc ad 67 ff ff ff vpavgb -0x99\(%rbp,%r13,4\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 23 79 df 84 ad 67 ff ff ff 64 vaeskeygenassist \$0x64,-0x99\(%rbp,%r13,4\),%xmm8
-[ ]*[a-f0-9]+: c4 23 79 14 84 ad 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rbp,%r13,4\)
+[ ]*[a-f0-9]+: c4 23 79 df 84 ad 67 ff ff ff 07 vaeskeygenassist \$0x7,-0x99\(%rbp,%r13,4\),%xmm8
+[ ]*[a-f0-9]+: c4 23 79 14 84 ad 67 ff ff ff 07 vpextrb \$0x7,%xmm8,-0x99\(%rbp,%r13,4\)
[ ]*[a-f0-9]+: c4 21 3b 2a bc ad 67 ff ff ff vcvtsi2sdl -0x99\(%rbp,%r13,4\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 23 19 4a b4 ad 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rbp,%r13,4\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 23 39 20 bc ad 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rbp,%r13,4\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 23 39 20 bc ad 67 ff ff ff 07 vpinsrb \$0x7,-0x99\(%rbp,%r13,4\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 21 7d 6f 84 ad 67 ff ff ff vmovdqa -0x99\(%rbp,%r13,4\),%ymm8
[ ]*[a-f0-9]+: c4 21 7d 7f 84 ad 67 ff ff ff vmovdqa %ymm8,-0x99\(%rbp,%r13,4\)
[ ]*[a-f0-9]+: c4 22 3d 0d bc ad 67 ff ff ff vpermilpd -0x99\(%rbp,%r13,4\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 23 7d 09 84 ad 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rbp,%r13,4\),%ymm8
-[ ]*[a-f0-9]+: c4 23 7d 19 84 ad 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rbp,%r13,4\)
-[ ]*[a-f0-9]+: c4 23 3d 06 bc ad 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rbp,%r13,4\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 23 7d 09 84 ad 67 ff ff ff 07 vroundpd \$0x7,-0x99\(%rbp,%r13,4\),%ymm8
+[ ]*[a-f0-9]+: c4 23 7d 19 84 ad 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,-0x99\(%rbp,%r13,4\)
+[ ]*[a-f0-9]+: c4 23 3d 06 bc ad 67 ff ff ff 07 vperm2f128 \$0x7,-0x99\(%rbp,%r13,4\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 23 1d 4b b4 ad 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rbp,%r13,4\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c4 a1 78 ae 94 24 67 ff ff ff vldmxcsr -0x99\(%rsp,%r12,1\)
[ ]*[a-f0-9]+: c4 21 79 6f 84 24 67 ff ff ff vmovdqa -0x99\(%rsp,%r12,1\),%xmm8
[ ]*[a-f0-9]+: c4 21 7e e6 84 24 67 ff ff ff vcvtdq2pd -0x99\(%rsp,%r12,1\),%ymm8
[ ]*[a-f0-9]+: c4 21 7d 5a 84 24 67 ff ff ff vcvtpd2psy -0x99\(%rsp,%r12,1\),%xmm8
[ ]*[a-f0-9]+: c4 21 39 e0 bc 24 67 ff ff ff vpavgb -0x99\(%rsp,%r12,1\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 23 79 df 84 24 67 ff ff ff 64 vaeskeygenassist \$0x64,-0x99\(%rsp,%r12,1\),%xmm8
-[ ]*[a-f0-9]+: c4 23 79 14 84 24 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rsp,%r12,1\)
+[ ]*[a-f0-9]+: c4 23 79 df 84 24 67 ff ff ff 07 vaeskeygenassist \$0x7,-0x99\(%rsp,%r12,1\),%xmm8
+[ ]*[a-f0-9]+: c4 23 79 14 84 24 67 ff ff ff 07 vpextrb \$0x7,%xmm8,-0x99\(%rsp,%r12,1\)
[ ]*[a-f0-9]+: c4 21 3b 2a bc 24 67 ff ff ff vcvtsi2sdl -0x99\(%rsp,%r12,1\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 23 19 4a b4 24 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rsp,%r12,1\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 23 39 20 bc 24 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rsp,%r12,1\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 23 39 20 bc 24 67 ff ff ff 07 vpinsrb \$0x7,-0x99\(%rsp,%r12,1\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 21 7d 6f 84 24 67 ff ff ff vmovdqa -0x99\(%rsp,%r12,1\),%ymm8
[ ]*[a-f0-9]+: c4 21 7d 7f 84 24 67 ff ff ff vmovdqa %ymm8,-0x99\(%rsp,%r12,1\)
[ ]*[a-f0-9]+: c4 22 3d 0d bc 24 67 ff ff ff vpermilpd -0x99\(%rsp,%r12,1\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 23 7d 09 84 24 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rsp,%r12,1\),%ymm8
-[ ]*[a-f0-9]+: c4 23 7d 19 84 24 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rsp,%r12,1\)
-[ ]*[a-f0-9]+: c4 23 3d 06 bc 24 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rsp,%r12,1\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 23 7d 09 84 24 67 ff ff ff 07 vroundpd \$0x7,-0x99\(%rsp,%r12,1\),%ymm8
+[ ]*[a-f0-9]+: c4 23 7d 19 84 24 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,-0x99\(%rsp,%r12,1\)
+[ ]*[a-f0-9]+: c4 23 3d 06 bc 24 67 ff ff ff 07 vperm2f128 \$0x7,-0x99\(%rsp,%r12,1\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 23 1d 4b b4 24 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rsp,%r12,1\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c4 41 79 50 c0 vmovmskpd %xmm8,%r8d
-[ ]*[a-f0-9]+: c4 c1 01 72 f0 64 vpslld \$0x64,%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 c1 01 72 f0 07 vpslld \$0x7,%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 41 7c 50 c0 vmovmskps %ymm8,%r8d
[ ]*[a-f0-9]+: c4 41 79 6f f8 vmovdqa %xmm8,%xmm15
[ ]*[a-f0-9]+: c4 41 79 7e c0 vmovd %xmm8,%r8d
[ ]*[a-f0-9]+: c4 41 7b 2d c0 vcvtsd2si %xmm8,%r8d
[ ]*[a-f0-9]+: c4 41 7e e6 c0 vcvtdq2pd %xmm8,%ymm8
[ ]*[a-f0-9]+: c4 41 7d 5a c0 vcvtpd2ps %ymm8,%xmm8
-[ ]*[a-f0-9]+: c4 43 79 df f8 64 vaeskeygenassist \$0x64,%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 43 79 14 c0 64 vpextrb \$0x64,%xmm8,%r8d
+[ ]*[a-f0-9]+: c4 43 79 df f8 07 vaeskeygenassist \$0x7,%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 43 79 14 c0 07 vpextrb \$0x7,%xmm8,%r8d
[ ]*[a-f0-9]+: c4 41 3b 2a f8 vcvtsi2sd %r8d,%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 43 19 4a f0 80 vblendvps %xmm8,%xmm8,%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 43 39 20 f8 64 vpinsrb \$0x64,%r8d,%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 43 39 20 f8 07 vpinsrb \$0x7,%r8d,%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 41 7d 6f f8 vmovdqa %ymm8,%ymm15
[ ]*[a-f0-9]+: c4 42 05 0d e0 vpermilpd %ymm8,%ymm15,%ymm12
-[ ]*[a-f0-9]+: c4 43 7d 09 f8 64 vroundpd \$0x64,%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 43 7d 19 c0 64 vextractf128 \$0x64,%ymm8,%xmm8
-[ ]*[a-f0-9]+: c4 43 05 06 e0 64 vperm2f128 \$0x64,%ymm8,%ymm15,%ymm12
+[ ]*[a-f0-9]+: c4 43 7d 09 f8 07 vroundpd \$0x7,%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 43 7d 19 c0 07 vextractf128 \$0x7,%ymm8,%xmm8
+[ ]*[a-f0-9]+: c4 43 05 06 e0 07 vperm2f128 \$0x7,%ymm8,%ymm15,%ymm12
[ ]*[a-f0-9]+: c4 43 1d 4b f7 80 vblendvpd %ymm8,%ymm15,%ymm12,%ymm14
-[ ]*[a-f0-9]+: c4 43 3d 18 f8 64 vinsertf128 \$0x64,%xmm8,%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 43 3d 18 f8 07 vinsertf128 \$0x7,%xmm8,%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 61 fb 2d 01 vcvtsd2si \(%rcx\),%r8
[ ]*[a-f0-9]+: c4 43 79 17 c0 0a vextractps \$0xa,%xmm8,%r8d
[ ]*[a-f0-9]+: c4 61 fa 2d 01 vcvtss2si \(%rcx\),%r8
-[ ]*[a-f0-9]+: c4 41 01 c4 c0 64 vpinsrw \$0x64,%r8d,%xmm15,%xmm8
+[ ]*[a-f0-9]+: c4 41 01 c4 c0 07 vpinsrw \$0x7,%r8d,%xmm15,%xmm8
[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%rcx\)
[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%rcx\)
[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%rcx\)
[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps %ymm4,%ymm6,\(%rcx\)
[ ]*[a-f0-9]+: c4 e2 5d 2c 31 vmaskmovps \(%rcx\),%ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 4d 2e 21 vmaskmovps %ymm4,%ymm6,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 7d 05 d6 64 vpermilpd \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd \$0x64,\(%rcx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 05 31 64 vpermilpd \$0x64,\(%rcx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 04 d6 64 vpermilps \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps \$0x64,\(%rcx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 04 31 64 vpermilps \$0x64,\(%rcx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 09 d6 64 vroundpd \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd \$0x64,\(%rcx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 09 31 64 vroundpd \$0x64,\(%rcx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 08 d6 64 vroundps \$0x64,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps \$0x64,\(%rcx\),%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 08 31 64 vroundps \$0x64,\(%rcx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 05 d6 07 vpermilpd \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 05 31 07 vpermilpd \$0x7,\(%rcx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 05 31 07 vpermilpd \$0x7,\(%rcx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 04 d6 07 vpermilps \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 04 31 07 vpermilps \$0x7,\(%rcx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 04 31 07 vpermilps \$0x7,\(%rcx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 09 d6 07 vroundpd \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 09 31 07 vroundpd \$0x7,\(%rcx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 09 31 07 vroundpd \$0x7,\(%rcx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 08 d6 07 vroundps \$0x7,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 7d 08 31 07 vroundps \$0x7,\(%rcx\),%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 08 31 07 vroundps \$0x7,\(%rcx\),%ymm6
[ ]*[a-f0-9]+: c5 cd 58 d4 vaddpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd \(%rcx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd 58 11 vaddpd \(%rcx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 fd 5a 21 vcvtpd2psy \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c5 fd e6 e4 vcvttpd2dq %ymm4,%xmm4
[ ]*[a-f0-9]+: c5 fd e6 21 vcvttpd2dqy \(%rcx\),%xmm4
-[ ]*[a-f0-9]+: c5 fc 5b e4 vcvtdq2ps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 5b f4 vcvtdq2ps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fc 5b 21 vcvtdq2ps \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 5b e4 vcvtps2dq %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 5b f4 vcvtps2dq %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fd 5b 21 vcvtps2dq \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 5b e4 vcvttps2dq %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 5b f4 vcvttps2dq %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fe 5b 21 vcvttps2dq \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 28 e4 vmovapd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fd 28 21 vmovapd \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 28 e4 vmovaps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fc 28 21 vmovaps \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 6f e4 vmovdqa %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fd 6f 21 vmovdqa \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 6f e4 vmovdqu %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fe 6f 21 vmovdqu \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 ff 12 e4 vmovddup %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 ff 12 f4 vmovddup %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 ff 12 21 vmovddup \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 16 e4 vmovshdup %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 16 f4 vmovshdup %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fe 16 21 vmovshdup \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fe 12 e4 vmovsldup %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fe 12 f4 vmovsldup %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fe 12 21 vmovsldup \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 10 e4 vmovupd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fd 10 21 vmovupd \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 10 e4 vmovups %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 10 21 vmovups \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fc 10 21 vmovups \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c4 e2 7d 17 e4 vptest %ymm4,%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 17 f4 vptest %ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c4 e2 7d 17 21 vptest \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 53 e4 vrcpps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 53 f4 vrcpps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fc 53 21 vrcpps \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 52 e4 vrsqrtps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 52 f4 vrsqrtps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fc 52 21 vrsqrtps \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fd 51 e4 vsqrtpd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fd 51 f4 vsqrtpd %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fd 51 21 vsqrtpd \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c5 fc 51 e4 vsqrtps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c5 fc 51 f4 vsqrtps %ymm4,%ymm6
[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 fc 51 21 vsqrtps \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c4 e2 7d 0f e4 vtestpd %ymm4,%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0f f4 vtestpd %ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c4 e2 7d 0f 21 vtestpd \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c4 e2 7d 0e e4 vtestps %ymm4,%ymm4
+[ ]*[a-f0-9]+: c4 e2 7d 0e f4 vtestps %ymm4,%ymm6
[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c4 e2 7d 0e 21 vtestps \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 ff f0 21 vlddqu \(%rcx\),%ymm4
-[ ]*[a-f0-9]+: c4 e3 4d 0d d4 64 vblendpd \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0d 11 64 vblendpd \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0c d4 64 vblendps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 0c 11 64 vblendps \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c2 d4 64 vcmppd \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c2 11 64 vcmppd \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c2 d4 64 vcmpps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c2 11 64 vcmpps \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 40 d4 64 vdpps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 40 11 64 vdpps \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 06 d4 64 vperm2f128 \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c4 e3 4d 06 11 64 vperm2f128 \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c6 d4 64 vshufpd \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cd c6 11 64 vshufpd \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c6 d4 64 vshufps \$0x64,%ymm4,%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps \$0x64,\(%rcx\),%ymm6,%ymm2
-[ ]*[a-f0-9]+: c5 cc c6 11 64 vshufps \$0x64,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0d d4 07 vblendpd \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0d 11 07 vblendpd \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0d 11 07 vblendpd \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0c d4 07 vblendps \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0c 11 07 vblendps \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 0c 11 07 vblendps \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd \(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd \(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps \(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps \(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 40 d4 07 vdpps \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 40 11 07 vdpps \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 40 11 07 vdpps \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 06 d4 07 vperm2f128 \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 06 11 07 vperm2f128 \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 4d 06 11 07 vperm2f128 \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c6 d4 07 vshufpd \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%rcx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%rcx\),%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%rcx\),%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps %ymm4,%ymm6,%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps %ymm4,\(%rcx\),%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4a 39 40 vblendvps %ymm4,\(%rcx\),%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 69 fc 20 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 69 39 20 vfmaddpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 69 39 20 vfmaddpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 68 fc 20 vfmaddps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 68 39 20 vfmaddps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 68 39 20 vfmaddps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5d fc 20 vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5d 39 20 vfmaddsubpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5d 39 20 vfmaddsubpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5c fc 20 vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5c 39 20 vfmaddsubps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5c 39 20 vfmaddsubps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5f fc 20 vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5f 39 20 vfmsubaddpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5f 39 20 vfmsubaddpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5e fc 20 vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5e 39 20 vfmsubaddps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 5e 39 20 vfmsubaddps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6d fc 20 vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6d 39 20 vfmsubpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6d 39 20 vfmsubpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6c fc 20 vfmsubps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6c 39 20 vfmsubps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 6c 39 20 vfmsubps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 79 fc 20 vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 79 39 20 vfnmaddpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 79 39 20 vfnmaddpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 78 fc 20 vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 78 39 20 vfnmaddps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 78 39 20 vfnmaddps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7d fc 20 vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7d 39 20 vfnmsubpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7d 39 20 vfnmsubpd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7c fc 20 vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7c 39 20 vfnmsubps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 cd 7c 39 20 vfnmsubps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 62 vpermilmo2pd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 62 vpermilmo2pd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 63 vpermilmz2pd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 63 vpermilmz2pd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 60 vpermiltd2pd %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 60 vpermiltd2pd \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 62 vpermilmo2ps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 62 vpermilmo2ps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 63 vpermilmz2ps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 63 vpermilmz2ps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 60 vpermiltd2ps %ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 60 vpermiltd2ps \(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 fc 6a vpermil2pd \$0xa,%ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd \$0xa,\(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 49 39 6a vpermil2pd \$0xa,\(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 fc 6a vpermil2ps \$0xa,%ymm4,%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps \$0xa,\(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 ed 48 39 6a vpermil2ps \$0xa,\(%rcx\),%ymm6,%ymm2,%ymm7
-[ ]*[a-f0-9]+: c4 e3 5d 18 f4 64 vinsertf128 \$0x64,%xmm4,%ymm4,%ymm6
-[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 \$0x64,\(%rcx\),%ymm4,%ymm6
-[ ]*[a-f0-9]+: c4 e3 5d 18 31 64 vinsertf128 \$0x64,\(%rcx\),%ymm4,%ymm6
-[ ]*[a-f0-9]+: c4 e3 7d 19 e4 64 vextractf128 \$0x64,%ymm4,%xmm4
-[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 \$0x64,%ymm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 7d 19 21 64 vextractf128 \$0x64,%ymm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 5d 18 f4 07 vinsertf128 \$0x7,%xmm4,%ymm4,%ymm6
+[ ]*[a-f0-9]+: c4 e3 5d 18 31 07 vinsertf128 \$0x7,\(%rcx\),%ymm4,%ymm6
+[ ]*[a-f0-9]+: c4 e3 5d 18 31 07 vinsertf128 \$0x7,\(%rcx\),%ymm4,%ymm6
+[ ]*[a-f0-9]+: c4 e3 7d 19 e4 07 vextractf128 \$0x7,%ymm4,%xmm4
+[ ]*[a-f0-9]+: c4 e3 7d 19 21 07 vextractf128 \$0x7,%ymm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 7d 19 21 07 vextractf128 \$0x7,%ymm4,\(%rcx\)
[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c4 e2 7d 1a 21 vbroadcastf128 \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 df f4 64 vaeskeygenassist \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 df 31 64 vaeskeygenassist \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 df 31 64 vaeskeygenassist \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 05 f4 64 vpermilpd \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 05 31 64 vpermilpd \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 04 f4 64 vpermilps \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 04 31 64 vpermilps \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps \$0x64,\(%rcx\),%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps \$0x64,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 df 31 07 vaeskeygenassist \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 df 31 07 vaeskeygenassist \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 61 f4 07 vpcmpestri \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 61 31 07 vpcmpestri \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 61 31 07 vpcmpestri \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 60 f4 07 vpcmpestrm \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 60 31 07 vpcmpestrm \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 60 31 07 vpcmpestrm \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 63 f4 07 vpcmpistri \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 63 31 07 vpcmpistri \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 63 31 07 vpcmpistri \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 62 f4 07 vpcmpistrm \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 62 31 07 vpcmpistrm \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 62 31 07 vpcmpistrm \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 05 f4 07 vpermilpd \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 05 31 07 vpermilpd \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 05 31 07 vpermilpd \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 04 f4 07 vpermilps \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 04 31 07 vpermilps \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 04 31 07 vpermilps \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c5 f9 70 f4 07 vpshufd \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 f9 70 31 07 vpshufd \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c5 f9 70 31 07 vpshufd \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c5 fa 70 f4 07 vpshufhw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 fa 70 31 07 vpshufhw \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c5 fa 70 31 07 vpshufhw \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c5 fb 70 f4 07 vpshuflw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 fb 70 31 07 vpshuflw \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c5 fb 70 31 07 vpshuflw \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 09 f4 07 vroundpd \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 09 31 07 vroundpd \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 09 31 07 vroundpd \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 08 f4 07 vroundps \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 08 31 07 vroundps \$0x7,\(%rcx\),%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 08 31 07 vroundps \$0x7,\(%rcx\),%xmm6
[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps %xmm4,%xmm6,\(%rcx\)
[ ]*[a-f0-9]+: c4 e2 49 2e 21 vmaskmovps %xmm4,%xmm6,\(%rcx\)
[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd %xmm4,%xmm6,\(%rcx\)
[ ]*[a-f0-9]+: c4 e2 49 2f 21 vmaskmovpd %xmm4,%xmm6,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 49 0d d4 64 vblendpd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0d 11 64 vblendpd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0c d4 64 vblendps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0c 11 64 vblendps \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c2 d4 64 vcmppd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c2 11 64 vcmppd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c2 d4 64 vcmpps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c2 11 64 vcmpps \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 41 d4 64 vdppd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 41 11 64 vdppd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 40 d4 64 vdpps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 40 11 64 vdpps \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 42 d4 64 vmpsadbw \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 42 11 64 vmpsadbw \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0f d4 64 vpalignr \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0f 11 64 vpalignr \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0e d4 64 vpblendw \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0e 11 64 vpblendw \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c6 d4 64 vshufpd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 c6 11 64 vshufpd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c6 d4 64 vshufps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c8 c6 11 64 vshufps \$0x64,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0d d4 07 vblendpd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0d 11 07 vblendpd \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0d 11 07 vblendpd \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0c d4 07 vblendps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0c 11 07 vblendps \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0c 11 07 vblendps \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c2 d4 07 vcmpordpd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c2 11 07 vcmpordpd \(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c2 11 07 vcmpordpd \(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c2 d4 07 vcmpordps %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c2 11 07 vcmpordps \(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c2 11 07 vcmpordps \(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 41 d4 07 vdppd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 41 11 07 vdppd \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 41 11 07 vdppd \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 40 d4 07 vdpps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 40 11 07 vdpps \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 40 11 07 vdpps \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 42 d4 07 vmpsadbw \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 42 11 07 vmpsadbw \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 42 11 07 vmpsadbw \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0f d4 07 vpalignr \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0f 11 07 vpalignr \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0f 11 07 vpalignr \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0e d4 07 vpblendw \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0e 11 07 vpblendw \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0e 11 07 vpblendw \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c6 d4 07 vshufpd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%rcx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%rcx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4c fe 40 vpblendvb %xmm4,%xmm6,%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb %xmm4,\(%rcx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4c 39 40 vpblendvb %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 69 fc 20 vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 69 39 20 vfmaddpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 69 39 20 vfmaddpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 69 39 20 vfmaddpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 69 39 20 vfmaddpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 68 fc 20 vfmaddps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 68 39 20 vfmaddps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 68 39 20 vfmaddps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 68 39 20 vfmaddps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 68 39 20 vfmaddps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5d fc 20 vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5d 39 20 vfmaddsubpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5d 39 20 vfmaddsubpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5d 39 20 vfmaddsubpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5d 39 20 vfmaddsubpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5c fc 20 vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5c 39 20 vfmaddsubps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5c 39 20 vfmaddsubps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5c 39 20 vfmaddsubps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5c 39 20 vfmaddsubps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5f fc 20 vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5f 39 20 vfmsubaddpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5f 39 20 vfmsubaddpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5f 39 20 vfmsubaddpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5f 39 20 vfmsubaddpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5e fc 20 vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5e 39 20 vfmsubaddps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5e 39 20 vfmsubaddps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 5e 39 20 vfmsubaddps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 5e 39 20 vfmsubaddps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6d fc 20 vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6d 39 20 vfmsubpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6d 39 20 vfmsubpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6d 39 20 vfmsubpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6d 39 20 vfmsubpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6c fc 20 vfmsubps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6c 39 20 vfmsubps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6c 39 20 vfmsubps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6c 39 20 vfmsubps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6c 39 20 vfmsubps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 79 fc 20 vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 79 39 20 vfnmaddpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 79 39 20 vfnmaddpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 79 39 20 vfnmaddpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 79 39 20 vfnmaddpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 78 fc 20 vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 78 39 20 vfnmaddps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 78 39 20 vfnmaddps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 78 39 20 vfnmaddps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 78 39 20 vfnmaddps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7d fc 20 vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7d 39 20 vfnmsubpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7d 39 20 vfnmsubpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7d 39 20 vfnmsubpd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7d 39 20 vfnmsubpd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7c fc 20 vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7c 39 20 vfnmsubps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7c 39 20 vfnmsubps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7c 39 20 vfnmsubps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7c 39 20 vfnmsubps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 62 vpermilmo2pd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 62 vpermilmo2pd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 42 vpermilmo2pd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 63 vpermilmz2pd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 63 vpermilmz2pd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 43 vpermilmz2pd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 60 vpermiltd2pd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 60 vpermiltd2pd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 40 vpermiltd2pd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 62 vpermilmo2ps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 62 vpermilmo2ps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 42 vpermilmo2ps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 63 vpermilmz2ps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 63 vpermilmz2ps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 43 vpermilmz2ps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 60 vpermiltd2ps %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 60 vpermiltd2ps \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 40 vpermiltd2ps %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 fc 6a vpermil2pd \$0xa,%xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd \$0xa,\(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd \$0xa,%xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 49 39 6a vpermil2pd \$0xa,\(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 49 39 4a vpermil2pd \$0xa,%xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 fc 6a vpermil2ps \$0xa,%xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps \$0xa,\(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps \$0xa,%xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 e9 48 39 6a vpermil2ps \$0xa,\(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 69 48 39 4a vpermil2ps \$0xa,%xmm4,\(%rcx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c4 e2 7d 19 21 vbroadcastsd \(%rcx\),%ymm4
[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e1 da 2a f1 vcvtsi2ss %rcx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e1 da 2a 31 vcvtsi2ssq \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e1 da 2a 31 vcvtsi2ssq \(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 d9 22 f1 64 vpinsrq \$0x64,%rcx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 d9 22 31 64 vpinsrq \$0x64,\(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 d9 22 31 64 vpinsrq \$0x64,\(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 f9 16 e1 64 vpextrq \$0x64,%xmm4,%rcx
-[ ]*[a-f0-9]+: c4 e3 f9 16 21 64 vpextrq \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 f9 16 21 64 vpextrq \$0x64,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 d9 22 f1 07 vpinsrq \$0x7,%rcx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d9 22 31 07 vpinsrq \$0x7,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d9 22 31 07 vpinsrq \$0x7,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 f9 16 e1 07 vpextrq \$0x7,%xmm4,%rcx
+[ ]*[a-f0-9]+: c4 e3 f9 16 21 07 vpextrq \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 f9 16 21 07 vpextrq \$0x7,%xmm4,\(%rcx\)
[ ]*[a-f0-9]+: c5 d9 12 31 vmovlpd \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 d9 12 31 vmovlpd \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 d8 12 31 vmovlps \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 d9 16 31 vmovhpd \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 d8 16 31 vmovhps \(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 cb c2 d4 64 vcmpsd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 cb c2 11 64 vcmpsd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0b d4 64 vroundsd \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0b 11 64 vroundsd \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 c9 6b fc 20 vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6b 39 20 vfmaddsd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6b 39 20 vfmaddsd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6b 39 20 vfmaddsd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6b 39 20 vfmaddsd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6f fc 20 vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6f 39 20 vfmsubsd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6f 39 20 vfmsubsd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6f 39 20 vfmsubsd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6f 39 20 vfmsubsd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7b fc 20 vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7b 39 20 vfnmaddsd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7b 39 20 vfnmaddsd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7b 39 20 vfnmaddsd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7b 39 20 vfnmaddsd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7f fc 20 vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7f 39 20 vfnmsubsd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7f 39 20 vfnmsubsd %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7f 39 20 vfnmsubsd \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7f 39 20 vfnmsubsd %xmm4,\(%rcx\),%xmm2,%xmm7
+[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd \(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd \(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0b d4 07 vroundsd \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0b 11 07 vroundsd \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0b 11 07 vroundsd \$0x7,\(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 58 d4 vaddsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd \(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 58 11 vaddsd \(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 1f vcmptrue_ussd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd \(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 1f vcmptrue_ussd \(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%rcx\)
+[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%rcx\)
+[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%rcx\)
+[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%rcx\)
[ ]*[a-f0-9]+: c5 ca 58 d4 vaddss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca 58 11 vaddss \(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca 58 11 vaddss \(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx
[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps %xmm4,%ecx
[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb %xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 79 17 e1 07 vextractps \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 79 16 e1 07 vpextrd \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 16 21 07 vpextrd \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 79 16 21 07 vpextrd \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 79 17 e1 07 vextractps \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 79 17 21 07 vextractps \$0x7,%xmm4,\(%rcx\)
[ ]*[a-f0-9]+: c5 db 2a f1 vcvtsi2sd %ecx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 db 2a 31 vcvtsi2sdl \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 da 2a f1 vcvtsi2ss %ecx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 da 2a 31 vcvtsi2ssl \(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 ca c2 d4 64 vcmpss \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 ca c2 11 64 vcmpss \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 21 d4 64 vinsertps \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 21 11 64 vinsertps \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0a d4 64 vroundss \$0x64,%xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 49 0a 11 64 vroundss \$0x64,\(%rcx\),%xmm6,%xmm2
-[ ]*[a-f0-9]+: c4 e3 c9 6a fc 20 vfmaddss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6a 39 20 vfmaddss \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6a 39 20 vfmaddss %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6a 39 20 vfmaddss \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6a 39 20 vfmaddss %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6e fc 20 vfmsubss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6e 39 20 vfmsubss \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6e 39 20 vfmsubss %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 6e 39 20 vfmsubss \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 6e 39 20 vfmsubss %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7a fc 20 vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7a 39 20 vfnmaddss \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7a 39 20 vfnmaddss %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7a 39 20 vfnmaddss \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7a 39 20 vfnmaddss %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7e fc 20 vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7e 39 20 vfnmsubss \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7e 39 20 vfnmsubss %xmm4,\(%rcx\),%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 c9 7e 39 20 vfnmsubss \(%rcx\),%xmm6,%xmm2,%xmm7
-[ ]*[a-f0-9]+: c4 e3 59 7e 39 20 vfnmsubss %xmm4,\(%rcx\),%xmm2,%xmm7
+[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss \(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss \(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 21 d4 07 vinsertps \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 21 11 07 vinsertps \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 21 11 07 vinsertps \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0a d4 07 vroundss \$0x7,%xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0a 11 07 vroundss \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 49 0a 11 07 vroundss \$0x7,\(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq %xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq \(%rcx\),%xmm4
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 d9 c4 f1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 d9 c4 31 64 vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%rcx\)
-[ ]*[a-f0-9]+: c4 e3 59 20 f1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e3 59 20 31 64 vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 79 15 21 07 vpextrw \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c5 d9 c4 f1 07 vpinsrw \$0x7,%ecx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw \$0x7,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw \$0x7,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 d9 c4 f1 07 vpinsrw \$0x7,%ecx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw \$0x7,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 d9 c4 31 07 vpinsrw \$0x7,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 79 14 e1 07 vpextrb \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb \$0x7,%ecx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb \$0x7,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb \$0x7,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 14 e1 07 vpextrb \$0x7,%xmm4,%ecx
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 79 14 21 07 vpextrb \$0x7,%xmm4,\(%rcx\)
+[ ]*[a-f0-9]+: c4 e3 59 20 f1 07 vpinsrb \$0x7,%ecx,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb \$0x7,\(%rcx\),%xmm4,%xmm6
+[ ]*[a-f0-9]+: c4 e3 59 20 31 07 vpinsrb \$0x7,\(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx
[ ]*[a-f0-9]+: c5 c8 16 d4 vmovlhps %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb 10 d4 vmovsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca 10 d4 vmovss %xmm4,%xmm6,%xmm2
-[ ]*[a-f0-9]+: c5 c9 72 f4 64 vpslld \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 fc 64 vpslldq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 f4 64 vpsllq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 71 f4 64 vpsllw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 72 e4 64 vpsrad \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 71 e4 64 vpsraw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 72 d4 64 vpsrld \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 dc 64 vpsrldq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 73 d4 64 vpsrlq \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 c9 71 d4 64 vpsrlw \$0x64,%xmm4,%xmm6
-[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
+[ ]*[a-f0-9]+: c5 c9 72 f4 07 vpslld \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 fc 07 vpslldq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 f4 07 vpsllq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 71 f4 07 vpsllw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 72 e4 07 vpsrad \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 71 e4 07 vpsraw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 72 d4 07 vpsrld \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 dc 07 vpsrldq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 73 d4 07 vpsrlq \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 c9 71 d4 07 vpsrlw \$0x7,%xmm4,%xmm6
+[ ]*[a-f0-9]+: c5 f9 c5 cc 07 vpextrw \$0x7,%xmm4,%ecx
[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd %ymm4,%ecx
[ ]*[a-f0-9]+: c5 fc 50 cc vmovmskps %ymm4,%ecx
[ ]*[a-f0-9]+: c5 fd 50 cc vmovmskpd %ymm4,%ecx
[ ]*[a-f0-9]+: c5 7e e6 04 25 78 56 34 12 vcvtdq2pd 0x12345678,%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 04 25 78 56 34 12 vcvtpd2psy 0x12345678,%xmm8
[ ]*[a-f0-9]+: c5 39 e0 3c 25 78 56 34 12 vpavgb 0x12345678,%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 04 25 78 56 34 12 64 vaeskeygenassist \$0x64,0x12345678,%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 04 25 78 56 34 12 64 vpextrb \$0x64,%xmm8,0x12345678
+[ ]*[a-f0-9]+: c4 63 79 df 04 25 78 56 34 12 07 vaeskeygenassist \$0x7,0x12345678,%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 04 25 78 56 34 12 07 vpextrb \$0x7,%xmm8,0x12345678
[ ]*[a-f0-9]+: c5 3b 2a 3c 25 78 56 34 12 vcvtsi2sdl 0x12345678,%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a 34 25 78 56 34 12 80 vblendvps %xmm8,0x12345678,%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 3c 25 78 56 34 12 64 vpinsrb \$0x64,0x12345678,%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 3c 25 78 56 34 12 07 vpinsrb \$0x7,0x12345678,%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 04 25 78 56 34 12 vmovdqa 0x12345678,%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 04 25 78 56 34 12 vmovdqa %ymm8,0x12345678
[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 78 56 34 12 vpermilpd 0x12345678,%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 04 25 78 56 34 12 64 vroundpd \$0x64,0x12345678,%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 04 25 78 56 34 12 64 vextractf128 \$0x64,%ymm8,0x12345678
-[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 78 56 34 12 64 vperm2f128 \$0x64,0x12345678,%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 04 25 78 56 34 12 07 vroundpd \$0x7,0x12345678,%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 04 25 78 56 34 12 07 vextractf128 \$0x7,%ymm8,0x12345678
+[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 78 56 34 12 07 vperm2f128 \$0x7,0x12345678,%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 78 56 34 12 80 vblendvpd %ymm8,0x12345678,%ymm12,%ymm14
[ ]*[a-f0-9]+: c5 f8 ae 55 00 vldmxcsr 0x0\(%rbp\)
[ ]*[a-f0-9]+: c5 79 6f 45 00 vmovdqa 0x0\(%rbp\),%xmm8
[ ]*[a-f0-9]+: c5 7e e6 45 00 vcvtdq2pd 0x0\(%rbp\),%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 45 00 vcvtpd2psy 0x0\(%rbp\),%xmm8
[ ]*[a-f0-9]+: c5 39 e0 7d 00 vpavgb 0x0\(%rbp\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 45 00 64 vaeskeygenassist \$0x64,0x0\(%rbp\),%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 45 00 64 vpextrb \$0x64,%xmm8,0x0\(%rbp\)
+[ ]*[a-f0-9]+: c4 63 79 df 45 00 07 vaeskeygenassist \$0x7,0x0\(%rbp\),%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 45 00 07 vpextrb \$0x7,%xmm8,0x0\(%rbp\)
[ ]*[a-f0-9]+: c5 3b 2a 7d 00 vcvtsi2sdl 0x0\(%rbp\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a 75 00 80 vblendvps %xmm8,0x0\(%rbp\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 7d 00 64 vpinsrb \$0x64,0x0\(%rbp\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 7d 00 07 vpinsrb \$0x7,0x0\(%rbp\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 45 00 vmovdqa 0x0\(%rbp\),%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 45 00 vmovdqa %ymm8,0x0\(%rbp\)
[ ]*[a-f0-9]+: c4 62 3d 0d 7d 00 vpermilpd 0x0\(%rbp\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 45 00 64 vroundpd \$0x64,0x0\(%rbp\),%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 45 00 64 vextractf128 \$0x64,%ymm8,0x0\(%rbp\)
-[ ]*[a-f0-9]+: c4 63 3d 06 7d 00 64 vperm2f128 \$0x64,0x0\(%rbp\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 45 00 07 vroundpd \$0x7,0x0\(%rbp\),%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 45 00 07 vextractf128 \$0x7,%ymm8,0x0\(%rbp\)
+[ ]*[a-f0-9]+: c4 63 3d 06 7d 00 07 vperm2f128 \$0x7,0x0\(%rbp\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b 75 00 80 vblendvpd %ymm8,0x0\(%rbp\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c5 f8 ae 95 99 00 00 00 vldmxcsr 0x99\(%rbp\)
[ ]*[a-f0-9]+: c5 79 6f 85 99 00 00 00 vmovdqa 0x99\(%rbp\),%xmm8
[ ]*[a-f0-9]+: c5 7e e6 85 99 00 00 00 vcvtdq2pd 0x99\(%rbp\),%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 85 99 00 00 00 vcvtpd2psy 0x99\(%rbp\),%xmm8
[ ]*[a-f0-9]+: c5 39 e0 bd 99 00 00 00 vpavgb 0x99\(%rbp\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 85 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%rbp\),%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 85 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%rbp\)
+[ ]*[a-f0-9]+: c4 63 79 df 85 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%rbp\),%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 85 99 00 00 00 07 vpextrb \$0x7,%xmm8,0x99\(%rbp\)
[ ]*[a-f0-9]+: c5 3b 2a bd 99 00 00 00 vcvtsi2sdl 0x99\(%rbp\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a b5 99 00 00 00 80 vblendvps %xmm8,0x99\(%rbp\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 bd 99 00 00 00 64 vpinsrb \$0x64,0x99\(%rbp\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 bd 99 00 00 00 07 vpinsrb \$0x7,0x99\(%rbp\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 85 99 00 00 00 vmovdqa 0x99\(%rbp\),%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 85 99 00 00 00 vmovdqa %ymm8,0x99\(%rbp\)
[ ]*[a-f0-9]+: c4 62 3d 0d bd 99 00 00 00 vpermilpd 0x99\(%rbp\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 85 99 00 00 00 64 vroundpd \$0x64,0x99\(%rbp\),%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 85 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%rbp\)
-[ ]*[a-f0-9]+: c4 63 3d 06 bd 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%rbp\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 85 99 00 00 00 07 vroundpd \$0x7,0x99\(%rbp\),%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 85 99 00 00 00 07 vextractf128 \$0x7,%ymm8,0x99\(%rbp\)
+[ ]*[a-f0-9]+: c4 63 3d 06 bd 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%rbp\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b b5 99 00 00 00 80 vblendvpd %ymm8,0x99\(%rbp\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c4 c1 78 ae 97 99 00 00 00 vldmxcsr 0x99\(%r15\)
[ ]*[a-f0-9]+: c4 41 79 6f 87 99 00 00 00 vmovdqa 0x99\(%r15\),%xmm8
[ ]*[a-f0-9]+: c4 41 7e e6 87 99 00 00 00 vcvtdq2pd 0x99\(%r15\),%ymm8
[ ]*[a-f0-9]+: c4 41 7d 5a 87 99 00 00 00 vcvtpd2psy 0x99\(%r15\),%xmm8
[ ]*[a-f0-9]+: c4 41 39 e0 bf 99 00 00 00 vpavgb 0x99\(%r15\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 43 79 df 87 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%r15\),%xmm8
-[ ]*[a-f0-9]+: c4 43 79 14 87 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%r15\)
+[ ]*[a-f0-9]+: c4 43 79 df 87 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%r15\),%xmm8
+[ ]*[a-f0-9]+: c4 43 79 14 87 99 00 00 00 07 vpextrb \$0x7,%xmm8,0x99\(%r15\)
[ ]*[a-f0-9]+: c4 41 3b 2a bf 99 00 00 00 vcvtsi2sdl 0x99\(%r15\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 43 19 4a b7 99 00 00 00 80 vblendvps %xmm8,0x99\(%r15\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 43 39 20 bf 99 00 00 00 64 vpinsrb \$0x64,0x99\(%r15\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 43 39 20 bf 99 00 00 00 07 vpinsrb \$0x7,0x99\(%r15\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 41 7d 6f 87 99 00 00 00 vmovdqa 0x99\(%r15\),%ymm8
[ ]*[a-f0-9]+: c4 41 7d 7f 87 99 00 00 00 vmovdqa %ymm8,0x99\(%r15\)
[ ]*[a-f0-9]+: c4 42 3d 0d bf 99 00 00 00 vpermilpd 0x99\(%r15\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 43 7d 09 87 99 00 00 00 64 vroundpd \$0x64,0x99\(%r15\),%ymm8
-[ ]*[a-f0-9]+: c4 43 7d 19 87 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%r15\)
-[ ]*[a-f0-9]+: c4 43 3d 06 bf 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%r15\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 43 7d 09 87 99 00 00 00 07 vroundpd \$0x7,0x99\(%r15\),%ymm8
+[ ]*[a-f0-9]+: c4 43 7d 19 87 99 00 00 00 07 vextractf128 \$0x7,%ymm8,0x99\(%r15\)
+[ ]*[a-f0-9]+: c4 43 3d 06 bf 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%r15\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 43 1d 4b b7 99 00 00 00 80 vblendvpd %ymm8,0x99\(%r15\),%ymm12,%ymm14
-[ ]*[a-f0-9]+: c5 f8 ae 15 99 00 00 00 vldmxcsr 0x99\(%rip\) # 48da <_start\+0x48da>
-[ ]*[a-f0-9]+: c5 79 6f 05 99 00 00 00 vmovdqa 0x99\(%rip\),%xmm8 # 48e2 <_start\+0x48e2>
-[ ]*[a-f0-9]+: c5 79 7f 05 99 00 00 00 vmovdqa %xmm8,0x99\(%rip\) # 48ea <_start\+0x48ea>
-[ ]*[a-f0-9]+: c5 79 7e 05 99 00 00 00 vmovd %xmm8,0x99\(%rip\) # 48f2 <_start\+0x48f2>
-[ ]*[a-f0-9]+: c5 7b 2d 05 99 00 00 00 vcvtsd2si 0x99\(%rip\),%r8d # 48fa <_start\+0x48fa>
-[ ]*[a-f0-9]+: c5 7e e6 05 99 00 00 00 vcvtdq2pd 0x99\(%rip\),%ymm8 # 4902 <_start\+0x4902>
-[ ]*[a-f0-9]+: c5 7d 5a 05 99 00 00 00 vcvtpd2psy 0x99\(%rip\),%xmm8 # 490a <_start\+0x490a>
-[ ]*[a-f0-9]+: c5 39 e0 3d 99 00 00 00 vpavgb 0x99\(%rip\),%xmm8,%xmm15 # 4912 <_start\+0x4912>
-[ ]*[a-f0-9]+: c4 63 79 df 05 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%rip\),%xmm8 # 491c <_start\+0x491c>
-[ ]*[a-f0-9]+: c4 63 79 14 05 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%rip\) # 4926 <_start\+0x4926>
-[ ]*[a-f0-9]+: c5 3b 2a 3d 99 00 00 00 vcvtsi2sdl 0x99\(%rip\),%xmm8,%xmm15 # 492e <_start\+0x492e>
-[ ]*[a-f0-9]+: c4 63 19 4a 35 99 00 00 00 80 vblendvps %xmm8,0x99\(%rip\),%xmm12,%xmm14 # 4938 <_start\+0x4938>
-[ ]*[a-f0-9]+: c4 63 39 20 3d 99 00 00 00 64 vpinsrb \$0x64,0x99\(%rip\),%xmm8,%xmm15 # 4942 <_start\+0x4942>
-[ ]*[a-f0-9]+: c5 7d 6f 05 99 00 00 00 vmovdqa 0x99\(%rip\),%ymm8 # 494a <_start\+0x494a>
-[ ]*[a-f0-9]+: c5 7d 7f 05 99 00 00 00 vmovdqa %ymm8,0x99\(%rip\) # 4952 <_start\+0x4952>
-[ ]*[a-f0-9]+: c4 62 3d 0d 3d 99 00 00 00 vpermilpd 0x99\(%rip\),%ymm8,%ymm15 # 495b <_start\+0x495b>
-[ ]*[a-f0-9]+: c4 63 7d 09 05 99 00 00 00 64 vroundpd \$0x64,0x99\(%rip\),%ymm8 # 4965 <_start\+0x4965>
-[ ]*[a-f0-9]+: c4 63 7d 19 05 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%rip\) # 496f <_start\+0x496f>
-[ ]*[a-f0-9]+: c4 63 3d 06 3d 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%rip\),%ymm8,%ymm15 # 4979 <_start\+0x4979>
-[ ]*[a-f0-9]+: c4 63 1d 4b 35 99 00 00 00 80 vblendvpd %ymm8,0x99\(%rip\),%ymm12,%ymm14 # 4983 <_start\+0x4983>
+[ ]*[a-f0-9]+: c5 f8 ae 15 99 00 00 00 vldmxcsr 0x99\(%rip\) # 415a <_start\+0x415a>
+[ ]*[a-f0-9]+: c5 79 6f 05 99 00 00 00 vmovdqa 0x99\(%rip\),%xmm8 # 4162 <_start\+0x4162>
+[ ]*[a-f0-9]+: c5 79 7f 05 99 00 00 00 vmovdqa %xmm8,0x99\(%rip\) # 416a <_start\+0x416a>
+[ ]*[a-f0-9]+: c5 79 7e 05 99 00 00 00 vmovd %xmm8,0x99\(%rip\) # 4172 <_start\+0x4172>
+[ ]*[a-f0-9]+: c5 7b 2d 05 99 00 00 00 vcvtsd2si 0x99\(%rip\),%r8d # 417a <_start\+0x417a>
+[ ]*[a-f0-9]+: c5 7e e6 05 99 00 00 00 vcvtdq2pd 0x99\(%rip\),%ymm8 # 4182 <_start\+0x4182>
+[ ]*[a-f0-9]+: c5 7d 5a 05 99 00 00 00 vcvtpd2psy 0x99\(%rip\),%xmm8 # 418a <_start\+0x418a>
+[ ]*[a-f0-9]+: c5 39 e0 3d 99 00 00 00 vpavgb 0x99\(%rip\),%xmm8,%xmm15 # 4192 <_start\+0x4192>
+[ ]*[a-f0-9]+: c4 63 79 df 05 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%rip\),%xmm8 # 419c <_start\+0x419c>
+[ ]*[a-f0-9]+: c4 63 79 14 05 99 00 00 00 07 vpextrb \$0x7,%xmm8,0x99\(%rip\) # 41a6 <_start\+0x41a6>
+[ ]*[a-f0-9]+: c5 3b 2a 3d 99 00 00 00 vcvtsi2sdl 0x99\(%rip\),%xmm8,%xmm15 # 41ae <_start\+0x41ae>
+[ ]*[a-f0-9]+: c4 63 19 4a 35 99 00 00 00 80 vblendvps %xmm8,0x99\(%rip\),%xmm12,%xmm14 # 41b8 <_start\+0x41b8>
+[ ]*[a-f0-9]+: c4 63 39 20 3d 99 00 00 00 07 vpinsrb \$0x7,0x99\(%rip\),%xmm8,%xmm15 # 41c2 <_start\+0x41c2>
+[ ]*[a-f0-9]+: c5 7d 6f 05 99 00 00 00 vmovdqa 0x99\(%rip\),%ymm8 # 41ca <_start\+0x41ca>
+[ ]*[a-f0-9]+: c5 7d 7f 05 99 00 00 00 vmovdqa %ymm8,0x99\(%rip\) # 41d2 <_start\+0x41d2>
+[ ]*[a-f0-9]+: c4 62 3d 0d 3d 99 00 00 00 vpermilpd 0x99\(%rip\),%ymm8,%ymm15 # 41db <_start\+0x41db>
+[ ]*[a-f0-9]+: c4 63 7d 09 05 99 00 00 00 07 vroundpd \$0x7,0x99\(%rip\),%ymm8 # 41e5 <_start\+0x41e5>
+[ ]*[a-f0-9]+: c4 63 7d 19 05 99 00 00 00 07 vextractf128 \$0x7,%ymm8,0x99\(%rip\) # 41ef <_start\+0x41ef>
+[ ]*[a-f0-9]+: c4 63 3d 06 3d 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%rip\),%ymm8,%ymm15 # 41f9 <_start\+0x41f9>
+[ ]*[a-f0-9]+: c4 63 1d 4b 35 99 00 00 00 80 vblendvpd %ymm8,0x99\(%rip\),%ymm12,%ymm14 # 4203 <_start\+0x4203>
[ ]*[a-f0-9]+: c5 f8 ae 94 24 99 00 00 00 vldmxcsr 0x99\(%rsp\)
[ ]*[a-f0-9]+: c5 79 6f 84 24 99 00 00 00 vmovdqa 0x99\(%rsp\),%xmm8
[ ]*[a-f0-9]+: c5 79 7f 84 24 99 00 00 00 vmovdqa %xmm8,0x99\(%rsp\)
[ ]*[a-f0-9]+: c5 7e e6 84 24 99 00 00 00 vcvtdq2pd 0x99\(%rsp\),%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 84 24 99 00 00 00 vcvtpd2psy 0x99\(%rsp\),%xmm8
[ ]*[a-f0-9]+: c5 39 e0 bc 24 99 00 00 00 vpavgb 0x99\(%rsp\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 84 24 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%rsp\),%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 84 24 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%rsp\)
+[ ]*[a-f0-9]+: c4 63 79 df 84 24 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%rsp\),%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 84 24 99 00 00 00 07 vpextrb \$0x7,%xmm8,0x99\(%rsp\)
[ ]*[a-f0-9]+: c5 3b 2a bc 24 99 00 00 00 vcvtsi2sdl 0x99\(%rsp\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a b4 24 99 00 00 00 80 vblendvps %xmm8,0x99\(%rsp\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 bc 24 99 00 00 00 64 vpinsrb \$0x64,0x99\(%rsp\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 bc 24 99 00 00 00 07 vpinsrb \$0x7,0x99\(%rsp\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 84 24 99 00 00 00 vmovdqa 0x99\(%rsp\),%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 84 24 99 00 00 00 vmovdqa %ymm8,0x99\(%rsp\)
[ ]*[a-f0-9]+: c4 62 3d 0d bc 24 99 00 00 00 vpermilpd 0x99\(%rsp\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 84 24 99 00 00 00 64 vroundpd \$0x64,0x99\(%rsp\),%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 84 24 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%rsp\)
-[ ]*[a-f0-9]+: c4 63 3d 06 bc 24 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%rsp\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 84 24 99 00 00 00 07 vroundpd \$0x7,0x99\(%rsp\),%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 84 24 99 00 00 00 07 vextractf128 \$0x7,%ymm8,0x99\(%rsp\)
+[ ]*[a-f0-9]+: c4 63 3d 06 bc 24 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%rsp\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b b4 24 99 00 00 00 80 vblendvpd %ymm8,0x99\(%rsp\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c4 c1 78 ae 94 24 99 00 00 00 vldmxcsr 0x99\(%r12\)
[ ]*[a-f0-9]+: c4 41 79 6f 84 24 99 00 00 00 vmovdqa 0x99\(%r12\),%xmm8
[ ]*[a-f0-9]+: c4 41 7e e6 84 24 99 00 00 00 vcvtdq2pd 0x99\(%r12\),%ymm8
[ ]*[a-f0-9]+: c4 41 7d 5a 84 24 99 00 00 00 vcvtpd2psy 0x99\(%r12\),%xmm8
[ ]*[a-f0-9]+: c4 41 39 e0 bc 24 99 00 00 00 vpavgb 0x99\(%r12\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 43 79 df 84 24 99 00 00 00 64 vaeskeygenassist \$0x64,0x99\(%r12\),%xmm8
-[ ]*[a-f0-9]+: c4 43 79 14 84 24 99 00 00 00 64 vpextrb \$0x64,%xmm8,0x99\(%r12\)
+[ ]*[a-f0-9]+: c4 43 79 df 84 24 99 00 00 00 07 vaeskeygenassist \$0x7,0x99\(%r12\),%xmm8
+[ ]*[a-f0-9]+: c4 43 79 14 84 24 99 00 00 00 07 vpextrb \$0x7,%xmm8,0x99\(%r12\)
[ ]*[a-f0-9]+: c4 41 3b 2a bc 24 99 00 00 00 vcvtsi2sdl 0x99\(%r12\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 43 19 4a b4 24 99 00 00 00 80 vblendvps %xmm8,0x99\(%r12\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 43 39 20 bc 24 99 00 00 00 64 vpinsrb \$0x64,0x99\(%r12\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 43 39 20 bc 24 99 00 00 00 07 vpinsrb \$0x7,0x99\(%r12\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 41 7d 6f 84 24 99 00 00 00 vmovdqa 0x99\(%r12\),%ymm8
[ ]*[a-f0-9]+: c4 41 7d 7f 84 24 99 00 00 00 vmovdqa %ymm8,0x99\(%r12\)
[ ]*[a-f0-9]+: c4 42 3d 0d bc 24 99 00 00 00 vpermilpd 0x99\(%r12\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 43 7d 09 84 24 99 00 00 00 64 vroundpd \$0x64,0x99\(%r12\),%ymm8
-[ ]*[a-f0-9]+: c4 43 7d 19 84 24 99 00 00 00 64 vextractf128 \$0x64,%ymm8,0x99\(%r12\)
-[ ]*[a-f0-9]+: c4 43 3d 06 bc 24 99 00 00 00 64 vperm2f128 \$0x64,0x99\(%r12\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 43 7d 09 84 24 99 00 00 00 07 vroundpd \$0x7,0x99\(%r12\),%ymm8
+[ ]*[a-f0-9]+: c4 43 7d 19 84 24 99 00 00 00 07 vextractf128 \$0x7,%ymm8,0x99\(%r12\)
+[ ]*[a-f0-9]+: c4 43 3d 06 bc 24 99 00 00 00 07 vperm2f128 \$0x7,0x99\(%r12\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 43 1d 4b b4 24 99 00 00 00 80 vblendvpd %ymm8,0x99\(%r12\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c5 f8 ae 14 25 67 ff ff ff vldmxcsr 0xffffffffffffff67
[ ]*[a-f0-9]+: c5 79 6f 04 25 67 ff ff ff vmovdqa 0xffffffffffffff67,%xmm8
[ ]*[a-f0-9]+: c5 7e e6 04 25 67 ff ff ff vcvtdq2pd 0xffffffffffffff67,%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 04 25 67 ff ff ff vcvtpd2psy 0xffffffffffffff67,%xmm8
[ ]*[a-f0-9]+: c5 39 e0 3c 25 67 ff ff ff vpavgb 0xffffffffffffff67,%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 04 25 67 ff ff ff 64 vaeskeygenassist \$0x64,0xffffffffffffff67,%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 04 25 67 ff ff ff 64 vpextrb \$0x64,%xmm8,0xffffffffffffff67
+[ ]*[a-f0-9]+: c4 63 79 df 04 25 67 ff ff ff 07 vaeskeygenassist \$0x7,0xffffffffffffff67,%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 04 25 67 ff ff ff 07 vpextrb \$0x7,%xmm8,0xffffffffffffff67
[ ]*[a-f0-9]+: c5 3b 2a 3c 25 67 ff ff ff vcvtsi2sdl 0xffffffffffffff67,%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a 34 25 67 ff ff ff 80 vblendvps %xmm8,0xffffffffffffff67,%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 3c 25 67 ff ff ff 64 vpinsrb \$0x64,0xffffffffffffff67,%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 3c 25 67 ff ff ff 07 vpinsrb \$0x7,0xffffffffffffff67,%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 04 25 67 ff ff ff vmovdqa 0xffffffffffffff67,%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 04 25 67 ff ff ff vmovdqa %ymm8,0xffffffffffffff67
[ ]*[a-f0-9]+: c4 62 3d 0d 3c 25 67 ff ff ff vpermilpd 0xffffffffffffff67,%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 04 25 67 ff ff ff 64 vroundpd \$0x64,0xffffffffffffff67,%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 04 25 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,0xffffffffffffff67
-[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 67 ff ff ff 64 vperm2f128 \$0x64,0xffffffffffffff67,%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 04 25 67 ff ff ff 07 vroundpd \$0x7,0xffffffffffffff67,%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 04 25 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,0xffffffffffffff67
+[ ]*[a-f0-9]+: c4 63 3d 06 3c 25 67 ff ff ff 07 vperm2f128 \$0x7,0xffffffffffffff67,%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b 34 25 67 ff ff ff 80 vblendvpd %ymm8,0xffffffffffffff67,%ymm12,%ymm14
[ ]*[a-f0-9]+: c5 f8 ae 14 65 67 ff ff ff vldmxcsr -0x99\(,%riz,2\)
[ ]*[a-f0-9]+: c5 79 6f 04 65 67 ff ff ff vmovdqa -0x99\(,%riz,2\),%xmm8
[ ]*[a-f0-9]+: c5 7e e6 04 65 67 ff ff ff vcvtdq2pd -0x99\(,%riz,2\),%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 04 65 67 ff ff ff vcvtpd2psy -0x99\(,%riz,2\),%xmm8
[ ]*[a-f0-9]+: c5 39 e0 3c 65 67 ff ff ff vpavgb -0x99\(,%riz,2\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 04 65 67 ff ff ff 64 vaeskeygenassist \$0x64,-0x99\(,%riz,2\),%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 04 65 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(,%riz,2\)
+[ ]*[a-f0-9]+: c4 63 79 df 04 65 67 ff ff ff 07 vaeskeygenassist \$0x7,-0x99\(,%riz,2\),%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 04 65 67 ff ff ff 07 vpextrb \$0x7,%xmm8,-0x99\(,%riz,2\)
[ ]*[a-f0-9]+: c5 3b 2a 3c 65 67 ff ff ff vcvtsi2sdl -0x99\(,%riz,2\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a 34 65 67 ff ff ff 80 vblendvps %xmm8,-0x99\(,%riz,2\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 3c 65 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(,%riz,2\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 3c 65 67 ff ff ff 07 vpinsrb \$0x7,-0x99\(,%riz,2\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 04 65 67 ff ff ff vmovdqa -0x99\(,%riz,2\),%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 04 65 67 ff ff ff vmovdqa %ymm8,-0x99\(,%riz,2\)
[ ]*[a-f0-9]+: c4 62 3d 0d 3c 65 67 ff ff ff vpermilpd -0x99\(,%riz,2\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 04 65 67 ff ff ff 64 vroundpd \$0x64,-0x99\(,%riz,2\),%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 04 65 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(,%riz,2\)
-[ ]*[a-f0-9]+: c4 63 3d 06 3c 65 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(,%riz,2\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 04 65 67 ff ff ff 07 vroundpd \$0x7,-0x99\(,%riz,2\),%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 04 65 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,-0x99\(,%riz,2\)
+[ ]*[a-f0-9]+: c4 63 3d 06 3c 65 67 ff ff ff 07 vperm2f128 \$0x7,-0x99\(,%riz,2\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b 34 65 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(,%riz,2\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c5 f8 ae 94 23 67 ff ff ff vldmxcsr -0x99\(%rbx,%riz,1\)
[ ]*[a-f0-9]+: c5 79 6f 84 23 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,1\),%xmm8
[ ]*[a-f0-9]+: c5 7e e6 84 23 67 ff ff ff vcvtdq2pd -0x99\(%rbx,%riz,1\),%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 84 23 67 ff ff ff vcvtpd2psy -0x99\(%rbx,%riz,1\),%xmm8
[ ]*[a-f0-9]+: c5 39 e0 bc 23 67 ff ff ff vpavgb -0x99\(%rbx,%riz,1\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 84 23 67 ff ff ff 64 vaeskeygenassist \$0x64,-0x99\(%rbx,%riz,1\),%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 84 23 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rbx,%riz,1\)
+[ ]*[a-f0-9]+: c4 63 79 df 84 23 67 ff ff ff 07 vaeskeygenassist \$0x7,-0x99\(%rbx,%riz,1\),%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 84 23 67 ff ff ff 07 vpextrb \$0x7,%xmm8,-0x99\(%rbx,%riz,1\)
[ ]*[a-f0-9]+: c5 3b 2a bc 23 67 ff ff ff vcvtsi2sdl -0x99\(%rbx,%riz,1\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a b4 23 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rbx,%riz,1\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 bc 23 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rbx,%riz,1\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 bc 23 67 ff ff ff 07 vpinsrb \$0x7,-0x99\(%rbx,%riz,1\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 84 23 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,1\),%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 84 23 67 ff ff ff vmovdqa %ymm8,-0x99\(%rbx,%riz,1\)
[ ]*[a-f0-9]+: c4 62 3d 0d bc 23 67 ff ff ff vpermilpd -0x99\(%rbx,%riz,1\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 84 23 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rbx,%riz,1\),%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 84 23 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rbx,%riz,1\)
-[ ]*[a-f0-9]+: c4 63 3d 06 bc 23 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rbx,%riz,1\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 84 23 67 ff ff ff 07 vroundpd \$0x7,-0x99\(%rbx,%riz,1\),%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 84 23 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,-0x99\(%rbx,%riz,1\)
+[ ]*[a-f0-9]+: c4 63 3d 06 bc 23 67 ff ff ff 07 vperm2f128 \$0x7,-0x99\(%rbx,%riz,1\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b b4 23 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rbx,%riz,1\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c5 f8 ae 94 63 67 ff ff ff vldmxcsr -0x99\(%rbx,%riz,2\)
[ ]*[a-f0-9]+: c5 79 6f 84 63 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,2\),%xmm8
[ ]*[a-f0-9]+: c5 7e e6 84 63 67 ff ff ff vcvtdq2pd -0x99\(%rbx,%riz,2\),%ymm8
[ ]*[a-f0-9]+: c5 7d 5a 84 63 67 ff ff ff vcvtpd2psy -0x99\(%rbx,%riz,2\),%xmm8
[ ]*[a-f0-9]+: c5 39 e0 bc 63 67 ff ff ff vpavgb -0x99\(%rbx,%riz,2\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 63 79 df 84 63 67 ff ff ff 64 vaeskeygenassist \$0x64,-0x99\(%rbx,%riz,2\),%xmm8
-[ ]*[a-f0-9]+: c4 63 79 14 84 63 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rbx,%riz,2\)
+[ ]*[a-f0-9]+: c4 63 79 df 84 63 67 ff ff ff 07 vaeskeygenassist \$0x7,-0x99\(%rbx,%riz,2\),%xmm8
+[ ]*[a-f0-9]+: c4 63 79 14 84 63 67 ff ff ff 07 vpextrb \$0x7,%xmm8,-0x99\(%rbx,%riz,2\)
[ ]*[a-f0-9]+: c5 3b 2a bc 63 67 ff ff ff vcvtsi2sdl -0x99\(%rbx,%riz,2\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 63 19 4a b4 63 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rbx,%riz,2\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 63 39 20 bc 63 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rbx,%riz,2\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 63 39 20 bc 63 67 ff ff ff 07 vpinsrb \$0x7,-0x99\(%rbx,%riz,2\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c5 7d 6f 84 63 67 ff ff ff vmovdqa -0x99\(%rbx,%riz,2\),%ymm8
[ ]*[a-f0-9]+: c5 7d 7f 84 63 67 ff ff ff vmovdqa %ymm8,-0x99\(%rbx,%riz,2\)
[ ]*[a-f0-9]+: c4 62 3d 0d bc 63 67 ff ff ff vpermilpd -0x99\(%rbx,%riz,2\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 63 7d 09 84 63 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rbx,%riz,2\),%ymm8
-[ ]*[a-f0-9]+: c4 63 7d 19 84 63 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rbx,%riz,2\)
-[ ]*[a-f0-9]+: c4 63 3d 06 bc 63 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rbx,%riz,2\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 63 7d 09 84 63 67 ff ff ff 07 vroundpd \$0x7,-0x99\(%rbx,%riz,2\),%ymm8
+[ ]*[a-f0-9]+: c4 63 7d 19 84 63 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,-0x99\(%rbx,%riz,2\)
+[ ]*[a-f0-9]+: c4 63 3d 06 bc 63 67 ff ff ff 07 vperm2f128 \$0x7,-0x99\(%rbx,%riz,2\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 63 1d 4b b4 63 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rbx,%riz,2\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c4 81 78 ae 94 bc 67 ff ff ff vldmxcsr -0x99\(%r12,%r15,4\)
[ ]*[a-f0-9]+: c4 01 79 6f 84 bc 67 ff ff ff vmovdqa -0x99\(%r12,%r15,4\),%xmm8
[ ]*[a-f0-9]+: c4 01 7e e6 84 bc 67 ff ff ff vcvtdq2pd -0x99\(%r12,%r15,4\),%ymm8
[ ]*[a-f0-9]+: c4 01 7d 5a 84 bc 67 ff ff ff vcvtpd2psy -0x99\(%r12,%r15,4\),%xmm8
[ ]*[a-f0-9]+: c4 01 39 e0 bc bc 67 ff ff ff vpavgb -0x99\(%r12,%r15,4\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 03 79 df 84 bc 67 ff ff ff 64 vaeskeygenassist \$0x64,-0x99\(%r12,%r15,4\),%xmm8
-[ ]*[a-f0-9]+: c4 03 79 14 84 bc 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%r12,%r15,4\)
+[ ]*[a-f0-9]+: c4 03 79 df 84 bc 67 ff ff ff 07 vaeskeygenassist \$0x7,-0x99\(%r12,%r15,4\),%xmm8
+[ ]*[a-f0-9]+: c4 03 79 14 84 bc 67 ff ff ff 07 vpextrb \$0x7,%xmm8,-0x99\(%r12,%r15,4\)
[ ]*[a-f0-9]+: c4 01 3b 2a bc bc 67 ff ff ff vcvtsi2sdl -0x99\(%r12,%r15,4\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 03 19 4a b4 bc 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%r12,%r15,4\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 03 39 20 bc bc 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%r12,%r15,4\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 03 39 20 bc bc 67 ff ff ff 07 vpinsrb \$0x7,-0x99\(%r12,%r15,4\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 01 7d 6f 84 bc 67 ff ff ff vmovdqa -0x99\(%r12,%r15,4\),%ymm8
[ ]*[a-f0-9]+: c4 01 7d 7f 84 bc 67 ff ff ff vmovdqa %ymm8,-0x99\(%r12,%r15,4\)
[ ]*[a-f0-9]+: c4 02 3d 0d bc bc 67 ff ff ff vpermilpd -0x99\(%r12,%r15,4\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 03 7d 09 84 bc 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%r12,%r15,4\),%ymm8
-[ ]*[a-f0-9]+: c4 03 7d 19 84 bc 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%r12,%r15,4\)
-[ ]*[a-f0-9]+: c4 03 3d 06 bc bc 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%r12,%r15,4\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 03 7d 09 84 bc 67 ff ff ff 07 vroundpd \$0x7,-0x99\(%r12,%r15,4\),%ymm8
+[ ]*[a-f0-9]+: c4 03 7d 19 84 bc 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,-0x99\(%r12,%r15,4\)
+[ ]*[a-f0-9]+: c4 03 3d 06 bc bc 67 ff ff ff 07 vperm2f128 \$0x7,-0x99\(%r12,%r15,4\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 03 1d 4b b4 bc 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%r12,%r15,4\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c4 81 78 ae 94 f8 67 ff ff ff vldmxcsr -0x99\(%r8,%r15,8\)
[ ]*[a-f0-9]+: c4 01 79 6f 84 f8 67 ff ff ff vmovdqa -0x99\(%r8,%r15,8\),%xmm8
[ ]*[a-f0-9]+: c4 01 7e e6 84 f8 67 ff ff ff vcvtdq2pd -0x99\(%r8,%r15,8\),%ymm8
[ ]*[a-f0-9]+: c4 01 7d 5a 84 f8 67 ff ff ff vcvtpd2psy -0x99\(%r8,%r15,8\),%xmm8
[ ]*[a-f0-9]+: c4 01 39 e0 bc f8 67 ff ff ff vpavgb -0x99\(%r8,%r15,8\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 03 79 df 84 f8 67 ff ff ff 64 vaeskeygenassist \$0x64,-0x99\(%r8,%r15,8\),%xmm8
-[ ]*[a-f0-9]+: c4 03 79 14 84 f8 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%r8,%r15,8\)
+[ ]*[a-f0-9]+: c4 03 79 df 84 f8 67 ff ff ff 07 vaeskeygenassist \$0x7,-0x99\(%r8,%r15,8\),%xmm8
+[ ]*[a-f0-9]+: c4 03 79 14 84 f8 67 ff ff ff 07 vpextrb \$0x7,%xmm8,-0x99\(%r8,%r15,8\)
[ ]*[a-f0-9]+: c4 01 3b 2a bc f8 67 ff ff ff vcvtsi2sdl -0x99\(%r8,%r15,8\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 03 19 4a b4 f8 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%r8,%r15,8\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 03 39 20 bc f8 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%r8,%r15,8\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 03 39 20 bc f8 67 ff ff ff 07 vpinsrb \$0x7,-0x99\(%r8,%r15,8\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 01 7d 6f 84 f8 67 ff ff ff vmovdqa -0x99\(%r8,%r15,8\),%ymm8
[ ]*[a-f0-9]+: c4 01 7d 7f 84 f8 67 ff ff ff vmovdqa %ymm8,-0x99\(%r8,%r15,8\)
[ ]*[a-f0-9]+: c4 02 3d 0d bc f8 67 ff ff ff vpermilpd -0x99\(%r8,%r15,8\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 03 7d 09 84 f8 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%r8,%r15,8\),%ymm8
-[ ]*[a-f0-9]+: c4 03 7d 19 84 f8 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%r8,%r15,8\)
-[ ]*[a-f0-9]+: c4 03 3d 06 bc f8 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%r8,%r15,8\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 03 7d 09 84 f8 67 ff ff ff 07 vroundpd \$0x7,-0x99\(%r8,%r15,8\),%ymm8
+[ ]*[a-f0-9]+: c4 03 7d 19 84 f8 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,-0x99\(%r8,%r15,8\)
+[ ]*[a-f0-9]+: c4 03 3d 06 bc f8 67 ff ff ff 07 vperm2f128 \$0x7,-0x99\(%r8,%r15,8\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 03 1d 4b b4 f8 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%r8,%r15,8\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c4 a1 78 ae 94 a5 67 ff ff ff vldmxcsr -0x99\(%rbp,%r12,4\)
[ ]*[a-f0-9]+: c4 21 79 6f 84 a5 67 ff ff ff vmovdqa -0x99\(%rbp,%r12,4\),%xmm8
[ ]*[a-f0-9]+: c4 21 7e e6 84 a5 67 ff ff ff vcvtdq2pd -0x99\(%rbp,%r12,4\),%ymm8
[ ]*[a-f0-9]+: c4 21 7d 5a 84 a5 67 ff ff ff vcvtpd2psy -0x99\(%rbp,%r12,4\),%xmm8
[ ]*[a-f0-9]+: c4 21 39 e0 bc a5 67 ff ff ff vpavgb -0x99\(%rbp,%r12,4\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 23 79 df 84 a5 67 ff ff ff 64 vaeskeygenassist \$0x64,-0x99\(%rbp,%r12,4\),%xmm8
-[ ]*[a-f0-9]+: c4 23 79 14 84 a5 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rbp,%r12,4\)
+[ ]*[a-f0-9]+: c4 23 79 df 84 a5 67 ff ff ff 07 vaeskeygenassist \$0x7,-0x99\(%rbp,%r12,4\),%xmm8
+[ ]*[a-f0-9]+: c4 23 79 14 84 a5 67 ff ff ff 07 vpextrb \$0x7,%xmm8,-0x99\(%rbp,%r12,4\)
[ ]*[a-f0-9]+: c4 21 3b 2a bc a5 67 ff ff ff vcvtsi2sdl -0x99\(%rbp,%r12,4\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 23 19 4a b4 a5 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rbp,%r12,4\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 23 39 20 bc a5 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rbp,%r12,4\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 23 39 20 bc a5 67 ff ff ff 07 vpinsrb \$0x7,-0x99\(%rbp,%r12,4\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 21 7d 6f 84 a5 67 ff ff ff vmovdqa -0x99\(%rbp,%r12,4\),%ymm8
[ ]*[a-f0-9]+: c4 21 7d 7f 84 a5 67 ff ff ff vmovdqa %ymm8,-0x99\(%rbp,%r12,4\)
[ ]*[a-f0-9]+: c4 22 3d 0d bc a5 67 ff ff ff vpermilpd -0x99\(%rbp,%r12,4\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 23 7d 09 84 a5 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rbp,%r12,4\),%ymm8
-[ ]*[a-f0-9]+: c4 23 7d 19 84 a5 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rbp,%r12,4\)
-[ ]*[a-f0-9]+: c4 23 3d 06 bc a5 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rbp,%r12,4\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 23 7d 09 84 a5 67 ff ff ff 07 vroundpd \$0x7,-0x99\(%rbp,%r12,4\),%ymm8
+[ ]*[a-f0-9]+: c4 23 7d 19 84 a5 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,-0x99\(%rbp,%r12,4\)
+[ ]*[a-f0-9]+: c4 23 3d 06 bc a5 67 ff ff ff 07 vperm2f128 \$0x7,-0x99\(%rbp,%r12,4\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 23 1d 4b b4 a5 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rbp,%r12,4\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c4 a1 78 ae 94 2c 67 ff ff ff vldmxcsr -0x99\(%rsp,%r13,1\)
[ ]*[a-f0-9]+: c4 21 79 6f 84 2c 67 ff ff ff vmovdqa -0x99\(%rsp,%r13,1\),%xmm8
[ ]*[a-f0-9]+: c4 21 7e e6 84 2c 67 ff ff ff vcvtdq2pd -0x99\(%rsp,%r13,1\),%ymm8
[ ]*[a-f0-9]+: c4 21 7d 5a 84 2c 67 ff ff ff vcvtpd2psy -0x99\(%rsp,%r13,1\),%xmm8
[ ]*[a-f0-9]+: c4 21 39 e0 bc 2c 67 ff ff ff vpavgb -0x99\(%rsp,%r13,1\),%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 23 79 df 84 2c 67 ff ff ff 64 vaeskeygenassist \$0x64,-0x99\(%rsp,%r13,1\),%xmm8
-[ ]*[a-f0-9]+: c4 23 79 14 84 2c 67 ff ff ff 64 vpextrb \$0x64,%xmm8,-0x99\(%rsp,%r13,1\)
+[ ]*[a-f0-9]+: c4 23 79 df 84 2c 67 ff ff ff 07 vaeskeygenassist \$0x7,-0x99\(%rsp,%r13,1\),%xmm8
+[ ]*[a-f0-9]+: c4 23 79 14 84 2c 67 ff ff ff 07 vpextrb \$0x7,%xmm8,-0x99\(%rsp,%r13,1\)
[ ]*[a-f0-9]+: c4 21 3b 2a bc 2c 67 ff ff ff vcvtsi2sdl -0x99\(%rsp,%r13,1\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 23 19 4a b4 2c 67 ff ff ff 80 vblendvps %xmm8,-0x99\(%rsp,%r13,1\),%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 23 39 20 bc 2c 67 ff ff ff 64 vpinsrb \$0x64,-0x99\(%rsp,%r13,1\),%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 23 39 20 bc 2c 67 ff ff ff 07 vpinsrb \$0x7,-0x99\(%rsp,%r13,1\),%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 21 7d 6f 84 2c 67 ff ff ff vmovdqa -0x99\(%rsp,%r13,1\),%ymm8
[ ]*[a-f0-9]+: c4 21 7d 7f 84 2c 67 ff ff ff vmovdqa %ymm8,-0x99\(%rsp,%r13,1\)
[ ]*[a-f0-9]+: c4 22 3d 0d bc 2c 67 ff ff ff vpermilpd -0x99\(%rsp,%r13,1\),%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 23 7d 09 84 2c 67 ff ff ff 64 vroundpd \$0x64,-0x99\(%rsp,%r13,1\),%ymm8
-[ ]*[a-f0-9]+: c4 23 7d 19 84 2c 67 ff ff ff 64 vextractf128 \$0x64,%ymm8,-0x99\(%rsp,%r13,1\)
-[ ]*[a-f0-9]+: c4 23 3d 06 bc 2c 67 ff ff ff 64 vperm2f128 \$0x64,-0x99\(%rsp,%r13,1\),%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 23 7d 09 84 2c 67 ff ff ff 07 vroundpd \$0x7,-0x99\(%rsp,%r13,1\),%ymm8
+[ ]*[a-f0-9]+: c4 23 7d 19 84 2c 67 ff ff ff 07 vextractf128 \$0x7,%ymm8,-0x99\(%rsp,%r13,1\)
+[ ]*[a-f0-9]+: c4 23 3d 06 bc 2c 67 ff ff ff 07 vperm2f128 \$0x7,-0x99\(%rsp,%r13,1\),%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 23 1d 4b b4 2c 67 ff ff ff 80 vblendvpd %ymm8,-0x99\(%rsp,%r13,1\),%ymm12,%ymm14
[ ]*[a-f0-9]+: c4 41 79 50 c0 vmovmskpd %xmm8,%r8d
-[ ]*[a-f0-9]+: c4 c1 01 72 f0 64 vpslld \$0x64,%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 c1 01 72 f0 07 vpslld \$0x7,%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 41 7c 50 c0 vmovmskps %ymm8,%r8d
[ ]*[a-f0-9]+: c4 41 79 6f f8 vmovdqa %xmm8,%xmm15
[ ]*[a-f0-9]+: c4 41 79 7e c0 vmovd %xmm8,%r8d
[ ]*[a-f0-9]+: c4 41 7b 2d c0 vcvtsd2si %xmm8,%r8d
[ ]*[a-f0-9]+: c4 41 7e e6 c0 vcvtdq2pd %xmm8,%ymm8
[ ]*[a-f0-9]+: c4 41 7d 5a c0 vcvtpd2ps %ymm8,%xmm8
-[ ]*[a-f0-9]+: c4 43 79 df f8 64 vaeskeygenassist \$0x64,%xmm8,%xmm15
-[ ]*[a-f0-9]+: c4 43 79 14 c0 64 vpextrb \$0x64,%xmm8,%r8d
+[ ]*[a-f0-9]+: c4 43 79 df f8 07 vaeskeygenassist \$0x7,%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 43 79 14 c0 07 vpextrb \$0x7,%xmm8,%r8d
[ ]*[a-f0-9]+: c4 41 3b 2a f8 vcvtsi2sd %r8d,%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 43 19 4a f0 80 vblendvps %xmm8,%xmm8,%xmm12,%xmm14
-[ ]*[a-f0-9]+: c4 43 39 20 f8 64 vpinsrb \$0x64,%r8d,%xmm8,%xmm15
+[ ]*[a-f0-9]+: c4 43 39 20 f8 07 vpinsrb \$0x7,%r8d,%xmm8,%xmm15
[ ]*[a-f0-9]+: c4 41 7d 6f f8 vmovdqa %ymm8,%ymm15
[ ]*[a-f0-9]+: c4 42 05 0d e0 vpermilpd %ymm8,%ymm15,%ymm12
-[ ]*[a-f0-9]+: c4 43 7d 09 f8 64 vroundpd \$0x64,%ymm8,%ymm15
-[ ]*[a-f0-9]+: c4 43 7d 19 c0 64 vextractf128 \$0x64,%ymm8,%xmm8
-[ ]*[a-f0-9]+: c4 43 05 06 e0 64 vperm2f128 \$0x64,%ymm8,%ymm15,%ymm12
+[ ]*[a-f0-9]+: c4 43 7d 09 f8 07 vroundpd \$0x7,%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 43 7d 19 c0 07 vextractf128 \$0x7,%ymm8,%xmm8
+[ ]*[a-f0-9]+: c4 43 05 06 e0 07 vperm2f128 \$0x7,%ymm8,%ymm15,%ymm12
[ ]*[a-f0-9]+: c4 43 1d 4b f7 80 vblendvpd %ymm8,%ymm15,%ymm12,%ymm14
-[ ]*[a-f0-9]+: c4 43 3d 18 f8 64 vinsertf128 \$0x64,%xmm8,%ymm8,%ymm15
+[ ]*[a-f0-9]+: c4 43 3d 18 f8 07 vinsertf128 \$0x7,%xmm8,%ymm8,%ymm15
[ ]*[a-f0-9]+: c4 61 fb 2d 01 vcvtsd2si \(%rcx\),%r8
[ ]*[a-f0-9]+: c4 43 79 17 c0 0a vextractps \$0xa,%xmm8,%r8d
[ ]*[a-f0-9]+: c4 61 fa 2d 01 vcvtss2si \(%rcx\),%r8
-[ ]*[a-f0-9]+: c4 41 01 c4 c0 64 vpinsrw \$0x64,%r8d,%xmm15,%xmm8
+[ ]*[a-f0-9]+: c4 41 01 c4 c0 07 vpinsrw \$0x7,%r8d,%xmm15,%xmm8
#pass
vmaskmovps %ymm4,%ymm6,(%rcx)
# Tests for op imm8, ymm/mem256, ymm
- vpermilpd $100,%ymm6,%ymm2
- vpermilpd $100,(%rcx),%ymm6
- vpermilps $100,%ymm6,%ymm2
- vpermilps $100,(%rcx),%ymm6
- vroundpd $100,%ymm6,%ymm2
- vroundpd $100,(%rcx),%ymm6
- vroundps $100,%ymm6,%ymm2
- vroundps $100,(%rcx),%ymm6
+ vpermilpd $7,%ymm6,%ymm2
+ vpermilpd $7,(%rcx),%ymm6
+ vpermilps $7,%ymm6,%ymm2
+ vpermilps $7,(%rcx),%ymm6
+ vroundpd $7,%ymm6,%ymm2
+ vroundpd $7,(%rcx),%ymm6
+ vroundps $7,%ymm6,%ymm2
+ vroundps $7,(%rcx),%ymm6
# Tests for op ymm/mem256, ymm, ymm
vaddpd %ymm4,%ymm6,%ymm2
vcvttpd2dqy (%rcx),%xmm4
# Tests for op ymm/mem256, ymm
- vcvtdq2ps %ymm4,%ymm4
+ vcvtdq2ps %ymm4,%ymm6
vcvtdq2ps (%rcx),%ymm4
- vcvtps2dq %ymm4,%ymm4
+ vcvtps2dq %ymm4,%ymm6
vcvtps2dq (%rcx),%ymm4
- vcvttps2dq %ymm4,%ymm4
+ vcvttps2dq %ymm4,%ymm6
vcvttps2dq (%rcx),%ymm4
- vmovapd %ymm4,%ymm4
+ vmovapd %ymm4,%ymm6
vmovapd (%rcx),%ymm4
- vmovaps %ymm4,%ymm4
+ vmovaps %ymm4,%ymm6
vmovaps (%rcx),%ymm4
- vmovdqa %ymm4,%ymm4
+ vmovdqa %ymm4,%ymm6
vmovdqa (%rcx),%ymm4
- vmovdqu %ymm4,%ymm4
+ vmovdqu %ymm4,%ymm6
vmovdqu (%rcx),%ymm4
- vmovddup %ymm4,%ymm4
+ vmovddup %ymm4,%ymm6
vmovddup (%rcx),%ymm4
- vmovshdup %ymm4,%ymm4
+ vmovshdup %ymm4,%ymm6
vmovshdup (%rcx),%ymm4
- vmovsldup %ymm4,%ymm4
+ vmovsldup %ymm4,%ymm6
vmovsldup (%rcx),%ymm4
- vmovupd %ymm4,%ymm4
+ vmovupd %ymm4,%ymm6
vmovupd (%rcx),%ymm4
- vmovups %ymm4,%ymm4
+ vmovups %ymm4,%ymm6
vmovups (%rcx),%ymm4
- vptest %ymm4,%ymm4
+ vptest %ymm4,%ymm6
vptest (%rcx),%ymm4
- vrcpps %ymm4,%ymm4
+ vrcpps %ymm4,%ymm6
vrcpps (%rcx),%ymm4
- vrsqrtps %ymm4,%ymm4
+ vrsqrtps %ymm4,%ymm6
vrsqrtps (%rcx),%ymm4
- vsqrtpd %ymm4,%ymm4
+ vsqrtpd %ymm4,%ymm6
vsqrtpd (%rcx),%ymm4
- vsqrtps %ymm4,%ymm4
+ vsqrtps %ymm4,%ymm6
vsqrtps (%rcx),%ymm4
- vtestpd %ymm4,%ymm4
+ vtestpd %ymm4,%ymm6
vtestpd (%rcx),%ymm4
- vtestps %ymm4,%ymm4
+ vtestps %ymm4,%ymm6
vtestps (%rcx),%ymm4
# Tests for op mem256, ymm
vlddqu (%rcx),%ymm4
# Tests for op imm8, ymm/mem256, ymm, ymm
- vblendpd $100,%ymm4,%ymm6,%ymm2
- vblendpd $100,(%rcx),%ymm6,%ymm2
- vblendps $100,%ymm4,%ymm6,%ymm2
- vblendps $100,(%rcx),%ymm6,%ymm2
- vcmppd $100,%ymm4,%ymm6,%ymm2
- vcmppd $100,(%rcx),%ymm6,%ymm2
- vcmpps $100,%ymm4,%ymm6,%ymm2
- vcmpps $100,(%rcx),%ymm6,%ymm2
- vdpps $100,%ymm4,%ymm6,%ymm2
- vdpps $100,(%rcx),%ymm6,%ymm2
- vperm2f128 $100,%ymm4,%ymm6,%ymm2
- vperm2f128 $100,(%rcx),%ymm6,%ymm2
- vshufpd $100,%ymm4,%ymm6,%ymm2
- vshufpd $100,(%rcx),%ymm6,%ymm2
- vshufps $100,%ymm4,%ymm6,%ymm2
- vshufps $100,(%rcx),%ymm6,%ymm2
+ vblendpd $7,%ymm4,%ymm6,%ymm2
+ vblendpd $7,(%rcx),%ymm6,%ymm2
+ vblendps $7,%ymm4,%ymm6,%ymm2
+ vblendps $7,(%rcx),%ymm6,%ymm2
+ vcmppd $7,%ymm4,%ymm6,%ymm2
+ vcmppd $7,(%rcx),%ymm6,%ymm2
+ vcmpps $7,%ymm4,%ymm6,%ymm2
+ vcmpps $7,(%rcx),%ymm6,%ymm2
+ vdpps $7,%ymm4,%ymm6,%ymm2
+ vdpps $7,(%rcx),%ymm6,%ymm2
+ vperm2f128 $7,%ymm4,%ymm6,%ymm2
+ vperm2f128 $7,(%rcx),%ymm6,%ymm2
+ vshufpd $7,%ymm4,%ymm6,%ymm2
+ vshufpd $7,(%rcx),%ymm6,%ymm2
+ vshufps $7,%ymm4,%ymm6,%ymm2
+ vshufps $7,(%rcx),%ymm6,%ymm2
# Tests for op ymm, ymm/mem256, ymm, ymm
vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
vblendvps %ymm4,%ymm6,%ymm2,%ymm7
vblendvps %ymm4,(%rcx),%ymm2,%ymm7
-# Tests for op ymm/mem256, ymm, ymm, ymm
-# Tests for op ymm, ymm/mem256, ymm, ymm
- vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
- vfmaddpd (%rcx),%ymm6,%ymm2,%ymm7
- vfmaddps %ymm4,%ymm6,%ymm2,%ymm7
- vfmaddps (%rcx),%ymm6,%ymm2,%ymm7
- vfmaddsubpd %ymm4,%ymm6,%ymm2,%ymm7
- vfmaddsubpd (%rcx),%ymm6,%ymm2,%ymm7
- vfmaddsubps %ymm4,%ymm6,%ymm2,%ymm7
- vfmaddsubps (%rcx),%ymm6,%ymm2,%ymm7
- vfmsubaddpd %ymm4,%ymm6,%ymm2,%ymm7
- vfmsubaddpd (%rcx),%ymm6,%ymm2,%ymm7
- vfmsubaddps %ymm4,%ymm6,%ymm2,%ymm7
- vfmsubaddps (%rcx),%ymm6,%ymm2,%ymm7
- vfmsubpd %ymm4,%ymm6,%ymm2,%ymm7
- vfmsubpd (%rcx),%ymm6,%ymm2,%ymm7
- vfmsubps %ymm4,%ymm6,%ymm2,%ymm7
- vfmsubps (%rcx),%ymm6,%ymm2,%ymm7
- vfnmaddpd %ymm4,%ymm6,%ymm2,%ymm7
- vfnmaddpd (%rcx),%ymm6,%ymm2,%ymm7
- vfnmaddps %ymm4,%ymm6,%ymm2,%ymm7
- vfnmaddps (%rcx),%ymm6,%ymm2,%ymm7
- vfnmsubpd %ymm4,%ymm6,%ymm2,%ymm7
- vfnmsubpd (%rcx),%ymm6,%ymm2,%ymm7
- vfnmsubps %ymm4,%ymm6,%ymm2,%ymm7
- vfnmsubps (%rcx),%ymm6,%ymm2,%ymm7
- vpermilmo2pd %ymm4,%ymm6,%ymm2,%ymm7
- vpermilmo2pd (%rcx),%ymm6,%ymm2,%ymm7
- vpermilmz2pd %ymm4,%ymm6,%ymm2,%ymm7
- vpermilmz2pd (%rcx),%ymm6,%ymm2,%ymm7
- vpermiltd2pd %ymm4,%ymm6,%ymm2,%ymm7
- vpermiltd2pd (%rcx),%ymm6,%ymm2,%ymm7
- vpermilmo2ps %ymm4,%ymm6,%ymm2,%ymm7
- vpermilmo2ps (%rcx),%ymm6,%ymm2,%ymm7
- vpermilmz2ps %ymm4,%ymm6,%ymm2,%ymm7
- vpermilmz2ps (%rcx),%ymm6,%ymm2,%ymm7
- vpermiltd2ps %ymm4,%ymm6,%ymm2,%ymm7
- vpermiltd2ps (%rcx),%ymm6,%ymm2,%ymm7
-
-# Tests for op imm4, ymm/mem256, ymm, ymm, ymm
-# Tests for op imm4, ymm, ymm/mem256, ymm, ymm
- vpermil2pd $10,%ymm4,%ymm6,%ymm2,%ymm7
- vpermil2pd $10,(%rcx),%ymm6,%ymm2,%ymm7
- vpermil2ps $10,%ymm4,%ymm6,%ymm2,%ymm7
- vpermil2ps $10,(%rcx),%ymm6,%ymm2,%ymm7
-
# Tests for op imm8, xmm/mem128, ymm, ymm
- vinsertf128 $100,%xmm4,%ymm4,%ymm6
- vinsertf128 $100,(%rcx),%ymm4,%ymm6
+ vinsertf128 $7,%xmm4,%ymm4,%ymm6
+ vinsertf128 $7,(%rcx),%ymm4,%ymm6
# Tests for op imm8, ymm, xmm/mem128
- vextractf128 $100,%ymm4,%xmm4
- vextractf128 $100,%ymm4,(%rcx)
+ vextractf128 $7,%ymm4,%xmm4
+ vextractf128 $7,%ymm4,(%rcx)
# Tests for op mem128, ymm
vbroadcastf128 (%rcx),%ymm4
vmaskmovpd (%rcx),%xmm4,%xmm6
# Tests for op imm8, xmm/mem128, xmm
- vaeskeygenassist $100,%xmm4,%xmm6
- vaeskeygenassist $100,(%rcx),%xmm6
- vpcmpestri $100,%xmm4,%xmm6
- vpcmpestri $100,(%rcx),%xmm6
- vpcmpestrm $100,%xmm4,%xmm6
- vpcmpestrm $100,(%rcx),%xmm6
- vpcmpistri $100,%xmm4,%xmm6
- vpcmpistri $100,(%rcx),%xmm6
- vpcmpistrm $100,%xmm4,%xmm6
- vpcmpistrm $100,(%rcx),%xmm6
- vpermilpd $100,%xmm4,%xmm6
- vpermilpd $100,(%rcx),%xmm6
- vpermilps $100,%xmm4,%xmm6
- vpermilps $100,(%rcx),%xmm6
- vpshufd $100,%xmm4,%xmm6
- vpshufd $100,(%rcx),%xmm6
- vpshufhw $100,%xmm4,%xmm6
- vpshufhw $100,(%rcx),%xmm6
- vpshuflw $100,%xmm4,%xmm6
- vpshuflw $100,(%rcx),%xmm6
- vroundpd $100,%xmm4,%xmm6
- vroundpd $100,(%rcx),%xmm6
- vroundps $100,%xmm4,%xmm6
- vroundps $100,(%rcx),%xmm6
+ vaeskeygenassist $7,%xmm4,%xmm6
+ vaeskeygenassist $7,(%rcx),%xmm6
+ vpcmpestri $7,%xmm4,%xmm6
+ vpcmpestri $7,(%rcx),%xmm6
+ vpcmpestrm $7,%xmm4,%xmm6
+ vpcmpestrm $7,(%rcx),%xmm6
+ vpcmpistri $7,%xmm4,%xmm6
+ vpcmpistri $7,(%rcx),%xmm6
+ vpcmpistrm $7,%xmm4,%xmm6
+ vpcmpistrm $7,(%rcx),%xmm6
+ vpermilpd $7,%xmm4,%xmm6
+ vpermilpd $7,(%rcx),%xmm6
+ vpermilps $7,%xmm4,%xmm6
+ vpermilps $7,(%rcx),%xmm6
+ vpshufd $7,%xmm4,%xmm6
+ vpshufd $7,(%rcx),%xmm6
+ vpshufhw $7,%xmm4,%xmm6
+ vpshufhw $7,(%rcx),%xmm6
+ vpshuflw $7,%xmm4,%xmm6
+ vpshuflw $7,(%rcx),%xmm6
+ vroundpd $7,%xmm4,%xmm6
+ vroundpd $7,(%rcx),%xmm6
+ vroundps $7,%xmm4,%xmm6
+ vroundps $7,(%rcx),%xmm6
# Tests for op xmm, xmm, mem128
vmaskmovps %xmm4,%xmm6,(%rcx)
vmaskmovpd %xmm4,%xmm6,(%rcx)
# Tests for op imm8, xmm/mem128, xmm, xmm
- vblendpd $100,%xmm4,%xmm6,%xmm2
- vblendpd $100,(%rcx),%xmm6,%xmm2
- vblendps $100,%xmm4,%xmm6,%xmm2
- vblendps $100,(%rcx),%xmm6,%xmm2
- vcmppd $100,%xmm4,%xmm6,%xmm2
- vcmppd $100,(%rcx),%xmm6,%xmm2
- vcmpps $100,%xmm4,%xmm6,%xmm2
- vcmpps $100,(%rcx),%xmm6,%xmm2
- vdppd $100,%xmm4,%xmm6,%xmm2
- vdppd $100,(%rcx),%xmm6,%xmm2
- vdpps $100,%xmm4,%xmm6,%xmm2
- vdpps $100,(%rcx),%xmm6,%xmm2
- vmpsadbw $100,%xmm4,%xmm6,%xmm2
- vmpsadbw $100,(%rcx),%xmm6,%xmm2
- vpalignr $100,%xmm4,%xmm6,%xmm2
- vpalignr $100,(%rcx),%xmm6,%xmm2
- vpblendw $100,%xmm4,%xmm6,%xmm2
- vpblendw $100,(%rcx),%xmm6,%xmm2
- vshufpd $100,%xmm4,%xmm6,%xmm2
- vshufpd $100,(%rcx),%xmm6,%xmm2
- vshufps $100,%xmm4,%xmm6,%xmm2
- vshufps $100,(%rcx),%xmm6,%xmm2
+ vblendpd $7,%xmm4,%xmm6,%xmm2
+ vblendpd $7,(%rcx),%xmm6,%xmm2
+ vblendps $7,%xmm4,%xmm6,%xmm2
+ vblendps $7,(%rcx),%xmm6,%xmm2
+ vcmppd $7,%xmm4,%xmm6,%xmm2
+ vcmppd $7,(%rcx),%xmm6,%xmm2
+ vcmpps $7,%xmm4,%xmm6,%xmm2
+ vcmpps $7,(%rcx),%xmm6,%xmm2
+ vdppd $7,%xmm4,%xmm6,%xmm2
+ vdppd $7,(%rcx),%xmm6,%xmm2
+ vdpps $7,%xmm4,%xmm6,%xmm2
+ vdpps $7,(%rcx),%xmm6,%xmm2
+ vmpsadbw $7,%xmm4,%xmm6,%xmm2
+ vmpsadbw $7,(%rcx),%xmm6,%xmm2
+ vpalignr $7,%xmm4,%xmm6,%xmm2
+ vpalignr $7,(%rcx),%xmm6,%xmm2
+ vpblendw $7,%xmm4,%xmm6,%xmm2
+ vpblendw $7,(%rcx),%xmm6,%xmm2
+ vshufpd $7,%xmm4,%xmm6,%xmm2
+ vshufpd $7,(%rcx),%xmm6,%xmm2
+ vshufps $7,%xmm4,%xmm6,%xmm2
+ vshufps $7,(%rcx),%xmm6,%xmm2
# Tests for op xmm, xmm/mem128, xmm, xmm
vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
vpblendvb %xmm4,%xmm6,%xmm2,%xmm7
vpblendvb %xmm4,(%rcx),%xmm2,%xmm7
-# Tests for op xmm/mem128, xmm, xmm, xmm
-# Tests for op xmm, xmm/mem128, xmm, xmm
- vfmaddpd %xmm4,%xmm6,%xmm2,%xmm7
- vfmaddpd (%rcx),%xmm6,%xmm2,%xmm7
- vfmaddpd %xmm4,(%rcx),%xmm2,%xmm7
- vfmaddps %xmm4,%xmm6,%xmm2,%xmm7
- vfmaddps (%rcx),%xmm6,%xmm2,%xmm7
- vfmaddps %xmm4,(%rcx),%xmm2,%xmm7
- vfmaddsubpd %xmm4,%xmm6,%xmm2,%xmm7
- vfmaddsubpd (%rcx),%xmm6,%xmm2,%xmm7
- vfmaddsubpd %xmm4,(%rcx),%xmm2,%xmm7
- vfmaddsubps %xmm4,%xmm6,%xmm2,%xmm7
- vfmaddsubps (%rcx),%xmm6,%xmm2,%xmm7
- vfmaddsubps %xmm4,(%rcx),%xmm2,%xmm7
- vfmsubaddpd %xmm4,%xmm6,%xmm2,%xmm7
- vfmsubaddpd (%rcx),%xmm6,%xmm2,%xmm7
- vfmsubaddpd %xmm4,(%rcx),%xmm2,%xmm7
- vfmsubaddps %xmm4,%xmm6,%xmm2,%xmm7
- vfmsubaddps (%rcx),%xmm6,%xmm2,%xmm7
- vfmsubaddps %xmm4,(%rcx),%xmm2,%xmm7
- vfmsubpd %xmm4,%xmm6,%xmm2,%xmm7
- vfmsubpd (%rcx),%xmm6,%xmm2,%xmm7
- vfmsubpd %xmm4,(%rcx),%xmm2,%xmm7
- vfmsubps %xmm4,%xmm6,%xmm2,%xmm7
- vfmsubps (%rcx),%xmm6,%xmm2,%xmm7
- vfmsubps %xmm4,(%rcx),%xmm2,%xmm7
- vfnmaddpd %xmm4,%xmm6,%xmm2,%xmm7
- vfnmaddpd (%rcx),%xmm6,%xmm2,%xmm7
- vfnmaddpd %xmm4,(%rcx),%xmm2,%xmm7
- vfnmaddps %xmm4,%xmm6,%xmm2,%xmm7
- vfnmaddps (%rcx),%xmm6,%xmm2,%xmm7
- vfnmaddps %xmm4,(%rcx),%xmm2,%xmm7
- vfnmsubpd %xmm4,%xmm6,%xmm2,%xmm7
- vfnmsubpd (%rcx),%xmm6,%xmm2,%xmm7
- vfnmsubpd %xmm4,(%rcx),%xmm2,%xmm7
- vfnmsubps %xmm4,%xmm6,%xmm2,%xmm7
- vfnmsubps (%rcx),%xmm6,%xmm2,%xmm7
- vfnmsubps %xmm4,(%rcx),%xmm2,%xmm7
- vpermilmo2pd %xmm4,%xmm6,%xmm2,%xmm7
- vpermilmo2pd (%rcx),%xmm6,%xmm2,%xmm7
- vpermilmo2pd %xmm4,(%rcx),%xmm2,%xmm7
- vpermilmz2pd %xmm4,%xmm6,%xmm2,%xmm7
- vpermilmz2pd (%rcx),%xmm6,%xmm2,%xmm7
- vpermilmz2pd %xmm4,(%rcx),%xmm2,%xmm7
- vpermiltd2pd %xmm4,%xmm6,%xmm2,%xmm7
- vpermiltd2pd (%rcx),%xmm6,%xmm2,%xmm7
- vpermiltd2pd %xmm4,(%rcx),%xmm2,%xmm7
- vpermilmo2ps %xmm4,%xmm6,%xmm2,%xmm7
- vpermilmo2ps (%rcx),%xmm6,%xmm2,%xmm7
- vpermilmo2ps %xmm4,(%rcx),%xmm2,%xmm7
- vpermilmz2ps %xmm4,%xmm6,%xmm2,%xmm7
- vpermilmz2ps (%rcx),%xmm6,%xmm2,%xmm7
- vpermilmz2ps %xmm4,(%rcx),%xmm2,%xmm7
- vpermiltd2ps %xmm4,%xmm6,%xmm2,%xmm7
- vpermiltd2ps (%rcx),%xmm6,%xmm2,%xmm7
- vpermiltd2ps %xmm4,(%rcx),%xmm2,%xmm7
-
-# Tests for op imm4, xmm/mem128, xmm, xmm, xmm
-# Tests for op imm4, xmm, xmm/mem128, xmm, xmm
- vpermil2pd $10,%xmm4,%xmm6,%xmm2,%xmm7
- vpermil2pd $10,(%rcx),%xmm6,%xmm2,%xmm7
- vpermil2pd $10,%xmm4,(%rcx),%xmm2,%xmm7
- vpermil2ps $10,%xmm4,%xmm6,%xmm2,%xmm7
- vpermil2ps $10,(%rcx),%xmm6,%xmm2,%xmm7
- vpermil2ps $10,%xmm4,(%rcx),%xmm2,%xmm7
-
# Tests for op mem64, ymm
vbroadcastsd (%rcx),%ymm4
vcvtsi2ssq (%rcx),%xmm4,%xmm6
# Tests for op imm8, regq/mem64, xmm, xmm
- vpinsrq $100,%rcx,%xmm4,%xmm6
- vpinsrq $100,(%rcx),%xmm4,%xmm6
+ vpinsrq $7,%rcx,%xmm4,%xmm6
+ vpinsrq $7,(%rcx),%xmm4,%xmm6
# Testsf for op imm8, xmm, regq/mem64
- vpextrq $100,%xmm4,%rcx
- vpextrq $100,%xmm4,(%rcx)
+ vpextrq $7,%xmm4,%rcx
+ vpextrq $7,%xmm4,(%rcx)
# Tests for op mem64, xmm, xmm
vmovlpd (%rcx),%xmm4,%xmm6
vmovhps (%rcx),%xmm4,%xmm6
# Tests for op imm8, xmm/mem64, xmm, xmm
- vcmpsd $100,%xmm4,%xmm6,%xmm2
- vcmpsd $100,(%rcx),%xmm6,%xmm2
- vroundsd $100,%xmm4,%xmm6,%xmm2
- vroundsd $100,(%rcx),%xmm6,%xmm2
-
-# Tests for op xmm/mem64, xmm, xmm, xmm
-# Tests for op xmm, xmm/mem64, xmm, xmm
- vfmaddsd %xmm4,%xmm6,%xmm2,%xmm7
- vfmaddsd (%rcx),%xmm6,%xmm2,%xmm7
- vfmaddsd %xmm4,(%rcx),%xmm2,%xmm7
- vfmsubsd %xmm4,%xmm6,%xmm2,%xmm7
- vfmsubsd (%rcx),%xmm6,%xmm2,%xmm7
- vfmsubsd %xmm4,(%rcx),%xmm2,%xmm7
- vfnmaddsd %xmm4,%xmm6,%xmm2,%xmm7
- vfnmaddsd (%rcx),%xmm6,%xmm2,%xmm7
- vfnmaddsd %xmm4,(%rcx),%xmm2,%xmm7
- vfnmsubsd %xmm4,%xmm6,%xmm2,%xmm7
- vfnmsubsd (%rcx),%xmm6,%xmm2,%xmm7
- vfnmsubsd %xmm4,(%rcx),%xmm2,%xmm7
+ vcmpsd $7,%xmm4,%xmm6,%xmm2
+ vcmpsd $7,(%rcx),%xmm6,%xmm2
+ vroundsd $7,%xmm4,%xmm6,%xmm2
+ vroundsd $7,(%rcx),%xmm6,%xmm2
# Tests for op xmm/mem64, xmm, xmm
vaddsd %xmm4,%xmm6,%xmm2
vcmptrue_ussd %xmm4,%xmm6,%xmm2
vcmptrue_ussd (%rcx),%xmm6,%xmm2
+# Tests for op mem64
+ vldmxcsr (%rcx)
+ vstmxcsr (%rcx)
+
# Tests for op xmm/mem32, xmm, xmm
vaddss %xmm4,%xmm6,%xmm2
vaddss (%rcx),%xmm6,%xmm2
vpmovmskb %xmm4,%rcx
# Tests for op imm8, xmm, regq/mem32
- vextractps $100,%xmm4,%rcx
- vextractps $100,%xmm4,(%rcx)
+ vextractps $7,%xmm4,%rcx
+ vextractps $7,%xmm4,(%rcx)
+
# Tests for op imm8, xmm, regl/mem32
- vpextrd $100,%xmm4,%ecx
- vpextrd $100,%xmm4,(%rcx)
- vextractps $100,%xmm4,%ecx
- vextractps $100,%xmm4,(%rcx)
+ vpextrd $7,%xmm4,%ecx
+ vpextrd $7,%xmm4,(%rcx)
+ vextractps $7,%xmm4,%ecx
+ vextractps $7,%xmm4,(%rcx)
# Tests for op regl/mem32, xmm, xmm
vcvtsi2sd %ecx,%xmm4,%xmm6
vcvtsi2ss (%rcx),%xmm4,%xmm6
# Tests for op imm8, xmm/mem32, xmm, xmm
- vcmpss $100,%xmm4,%xmm6,%xmm2
- vcmpss $100,(%rcx),%xmm6,%xmm2
- vinsertps $100,%xmm4,%xmm6,%xmm2
- vinsertps $100,(%rcx),%xmm6,%xmm2
- vroundss $100,%xmm4,%xmm6,%xmm2
- vroundss $100,(%rcx),%xmm6,%xmm2
-
-# Tests for op xmm/mem32, xmm, xmm, xmm
-# Tests for op xmm, xmm/mem32, xmm, xmm
- vfmaddss %xmm4,%xmm6,%xmm2,%xmm7
- vfmaddss (%rcx),%xmm6,%xmm2,%xmm7
- vfmaddss %xmm4,(%rcx),%xmm2,%xmm7
- vfmsubss %xmm4,%xmm6,%xmm2,%xmm7
- vfmsubss (%rcx),%xmm6,%xmm2,%xmm7
- vfmsubss %xmm4,(%rcx),%xmm2,%xmm7
- vfnmaddss %xmm4,%xmm6,%xmm2,%xmm7
- vfnmaddss (%rcx),%xmm6,%xmm2,%xmm7
- vfnmaddss %xmm4,(%rcx),%xmm2,%xmm7
- vfnmsubss %xmm4,%xmm6,%xmm2,%xmm7
- vfnmsubss (%rcx),%xmm6,%xmm2,%xmm7
- vfnmsubss %xmm4,(%rcx),%xmm2,%xmm7
+ vcmpss $7,%xmm4,%xmm6,%xmm2
+ vcmpss $7,(%rcx),%xmm6,%xmm2
+ vinsertps $7,%xmm4,%xmm6,%xmm2
+ vinsertps $7,(%rcx),%xmm6,%xmm2
+ vroundss $7,%xmm4,%xmm6,%xmm2
+ vroundss $7,(%rcx),%xmm6,%xmm2
# Tests for op xmm/m16, xmm
vpmovsxbq %xmm4,%xmm6
vpmovzxbq (%rcx),%xmm4
# Tests for op imm8, xmm, regl/mem16
- vpextrw $100,%xmm4,%ecx
- vpextrw $100,%xmm4,(%rcx)
+ vpextrw $7,%xmm4,%ecx
+ vpextrw $7,%xmm4,(%rcx)
# Tests for op imm8, xmm, regq/mem16
- vpextrw $100,%xmm4,%rcx
- vpextrw $100,%xmm4,(%rcx)
+ vpextrw $7,%xmm4,%rcx
+ vpextrw $7,%xmm4,(%rcx)
# Tests for op imm8, regl/mem16, xmm, xmm
- vpinsrw $100,%ecx,%xmm4,%xmm6
- vpinsrw $100,(%rcx),%xmm4,%xmm6
+ vpinsrw $7,%ecx,%xmm4,%xmm6
+ vpinsrw $7,(%rcx),%xmm4,%xmm6
- vpinsrw $100,%rcx,%xmm4,%xmm6
- vpinsrw $100,(%rcx),%xmm4,%xmm6
+ vpinsrw $7,%rcx,%xmm4,%xmm6
+ vpinsrw $7,(%rcx),%xmm4,%xmm6
# Tests for op imm8, xmm, regl/mem8
- vpextrb $100,%xmm4,%ecx
- vpextrb $100,%xmm4,(%rcx)
+ vpextrb $7,%xmm4,%ecx
+ vpextrb $7,%xmm4,(%rcx)
# Tests for op imm8, regl/mem8, xmm, xmm
- vpinsrb $100,%ecx,%xmm4,%xmm6
- vpinsrb $100,(%rcx),%xmm4,%xmm6
+ vpinsrb $7,%ecx,%xmm4,%xmm6
+ vpinsrb $7,(%rcx),%xmm4,%xmm6
# Tests for op imm8, xmm, regq
- vpextrw $100,%xmm4,%rcx
+ vpextrw $7,%xmm4,%rcx
+
# Tests for op imm8, xmm, regq/mem8
- vpextrb $100,%xmm4,%rcx
- vpextrb $100,%xmm4,(%rcx)
+ vpextrb $7,%xmm4,%rcx
+ vpextrb $7,%xmm4,(%rcx)
# Tests for op imm8, regl/mem8, xmm, xmm
- vpinsrb $100,%ecx,%xmm4,%xmm6
- vpinsrb $100,(%rcx),%xmm4,%xmm6
+ vpinsrb $7,%ecx,%xmm4,%xmm6
+ vpinsrb $7,(%rcx),%xmm4,%xmm6
# Tests for op xmm, xmm
vmaskmovdqu %xmm4,%xmm6
vmovmskpd %xmm4,%ecx
vmovmskps %xmm4,%ecx
vpmovmskb %xmm4,%ecx
+
# Tests for op xmm, xmm, xmm
vmovhlps %xmm4,%xmm6,%xmm2
vmovlhps %xmm4,%xmm6,%xmm2
vmovss %xmm4,%xmm6,%xmm2
# Tests for op imm8, xmm, xmm
- vpslld $100,%xmm4,%xmm6
- vpslldq $100,%xmm4,%xmm6
- vpsllq $100,%xmm4,%xmm6
- vpsllw $100,%xmm4,%xmm6
- vpsrad $100,%xmm4,%xmm6
- vpsraw $100,%xmm4,%xmm6
- vpsrld $100,%xmm4,%xmm6
- vpsrldq $100,%xmm4,%xmm6
- vpsrlq $100,%xmm4,%xmm6
- vpsrlw $100,%xmm4,%xmm6
+ vpslld $7,%xmm4,%xmm6
+ vpslldq $7,%xmm4,%xmm6
+ vpsllq $7,%xmm4,%xmm6
+ vpsllw $7,%xmm4,%xmm6
+ vpsrad $7,%xmm4,%xmm6
+ vpsraw $7,%xmm4,%xmm6
+ vpsrld $7,%xmm4,%xmm6
+ vpsrldq $7,%xmm4,%xmm6
+ vpsrlq $7,%xmm4,%xmm6
+ vpsrlw $7,%xmm4,%xmm6
# Tests for op imm8, xmm, regl
- vpextrw $100,%xmm4,%ecx
+ vpextrw $7,%xmm4,%ecx
# Tests for op ymm, regl
vmovmskpd %ymm4,%ecx
vmovmskpd %ymm4,%rcx
vmovmskps %ymm4,%rcx
-
# Default instructions without suffixes.
vcvtpd2dq %xmm4,%xmm6
vcvtpd2dq %ymm4,%xmm6
vcvtdq2pd 0x12345678,%ymm8
vcvtpd2psy 0x12345678,%xmm8
vpavgb 0x12345678,%xmm8,%xmm15
- vaeskeygenassist $100,0x12345678,%xmm8
- vpextrb $100,%xmm8,0x12345678
+ vaeskeygenassist $7,0x12345678,%xmm8
+ vpextrb $7,%xmm8,0x12345678
vcvtsi2sdl 0x12345678,%xmm8,%xmm15
vblendvps %xmm8,0x12345678,%xmm12,%xmm14
- vpinsrb $100,0x12345678,%xmm8,%xmm15
+ vpinsrb $7,0x12345678,%xmm8,%xmm15
vmovdqa 0x12345678,%ymm8
vmovdqa %ymm8,0x12345678
vpermilpd 0x12345678,%ymm8,%ymm15
- vroundpd $100,0x12345678,%ymm8
- vextractf128 $100,%ymm8,0x12345678
- vperm2f128 $100,0x12345678,%ymm8,%ymm15
+ vroundpd $7,0x12345678,%ymm8
+ vextractf128 $7,%ymm8,0x12345678
+ vperm2f128 $7,0x12345678,%ymm8,%ymm15
vblendvpd %ymm8,0x12345678,%ymm12,%ymm14
vldmxcsr (%rbp)
vmovdqa (%rbp),%xmm8
vcvtdq2pd (%rbp),%ymm8
vcvtpd2psy (%rbp),%xmm8
vpavgb (%rbp),%xmm8,%xmm15
- vaeskeygenassist $100,(%rbp),%xmm8
- vpextrb $100,%xmm8,(%rbp)
+ vaeskeygenassist $7,(%rbp),%xmm8
+ vpextrb $7,%xmm8,(%rbp)
vcvtsi2sdl (%rbp),%xmm8,%xmm15
vblendvps %xmm8,(%rbp),%xmm12,%xmm14
- vpinsrb $100,(%rbp),%xmm8,%xmm15
+ vpinsrb $7,(%rbp),%xmm8,%xmm15
vmovdqa (%rbp),%ymm8
vmovdqa %ymm8,(%rbp)
vpermilpd (%rbp),%ymm8,%ymm15
- vroundpd $100,(%rbp),%ymm8
- vextractf128 $100,%ymm8,(%rbp)
- vperm2f128 $100,(%rbp),%ymm8,%ymm15
+ vroundpd $7,(%rbp),%ymm8
+ vextractf128 $7,%ymm8,(%rbp)
+ vperm2f128 $7,(%rbp),%ymm8,%ymm15
vblendvpd %ymm8,(%rbp),%ymm12,%ymm14
vldmxcsr (%rsp)
vmovdqa (%rsp),%xmm8
vcvtdq2pd (%rsp),%ymm8
vcvtpd2psy (%rsp),%xmm8
vpavgb (%rsp),%xmm8,%xmm15
- vaeskeygenassist $100,(%rsp),%xmm8
- vpextrb $100,%xmm8,(%rsp)
+ vaeskeygenassist $7,(%rsp),%xmm8
+ vpextrb $7,%xmm8,(%rsp)
vcvtsi2sdl (%rsp),%xmm8,%xmm15
vblendvps %xmm8,(%rsp),%xmm12,%xmm14
- vpinsrb $100,(%rsp),%xmm8,%xmm15
+ vpinsrb $7,(%rsp),%xmm8,%xmm15
vmovdqa (%rsp),%ymm8
vmovdqa %ymm8,(%rsp)
vpermilpd (%rsp),%ymm8,%ymm15
- vroundpd $100,(%rsp),%ymm8
- vextractf128 $100,%ymm8,(%rsp)
- vperm2f128 $100,(%rsp),%ymm8,%ymm15
+ vroundpd $7,(%rsp),%ymm8
+ vextractf128 $7,%ymm8,(%rsp)
+ vperm2f128 $7,(%rsp),%ymm8,%ymm15
vblendvpd %ymm8,(%rsp),%ymm12,%ymm14
vldmxcsr 0x99(%rbp)
vmovdqa 0x99(%rbp),%xmm8
vcvtdq2pd 0x99(%rbp),%ymm8
vcvtpd2psy 0x99(%rbp),%xmm8
vpavgb 0x99(%rbp),%xmm8,%xmm15
- vaeskeygenassist $100,0x99(%rbp),%xmm8
- vpextrb $100,%xmm8,0x99(%rbp)
+ vaeskeygenassist $7,0x99(%rbp),%xmm8
+ vpextrb $7,%xmm8,0x99(%rbp)
vcvtsi2sdl 0x99(%rbp),%xmm8,%xmm15
vblendvps %xmm8,0x99(%rbp),%xmm12,%xmm14
- vpinsrb $100,0x99(%rbp),%xmm8,%xmm15
+ vpinsrb $7,0x99(%rbp),%xmm8,%xmm15
vmovdqa 0x99(%rbp),%ymm8
vmovdqa %ymm8,0x99(%rbp)
vpermilpd 0x99(%rbp),%ymm8,%ymm15
- vroundpd $100,0x99(%rbp),%ymm8
- vextractf128 $100,%ymm8,0x99(%rbp)
- vperm2f128 $100,0x99(%rbp),%ymm8,%ymm15
+ vroundpd $7,0x99(%rbp),%ymm8
+ vextractf128 $7,%ymm8,0x99(%rbp)
+ vperm2f128 $7,0x99(%rbp),%ymm8,%ymm15
vblendvpd %ymm8,0x99(%rbp),%ymm12,%ymm14
vldmxcsr 0x99(%r15)
vmovdqa 0x99(%r15),%xmm8
vcvtdq2pd 0x99(%r15),%ymm8
vcvtpd2psy 0x99(%r15),%xmm8
vpavgb 0x99(%r15),%xmm8,%xmm15
- vaeskeygenassist $100,0x99(%r15),%xmm8
- vpextrb $100,%xmm8,0x99(%r15)
+ vaeskeygenassist $7,0x99(%r15),%xmm8
+ vpextrb $7,%xmm8,0x99(%r15)
vcvtsi2sdl 0x99(%r15),%xmm8,%xmm15
vblendvps %xmm8,0x99(%r15),%xmm12,%xmm14
- vpinsrb $100,0x99(%r15),%xmm8,%xmm15
+ vpinsrb $7,0x99(%r15),%xmm8,%xmm15
vmovdqa 0x99(%r15),%ymm8
vmovdqa %ymm8,0x99(%r15)
vpermilpd 0x99(%r15),%ymm8,%ymm15
- vroundpd $100,0x99(%r15),%ymm8
- vextractf128 $100,%ymm8,0x99(%r15)
- vperm2f128 $100,0x99(%r15),%ymm8,%ymm15
+ vroundpd $7,0x99(%r15),%ymm8
+ vextractf128 $7,%ymm8,0x99(%r15)
+ vperm2f128 $7,0x99(%r15),%ymm8,%ymm15
vblendvpd %ymm8,0x99(%r15),%ymm12,%ymm14
vldmxcsr 0x99(%rip)
vmovdqa 0x99(%rip),%xmm8
vcvtdq2pd 0x99(%rip),%ymm8
vcvtpd2psy 0x99(%rip),%xmm8
vpavgb 0x99(%rip),%xmm8,%xmm15
- vaeskeygenassist $100,0x99(%rip),%xmm8
- vpextrb $100,%xmm8,0x99(%rip)
+ vaeskeygenassist $7,0x99(%rip),%xmm8
+ vpextrb $7,%xmm8,0x99(%rip)
vcvtsi2sdl 0x99(%rip),%xmm8,%xmm15
vblendvps %xmm8,0x99(%rip),%xmm12,%xmm14
- vpinsrb $100,0x99(%rip),%xmm8,%xmm15
+ vpinsrb $7,0x99(%rip),%xmm8,%xmm15
vmovdqa 0x99(%rip),%ymm8
vmovdqa %ymm8,0x99(%rip)
vpermilpd 0x99(%rip),%ymm8,%ymm15
- vroundpd $100,0x99(%rip),%ymm8
- vextractf128 $100,%ymm8,0x99(%rip)
- vperm2f128 $100,0x99(%rip),%ymm8,%ymm15
+ vroundpd $7,0x99(%rip),%ymm8
+ vextractf128 $7,%ymm8,0x99(%rip)
+ vperm2f128 $7,0x99(%rip),%ymm8,%ymm15
vblendvpd %ymm8,0x99(%rip),%ymm12,%ymm14
vldmxcsr 0x99(%rsp)
vmovdqa 0x99(%rsp),%xmm8
vcvtdq2pd 0x99(%rsp),%ymm8
vcvtpd2psy 0x99(%rsp),%xmm8
vpavgb 0x99(%rsp),%xmm8,%xmm15
- vaeskeygenassist $100,0x99(%rsp),%xmm8
- vpextrb $100,%xmm8,0x99(%rsp)
+ vaeskeygenassist $7,0x99(%rsp),%xmm8
+ vpextrb $7,%xmm8,0x99(%rsp)
vcvtsi2sdl 0x99(%rsp),%xmm8,%xmm15
vblendvps %xmm8,0x99(%rsp),%xmm12,%xmm14
- vpinsrb $100,0x99(%rsp),%xmm8,%xmm15
+ vpinsrb $7,0x99(%rsp),%xmm8,%xmm15
vmovdqa 0x99(%rsp),%ymm8
vmovdqa %ymm8,0x99(%rsp)
vpermilpd 0x99(%rsp),%ymm8,%ymm15
- vroundpd $100,0x99(%rsp),%ymm8
- vextractf128 $100,%ymm8,0x99(%rsp)
- vperm2f128 $100,0x99(%rsp),%ymm8,%ymm15
+ vroundpd $7,0x99(%rsp),%ymm8
+ vextractf128 $7,%ymm8,0x99(%rsp)
+ vperm2f128 $7,0x99(%rsp),%ymm8,%ymm15
vblendvpd %ymm8,0x99(%rsp),%ymm12,%ymm14
vldmxcsr 0x99(%r12)
vmovdqa 0x99(%r12),%xmm8
vcvtdq2pd 0x99(%r12),%ymm8
vcvtpd2psy 0x99(%r12),%xmm8
vpavgb 0x99(%r12),%xmm8,%xmm15
- vaeskeygenassist $100,0x99(%r12),%xmm8
- vpextrb $100,%xmm8,0x99(%r12)
+ vaeskeygenassist $7,0x99(%r12),%xmm8
+ vpextrb $7,%xmm8,0x99(%r12)
vcvtsi2sdl 0x99(%r12),%xmm8,%xmm15
vblendvps %xmm8,0x99(%r12),%xmm12,%xmm14
- vpinsrb $100,0x99(%r12),%xmm8,%xmm15
+ vpinsrb $7,0x99(%r12),%xmm8,%xmm15
vmovdqa 0x99(%r12),%ymm8
vmovdqa %ymm8,0x99(%r12)
vpermilpd 0x99(%r12),%ymm8,%ymm15
- vroundpd $100,0x99(%r12),%ymm8
- vextractf128 $100,%ymm8,0x99(%r12)
- vperm2f128 $100,0x99(%r12),%ymm8,%ymm15
+ vroundpd $7,0x99(%r12),%ymm8
+ vextractf128 $7,%ymm8,0x99(%r12)
+ vperm2f128 $7,0x99(%r12),%ymm8,%ymm15
vblendvpd %ymm8,0x99(%r12),%ymm12,%ymm14
vldmxcsr -0x99(,%riz)
vmovdqa -0x99(,%riz),%xmm8
vcvtdq2pd -0x99(,%riz),%ymm8
vcvtpd2psy -0x99(,%riz),%xmm8
vpavgb -0x99(,%riz),%xmm8,%xmm15
- vaeskeygenassist $100,-0x99(,%riz),%xmm8
- vpextrb $100,%xmm8,-0x99(,%riz)
+ vaeskeygenassist $7,-0x99(,%riz),%xmm8
+ vpextrb $7,%xmm8,-0x99(,%riz)
vcvtsi2sdl -0x99(,%riz),%xmm8,%xmm15
vblendvps %xmm8,-0x99(,%riz),%xmm12,%xmm14
- vpinsrb $100,-0x99(,%riz),%xmm8,%xmm15
+ vpinsrb $7,-0x99(,%riz),%xmm8,%xmm15
vmovdqa -0x99(,%riz),%ymm8
vmovdqa %ymm8,-0x99(,%riz)
vpermilpd -0x99(,%riz),%ymm8,%ymm15
- vroundpd $100,-0x99(,%riz),%ymm8
- vextractf128 $100,%ymm8,-0x99(,%riz)
- vperm2f128 $100,-0x99(,%riz),%ymm8,%ymm15
+ vroundpd $7,-0x99(,%riz),%ymm8
+ vextractf128 $7,%ymm8,-0x99(,%riz)
+ vperm2f128 $7,-0x99(,%riz),%ymm8,%ymm15
vblendvpd %ymm8,-0x99(,%riz),%ymm12,%ymm14
vldmxcsr -0x99(,%riz,2)
vmovdqa -0x99(,%riz,2),%xmm8
vcvtdq2pd -0x99(,%riz,2),%ymm8
vcvtpd2psy -0x99(,%riz,2),%xmm8
vpavgb -0x99(,%riz,2),%xmm8,%xmm15
- vaeskeygenassist $100,-0x99(,%riz,2),%xmm8
- vpextrb $100,%xmm8,-0x99(,%riz,2)
+ vaeskeygenassist $7,-0x99(,%riz,2),%xmm8
+ vpextrb $7,%xmm8,-0x99(,%riz,2)
vcvtsi2sdl -0x99(,%riz,2),%xmm8,%xmm15
vblendvps %xmm8,-0x99(,%riz,2),%xmm12,%xmm14
- vpinsrb $100,-0x99(,%riz,2),%xmm8,%xmm15
+ vpinsrb $7,-0x99(,%riz,2),%xmm8,%xmm15
vmovdqa -0x99(,%riz,2),%ymm8
vmovdqa %ymm8,-0x99(,%riz,2)
vpermilpd -0x99(,%riz,2),%ymm8,%ymm15
- vroundpd $100,-0x99(,%riz,2),%ymm8
- vextractf128 $100,%ymm8,-0x99(,%riz,2)
- vperm2f128 $100,-0x99(,%riz,2),%ymm8,%ymm15
+ vroundpd $7,-0x99(,%riz,2),%ymm8
+ vextractf128 $7,%ymm8,-0x99(,%riz,2)
+ vperm2f128 $7,-0x99(,%riz,2),%ymm8,%ymm15
vblendvpd %ymm8,-0x99(,%riz,2),%ymm12,%ymm14
vldmxcsr -0x99(%rbx,%riz)
vmovdqa -0x99(%rbx,%riz),%xmm8
vcvtdq2pd -0x99(%rbx,%riz),%ymm8
vcvtpd2psy -0x99(%rbx,%riz),%xmm8
vpavgb -0x99(%rbx,%riz),%xmm8,%xmm15
- vaeskeygenassist $100,-0x99(%rbx,%riz),%xmm8
- vpextrb $100,%xmm8,-0x99(%rbx,%riz)
+ vaeskeygenassist $7,-0x99(%rbx,%riz),%xmm8
+ vpextrb $7,%xmm8,-0x99(%rbx,%riz)
vcvtsi2sdl -0x99(%rbx,%riz),%xmm8,%xmm15
vblendvps %xmm8,-0x99(%rbx,%riz),%xmm12,%xmm14
- vpinsrb $100,-0x99(%rbx,%riz),%xmm8,%xmm15
+ vpinsrb $7,-0x99(%rbx,%riz),%xmm8,%xmm15
vmovdqa -0x99(%rbx,%riz),%ymm8
vmovdqa %ymm8,-0x99(%rbx,%riz)
vpermilpd -0x99(%rbx,%riz),%ymm8,%ymm15
- vroundpd $100,-0x99(%rbx,%riz),%ymm8
- vextractf128 $100,%ymm8,-0x99(%rbx,%riz)
- vperm2f128 $100,-0x99(%rbx,%riz),%ymm8,%ymm15
+ vroundpd $7,-0x99(%rbx,%riz),%ymm8
+ vextractf128 $7,%ymm8,-0x99(%rbx,%riz)
+ vperm2f128 $7,-0x99(%rbx,%riz),%ymm8,%ymm15
vblendvpd %ymm8,-0x99(%rbx,%riz),%ymm12,%ymm14
vldmxcsr -0x99(%rbx,%riz,2)
vmovdqa -0x99(%rbx,%riz,2),%xmm8
vcvtdq2pd -0x99(%rbx,%riz,2),%ymm8
vcvtpd2psy -0x99(%rbx,%riz,2),%xmm8
vpavgb -0x99(%rbx,%riz,2),%xmm8,%xmm15
- vaeskeygenassist $100,-0x99(%rbx,%riz,2),%xmm8
- vpextrb $100,%xmm8,-0x99(%rbx,%riz,2)
+ vaeskeygenassist $7,-0x99(%rbx,%riz,2),%xmm8
+ vpextrb $7,%xmm8,-0x99(%rbx,%riz,2)
vcvtsi2sdl -0x99(%rbx,%riz,2),%xmm8,%xmm15
vblendvps %xmm8,-0x99(%rbx,%riz,2),%xmm12,%xmm14
- vpinsrb $100,-0x99(%rbx,%riz,2),%xmm8,%xmm15
+ vpinsrb $7,-0x99(%rbx,%riz,2),%xmm8,%xmm15
vmovdqa -0x99(%rbx,%riz,2),%ymm8
vmovdqa %ymm8,-0x99(%rbx,%riz,2)
vpermilpd -0x99(%rbx,%riz,2),%ymm8,%ymm15
- vroundpd $100,-0x99(%rbx,%riz,2),%ymm8
- vextractf128 $100,%ymm8,-0x99(%rbx,%riz,2)
- vperm2f128 $100,-0x99(%rbx,%riz,2),%ymm8,%ymm15
+ vroundpd $7,-0x99(%rbx,%riz,2),%ymm8
+ vextractf128 $7,%ymm8,-0x99(%rbx,%riz,2)
+ vperm2f128 $7,-0x99(%rbx,%riz,2),%ymm8,%ymm15
vblendvpd %ymm8,-0x99(%rbx,%riz,2),%ymm12,%ymm14
vldmxcsr -0x99(%r12,%r15,4)
vmovdqa -0x99(%r12,%r15,4),%xmm8
vcvtdq2pd -0x99(%r12,%r15,4),%ymm8
vcvtpd2psy -0x99(%r12,%r15,4),%xmm8
vpavgb -0x99(%r12,%r15,4),%xmm8,%xmm15
- vaeskeygenassist $100,-0x99(%r12,%r15,4),%xmm8
- vpextrb $100,%xmm8,-0x99(%r12,%r15,4)
+ vaeskeygenassist $7,-0x99(%r12,%r15,4),%xmm8
+ vpextrb $7,%xmm8,-0x99(%r12,%r15,4)
vcvtsi2sdl -0x99(%r12,%r15,4),%xmm8,%xmm15
vblendvps %xmm8,-0x99(%r12,%r15,4),%xmm12,%xmm14
- vpinsrb $100,-0x99(%r12,%r15,4),%xmm8,%xmm15
+ vpinsrb $7,-0x99(%r12,%r15,4),%xmm8,%xmm15
vmovdqa -0x99(%r12,%r15,4),%ymm8
vmovdqa %ymm8,-0x99(%r12,%r15,4)
vpermilpd -0x99(%r12,%r15,4),%ymm8,%ymm15
- vroundpd $100,-0x99(%r12,%r15,4),%ymm8
- vextractf128 $100,%ymm8,-0x99(%r12,%r15,4)
- vperm2f128 $100,-0x99(%r12,%r15,4),%ymm8,%ymm15
+ vroundpd $7,-0x99(%r12,%r15,4),%ymm8
+ vextractf128 $7,%ymm8,-0x99(%r12,%r15,4)
+ vperm2f128 $7,-0x99(%r12,%r15,4),%ymm8,%ymm15
vblendvpd %ymm8,-0x99(%r12,%r15,4),%ymm12,%ymm14
vldmxcsr -0x99(%r8,%r15,8)
vmovdqa -0x99(%r8,%r15,8),%xmm8
vcvtdq2pd -0x99(%r8,%r15,8),%ymm8
vcvtpd2psy -0x99(%r8,%r15,8),%xmm8
vpavgb -0x99(%r8,%r15,8),%xmm8,%xmm15
- vaeskeygenassist $100,-0x99(%r8,%r15,8),%xmm8
- vpextrb $100,%xmm8,-0x99(%r8,%r15,8)
+ vaeskeygenassist $7,-0x99(%r8,%r15,8),%xmm8
+ vpextrb $7,%xmm8,-0x99(%r8,%r15,8)
vcvtsi2sdl -0x99(%r8,%r15,8),%xmm8,%xmm15
vblendvps %xmm8,-0x99(%r8,%r15,8),%xmm12,%xmm14
- vpinsrb $100,-0x99(%r8,%r15,8),%xmm8,%xmm15
+ vpinsrb $7,-0x99(%r8,%r15,8),%xmm8,%xmm15
vmovdqa -0x99(%r8,%r15,8),%ymm8
vmovdqa %ymm8,-0x99(%r8,%r15,8)
vpermilpd -0x99(%r8,%r15,8),%ymm8,%ymm15
- vroundpd $100,-0x99(%r8,%r15,8),%ymm8
- vextractf128 $100,%ymm8,-0x99(%r8,%r15,8)
- vperm2f128 $100,-0x99(%r8,%r15,8),%ymm8,%ymm15
+ vroundpd $7,-0x99(%r8,%r15,8),%ymm8
+ vextractf128 $7,%ymm8,-0x99(%r8,%r15,8)
+ vperm2f128 $7,-0x99(%r8,%r15,8),%ymm8,%ymm15
vblendvpd %ymm8,-0x99(%r8,%r15,8),%ymm12,%ymm14
vldmxcsr -0x99(%rbp,%r13,4)
vmovdqa -0x99(%rbp,%r13,4),%xmm8
vcvtdq2pd -0x99(%rbp,%r13,4),%ymm8
vcvtpd2psy -0x99(%rbp,%r13,4),%xmm8
vpavgb -0x99(%rbp,%r13,4),%xmm8,%xmm15
- vaeskeygenassist $100,-0x99(%rbp,%r13,4),%xmm8
- vpextrb $100,%xmm8,-0x99(%rbp,%r13,4)
+ vaeskeygenassist $7,-0x99(%rbp,%r13,4),%xmm8
+ vpextrb $7,%xmm8,-0x99(%rbp,%r13,4)
vcvtsi2sdl -0x99(%rbp,%r13,4),%xmm8,%xmm15
vblendvps %xmm8,-0x99(%rbp,%r13,4),%xmm12,%xmm14
- vpinsrb $100,-0x99(%rbp,%r13,4),%xmm8,%xmm15
+ vpinsrb $7,-0x99(%rbp,%r13,4),%xmm8,%xmm15
vmovdqa -0x99(%rbp,%r13,4),%ymm8
vmovdqa %ymm8,-0x99(%rbp,%r13,4)
vpermilpd -0x99(%rbp,%r13,4),%ymm8,%ymm15
- vroundpd $100,-0x99(%rbp,%r13,4),%ymm8
- vextractf128 $100,%ymm8,-0x99(%rbp,%r13,4)
- vperm2f128 $100,-0x99(%rbp,%r13,4),%ymm8,%ymm15
+ vroundpd $7,-0x99(%rbp,%r13,4),%ymm8
+ vextractf128 $7,%ymm8,-0x99(%rbp,%r13,4)
+ vperm2f128 $7,-0x99(%rbp,%r13,4),%ymm8,%ymm15
vblendvpd %ymm8,-0x99(%rbp,%r13,4),%ymm12,%ymm14
vldmxcsr -0x99(%rsp,%r12,1)
vmovdqa -0x99(%rsp,%r12,1),%xmm8
vcvtdq2pd -0x99(%rsp,%r12,1),%ymm8
vcvtpd2psy -0x99(%rsp,%r12,1),%xmm8
vpavgb -0x99(%rsp,%r12,1),%xmm8,%xmm15
- vaeskeygenassist $100,-0x99(%rsp,%r12,1),%xmm8
- vpextrb $100,%xmm8,-0x99(%rsp,%r12,1)
+ vaeskeygenassist $7,-0x99(%rsp,%r12,1),%xmm8
+ vpextrb $7,%xmm8,-0x99(%rsp,%r12,1)
vcvtsi2sdl -0x99(%rsp,%r12,1),%xmm8,%xmm15
vblendvps %xmm8,-0x99(%rsp,%r12,1),%xmm12,%xmm14
- vpinsrb $100,-0x99(%rsp,%r12,1),%xmm8,%xmm15
+ vpinsrb $7,-0x99(%rsp,%r12,1),%xmm8,%xmm15
vmovdqa -0x99(%rsp,%r12,1),%ymm8
vmovdqa %ymm8,-0x99(%rsp,%r12,1)
vpermilpd -0x99(%rsp,%r12,1),%ymm8,%ymm15
- vroundpd $100,-0x99(%rsp,%r12,1),%ymm8
- vextractf128 $100,%ymm8,-0x99(%rsp,%r12,1)
- vperm2f128 $100,-0x99(%rsp,%r12,1),%ymm8,%ymm15
+ vroundpd $7,-0x99(%rsp,%r12,1),%ymm8
+ vextractf128 $7,%ymm8,-0x99(%rsp,%r12,1)
+ vperm2f128 $7,-0x99(%rsp,%r12,1),%ymm8,%ymm15
vblendvpd %ymm8,-0x99(%rsp,%r12,1),%ymm12,%ymm14
# Tests for all register operands.
vmovmskpd %xmm8,%r8d
- vpslld $100,%xmm8,%xmm15
+ vpslld $7,%xmm8,%xmm15
vmovmskps %ymm8,%r8d
vmovdqa %xmm8,%xmm15
vmovd %xmm8,%r8d
vcvtsd2si %xmm8,%r8d
vcvtdq2pd %xmm8,%ymm8
vcvtpd2psy %ymm8,%xmm8
- vaeskeygenassist $100,%xmm8,%xmm15
- vpextrb $100,%xmm8,%r8d
+ vaeskeygenassist $7,%xmm8,%xmm15
+ vpextrb $7,%xmm8,%r8d
vcvtsi2sdl %r8d,%xmm8,%xmm15
vblendvps %xmm8,%xmm8,%xmm12,%xmm14
- vpinsrb $100,%r8d,%xmm8,%xmm15
+ vpinsrb $7,%r8d,%xmm8,%xmm15
vmovdqa %ymm8,%ymm15
vpermilpd %ymm8,%ymm15,%ymm12
- vroundpd $100,%ymm8,%ymm15
- vextractf128 $100,%ymm8,%xmm8
- vperm2f128 $100,%ymm8,%ymm15,%ymm12
+ vroundpd $7,%ymm8,%ymm15
+ vextractf128 $7,%ymm8,%xmm8
+ vperm2f128 $7,%ymm8,%ymm15,%ymm12
vblendvpd %ymm8,%ymm15,%ymm12,%ymm14
- vinsertf128 $100,%xmm8,%ymm8,%ymm15
+ vinsertf128 $7,%xmm8,%ymm8,%ymm15
# Tests for different memory/register operand
vcvtsd2si (%rcx),%r8
vextractps $10,%xmm8,%r8
vcvtss2si (%rcx),%r8
- vpinsrw $100,%r8,%xmm15,%xmm8
+ vpinsrw $7,%r8,%xmm15,%xmm8
.intel_syntax noprefix
+
# Tests for op mem64
vldmxcsr DWORD PTR [rcx]
vldmxcsr [rcx]
vmaskmovps [rcx],ymm6,ymm4
# Tests for op imm8, ymm/mem256, ymm
- vpermilpd ymm2,ymm6,100
- vpermilpd ymm6,YMMWORD PTR [rcx],100
- vpermilpd ymm6,[rcx],100
- vpermilps ymm2,ymm6,100
- vpermilps ymm6,YMMWORD PTR [rcx],100
- vpermilps ymm6,[rcx],100
- vroundpd ymm2,ymm6,100
- vroundpd ymm6,YMMWORD PTR [rcx],100
- vroundpd ymm6,[rcx],100
- vroundps ymm2,ymm6,100
- vroundps ymm6,YMMWORD PTR [rcx],100
- vroundps ymm6,[rcx],100
+ vpermilpd ymm2,ymm6,7
+ vpermilpd ymm6,YMMWORD PTR [rcx],7
+ vpermilpd ymm6,[rcx],7
+ vpermilps ymm2,ymm6,7
+ vpermilps ymm6,YMMWORD PTR [rcx],7
+ vpermilps ymm6,[rcx],7
+ vroundpd ymm2,ymm6,7
+ vroundpd ymm6,YMMWORD PTR [rcx],7
+ vroundpd ymm6,[rcx],7
+ vroundps ymm2,ymm6,7
+ vroundps ymm6,YMMWORD PTR [rcx],7
+ vroundps ymm6,[rcx],7
# Tests for op ymm/mem256, ymm, ymm
vaddpd ymm2,ymm6,ymm4
vcvttpd2dq xmm4,YMMWORD PTR [rcx]
# Tests for op ymm/mem256, ymm
- vcvtdq2ps ymm4,ymm4
+ vcvtdq2ps ymm6,ymm4
vcvtdq2ps ymm4,YMMWORD PTR [rcx]
vcvtdq2ps ymm4,[rcx]
- vcvtps2dq ymm4,ymm4
+ vcvtps2dq ymm6,ymm4
vcvtps2dq ymm4,YMMWORD PTR [rcx]
vcvtps2dq ymm4,[rcx]
- vcvttps2dq ymm4,ymm4
+ vcvttps2dq ymm6,ymm4
vcvttps2dq ymm4,YMMWORD PTR [rcx]
vcvttps2dq ymm4,[rcx]
- vmovapd ymm4,ymm4
+ vmovapd ymm6,ymm4
vmovapd ymm4,YMMWORD PTR [rcx]
vmovapd ymm4,[rcx]
- vmovaps ymm4,ymm4
+ vmovaps ymm6,ymm4
vmovaps ymm4,YMMWORD PTR [rcx]
vmovaps ymm4,[rcx]
- vmovdqa ymm4,ymm4
+ vmovdqa ymm6,ymm4
vmovdqa ymm4,YMMWORD PTR [rcx]
vmovdqa ymm4,[rcx]
- vmovdqu ymm4,ymm4
+ vmovdqu ymm6,ymm4
vmovdqu ymm4,YMMWORD PTR [rcx]
vmovdqu ymm4,[rcx]
- vmovddup ymm4,ymm4
+ vmovddup ymm6,ymm4
vmovddup ymm4,YMMWORD PTR [rcx]
vmovddup ymm4,[rcx]
- vmovshdup ymm4,ymm4
+ vmovshdup ymm6,ymm4
vmovshdup ymm4,YMMWORD PTR [rcx]
vmovshdup ymm4,[rcx]
- vmovsldup ymm4,ymm4
+ vmovsldup ymm6,ymm4
vmovsldup ymm4,YMMWORD PTR [rcx]
vmovsldup ymm4,[rcx]
- vmovupd ymm4,ymm4
+ vmovupd ymm6,ymm4
vmovupd ymm4,YMMWORD PTR [rcx]
vmovupd ymm4,[rcx]
- vmovups ymm4,ymm4
+ vmovups ymm6,ymm4
vmovups ymm4,YMMWORD PTR [rcx]
vmovups ymm4,[rcx]
- vptest ymm4,ymm4
+ vptest ymm6,ymm4
vptest ymm4,YMMWORD PTR [rcx]
vptest ymm4,[rcx]
- vrcpps ymm4,ymm4
+ vrcpps ymm6,ymm4
vrcpps ymm4,YMMWORD PTR [rcx]
vrcpps ymm4,[rcx]
- vrsqrtps ymm4,ymm4
+ vrsqrtps ymm6,ymm4
vrsqrtps ymm4,YMMWORD PTR [rcx]
vrsqrtps ymm4,[rcx]
- vsqrtpd ymm4,ymm4
+ vsqrtpd ymm6,ymm4
vsqrtpd ymm4,YMMWORD PTR [rcx]
vsqrtpd ymm4,[rcx]
- vsqrtps ymm4,ymm4
+ vsqrtps ymm6,ymm4
vsqrtps ymm4,YMMWORD PTR [rcx]
vsqrtps ymm4,[rcx]
- vtestpd ymm4,ymm4
+ vtestpd ymm6,ymm4
vtestpd ymm4,YMMWORD PTR [rcx]
vtestpd ymm4,[rcx]
- vtestps ymm4,ymm4
+ vtestps ymm6,ymm4
vtestps ymm4,YMMWORD PTR [rcx]
vtestps ymm4,[rcx]
vlddqu ymm4,[rcx]
# Tests for op imm8, ymm/mem256, ymm, ymm
- vblendpd ymm2,ymm6,ymm4,100
- vblendpd ymm2,ymm6,YMMWORD PTR [rcx],100
- vblendpd ymm2,ymm6,[rcx],100
- vblendps ymm2,ymm6,ymm4,100
- vblendps ymm2,ymm6,YMMWORD PTR [rcx],100
- vblendps ymm2,ymm6,[rcx],100
- vcmppd ymm2,ymm6,ymm4,100
- vcmppd ymm2,ymm6,YMMWORD PTR [rcx],100
- vcmppd ymm2,ymm6,[rcx],100
- vcmpps ymm2,ymm6,ymm4,100
- vcmpps ymm2,ymm6,YMMWORD PTR [rcx],100
- vcmpps ymm2,ymm6,[rcx],100
- vdpps ymm2,ymm6,ymm4,100
- vdpps ymm2,ymm6,YMMWORD PTR [rcx],100
- vdpps ymm2,ymm6,[rcx],100
- vperm2f128 ymm2,ymm6,ymm4,100
- vperm2f128 ymm2,ymm6,YMMWORD PTR [rcx],100
- vperm2f128 ymm2,ymm6,[rcx],100
- vshufpd ymm2,ymm6,ymm4,100
- vshufpd ymm2,ymm6,YMMWORD PTR [rcx],100
- vshufpd ymm2,ymm6,[rcx],100
- vshufps ymm2,ymm6,ymm4,100
- vshufps ymm2,ymm6,YMMWORD PTR [rcx],100
- vshufps ymm2,ymm6,[rcx],100
+ vblendpd ymm2,ymm6,ymm4,7
+ vblendpd ymm2,ymm6,YMMWORD PTR [rcx],7
+ vblendpd ymm2,ymm6,[rcx],7
+ vblendps ymm2,ymm6,ymm4,7
+ vblendps ymm2,ymm6,YMMWORD PTR [rcx],7
+ vblendps ymm2,ymm6,[rcx],7
+ vcmppd ymm2,ymm6,ymm4,7
+ vcmppd ymm2,ymm6,YMMWORD PTR [rcx],7
+ vcmppd ymm2,ymm6,[rcx],7
+ vcmpps ymm2,ymm6,ymm4,7
+ vcmpps ymm2,ymm6,YMMWORD PTR [rcx],7
+ vcmpps ymm2,ymm6,[rcx],7
+ vdpps ymm2,ymm6,ymm4,7
+ vdpps ymm2,ymm6,YMMWORD PTR [rcx],7
+ vdpps ymm2,ymm6,[rcx],7
+ vperm2f128 ymm2,ymm6,ymm4,7
+ vperm2f128 ymm2,ymm6,YMMWORD PTR [rcx],7
+ vperm2f128 ymm2,ymm6,[rcx],7
+ vshufpd ymm2,ymm6,ymm4,7
+ vshufpd ymm2,ymm6,YMMWORD PTR [rcx],7
+ vshufpd ymm2,ymm6,[rcx],7
+ vshufps ymm2,ymm6,ymm4,7
+ vshufps ymm2,ymm6,YMMWORD PTR [rcx],7
+ vshufps ymm2,ymm6,[rcx],7
# Tests for op ymm, ymm/mem256, ymm, ymm
vblendvpd ymm7,ymm2,ymm6,ymm4
vblendvps ymm7,ymm2,YMMWORD PTR [rcx],ymm4
vblendvps ymm7,ymm2,[rcx],ymm4
-# Tests for op ymm/mem256, ymm, ymm, ymm
-# Tests for op ymm, ymm/mem256, ymm, ymm
- vfmaddpd ymm7,ymm2,ymm6,ymm4
- vfmaddpd ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vfmaddpd ymm7,ymm2,ymm6,[rcx]
- vfmaddps ymm7,ymm2,ymm6,ymm4
- vfmaddps ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vfmaddps ymm7,ymm2,ymm6,[rcx]
- vfmaddsubpd ymm7,ymm2,ymm6,ymm4
- vfmaddsubpd ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vfmaddsubpd ymm7,ymm2,ymm6,[rcx]
- vfmaddsubps ymm7,ymm2,ymm6,ymm4
- vfmaddsubps ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vfmaddsubps ymm7,ymm2,ymm6,[rcx]
- vfmsubaddpd ymm7,ymm2,ymm6,ymm4
- vfmsubaddpd ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vfmsubaddpd ymm7,ymm2,ymm6,[rcx]
- vfmsubaddps ymm7,ymm2,ymm6,ymm4
- vfmsubaddps ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vfmsubaddps ymm7,ymm2,ymm6,[rcx]
- vfmsubpd ymm7,ymm2,ymm6,ymm4
- vfmsubpd ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vfmsubpd ymm7,ymm2,ymm6,[rcx]
- vfmsubps ymm7,ymm2,ymm6,ymm4
- vfmsubps ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vfmsubps ymm7,ymm2,ymm6,[rcx]
- vfnmaddpd ymm7,ymm2,ymm6,ymm4
- vfnmaddpd ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vfnmaddpd ymm7,ymm2,ymm6,[rcx]
- vfnmaddps ymm7,ymm2,ymm6,ymm4
- vfnmaddps ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vfnmaddps ymm7,ymm2,ymm6,[rcx]
- vfnmsubpd ymm7,ymm2,ymm6,ymm4
- vfnmsubpd ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vfnmsubpd ymm7,ymm2,ymm6,[rcx]
- vfnmsubps ymm7,ymm2,ymm6,ymm4
- vfnmsubps ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vfnmsubps ymm7,ymm2,ymm6,[rcx]
- vpermilmo2pd ymm7,ymm2,ymm6,ymm4
- vpermilmo2pd ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vpermilmo2pd ymm7,ymm2,ymm6,[rcx]
- vpermilmz2pd ymm7,ymm2,ymm6,ymm4
- vpermilmz2pd ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vpermilmz2pd ymm7,ymm2,ymm6,[rcx]
- vpermiltd2pd ymm7,ymm2,ymm6,ymm4
- vpermiltd2pd ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vpermiltd2pd ymm7,ymm2,ymm6,[rcx]
- vpermilmo2ps ymm7,ymm2,ymm6,ymm4
- vpermilmo2ps ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vpermilmo2ps ymm7,ymm2,ymm6,[rcx]
- vpermilmz2ps ymm7,ymm2,ymm6,ymm4
- vpermilmz2ps ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vpermilmz2ps ymm7,ymm2,ymm6,[rcx]
- vpermiltd2ps ymm7,ymm2,ymm6,ymm4
- vpermiltd2ps ymm7,ymm2,ymm6,YMMWORD PTR [rcx]
- vpermiltd2ps ymm7,ymm2,ymm6,[rcx]
-
-# Tests for op imm4, ymm/mem256, ymm, ymm, ymm
-# Tests for op imm4, ymm, ymm/mem256, ymm, ymm
- vpermil2pd ymm7,ymm2,ymm6,ymm4,10
- vpermil2pd ymm7,ymm2,ymm6,YMMWORD PTR [rcx],10
- vpermil2pd ymm7,ymm2,ymm6,[rcx],10
- vpermil2ps ymm7,ymm2,ymm6,ymm4,10
- vpermil2ps ymm7,ymm2,ymm6,YMMWORD PTR [rcx],10
- vpermil2ps ymm7,ymm2,ymm6,[rcx],10
-
# Tests for op imm8, xmm/mem128, ymm, ymm
- vinsertf128 ymm6,ymm4,xmm4,100
- vinsertf128 ymm6,ymm4,XMMWORD PTR [rcx],100
- vinsertf128 ymm6,ymm4,[rcx],100
+ vinsertf128 ymm6,ymm4,xmm4,7
+ vinsertf128 ymm6,ymm4,XMMWORD PTR [rcx],7
+ vinsertf128 ymm6,ymm4,[rcx],7
# Tests for op imm8, ymm, xmm/mem128
- vextractf128 xmm4,ymm4,100
- vextractf128 XMMWORD PTR [rcx],ymm4,100
- vextractf128 [rcx],ymm4,100
+ vextractf128 xmm4,ymm4,7
+ vextractf128 XMMWORD PTR [rcx],ymm4,7
+ vextractf128 [rcx],ymm4,7
# Tests for op mem128, ymm
vbroadcastf128 ymm4,XMMWORD PTR [rcx]
vmaskmovpd xmm6,xmm4,[rcx]
# Tests for op imm8, xmm/mem128, xmm
- vaeskeygenassist xmm6,xmm4,100
- vaeskeygenassist xmm6,XMMWORD PTR [rcx],100
- vaeskeygenassist xmm6,[rcx],100
- vpcmpestri xmm6,xmm4,100
- vpcmpestri xmm6,XMMWORD PTR [rcx],100
- vpcmpestri xmm6,[rcx],100
- vpcmpestrm xmm6,xmm4,100
- vpcmpestrm xmm6,XMMWORD PTR [rcx],100
- vpcmpestrm xmm6,[rcx],100
- vpcmpistri xmm6,xmm4,100
- vpcmpistri xmm6,XMMWORD PTR [rcx],100
- vpcmpistri xmm6,[rcx],100
- vpcmpistrm xmm6,xmm4,100
- vpcmpistrm xmm6,XMMWORD PTR [rcx],100
- vpcmpistrm xmm6,[rcx],100
- vpermilpd xmm6,xmm4,100
- vpermilpd xmm6,XMMWORD PTR [rcx],100
- vpermilpd xmm6,[rcx],100
- vpermilps xmm6,xmm4,100
- vpermilps xmm6,XMMWORD PTR [rcx],100
- vpermilps xmm6,[rcx],100
- vpshufd xmm6,xmm4,100
- vpshufd xmm6,XMMWORD PTR [rcx],100
- vpshufd xmm6,[rcx],100
- vpshufhw xmm6,xmm4,100
- vpshufhw xmm6,XMMWORD PTR [rcx],100
- vpshufhw xmm6,[rcx],100
- vpshuflw xmm6,xmm4,100
- vpshuflw xmm6,XMMWORD PTR [rcx],100
- vpshuflw xmm6,[rcx],100
- vroundpd xmm6,xmm4,100
- vroundpd xmm6,XMMWORD PTR [rcx],100
- vroundpd xmm6,[rcx],100
- vroundps xmm6,xmm4,100
- vroundps xmm6,XMMWORD PTR [rcx],100
- vroundps xmm6,[rcx],100
+ vaeskeygenassist xmm6,xmm4,7
+ vaeskeygenassist xmm6,XMMWORD PTR [rcx],7
+ vaeskeygenassist xmm6,[rcx],7
+ vpcmpestri xmm6,xmm4,7
+ vpcmpestri xmm6,XMMWORD PTR [rcx],7
+ vpcmpestri xmm6,[rcx],7
+ vpcmpestrm xmm6,xmm4,7
+ vpcmpestrm xmm6,XMMWORD PTR [rcx],7
+ vpcmpestrm xmm6,[rcx],7
+ vpcmpistri xmm6,xmm4,7
+ vpcmpistri xmm6,XMMWORD PTR [rcx],7
+ vpcmpistri xmm6,[rcx],7
+ vpcmpistrm xmm6,xmm4,7
+ vpcmpistrm xmm6,XMMWORD PTR [rcx],7
+ vpcmpistrm xmm6,[rcx],7
+ vpermilpd xmm6,xmm4,7
+ vpermilpd xmm6,XMMWORD PTR [rcx],7
+ vpermilpd xmm6,[rcx],7
+ vpermilps xmm6,xmm4,7
+ vpermilps xmm6,XMMWORD PTR [rcx],7
+ vpermilps xmm6,[rcx],7
+ vpshufd xmm6,xmm4,7
+ vpshufd xmm6,XMMWORD PTR [rcx],7
+ vpshufd xmm6,[rcx],7
+ vpshufhw xmm6,xmm4,7
+ vpshufhw xmm6,XMMWORD PTR [rcx],7
+ vpshufhw xmm6,[rcx],7
+ vpshuflw xmm6,xmm4,7
+ vpshuflw xmm6,XMMWORD PTR [rcx],7
+ vpshuflw xmm6,[rcx],7
+ vroundpd xmm6,xmm4,7
+ vroundpd xmm6,XMMWORD PTR [rcx],7
+ vroundpd xmm6,[rcx],7
+ vroundps xmm6,xmm4,7
+ vroundps xmm6,XMMWORD PTR [rcx],7
+ vroundps xmm6,[rcx],7
# Tests for op xmm, xmm, mem128
vmaskmovps XMMWORD PTR [rcx],xmm6,xmm4
vmaskmovpd [rcx],xmm6,xmm4
# Tests for op imm8, xmm/mem128, xmm, xmm
- vblendpd xmm2,xmm6,xmm4,100
- vblendpd xmm2,xmm6,XMMWORD PTR [rcx],100
- vblendpd xmm2,xmm6,[rcx],100
- vblendps xmm2,xmm6,xmm4,100
- vblendps xmm2,xmm6,XMMWORD PTR [rcx],100
- vblendps xmm2,xmm6,[rcx],100
- vcmppd xmm2,xmm6,xmm4,100
- vcmppd xmm2,xmm6,XMMWORD PTR [rcx],100
- vcmppd xmm2,xmm6,[rcx],100
- vcmpps xmm2,xmm6,xmm4,100
- vcmpps xmm2,xmm6,XMMWORD PTR [rcx],100
- vcmpps xmm2,xmm6,[rcx],100
- vdppd xmm2,xmm6,xmm4,100
- vdppd xmm2,xmm6,XMMWORD PTR [rcx],100
- vdppd xmm2,xmm6,[rcx],100
- vdpps xmm2,xmm6,xmm4,100
- vdpps xmm2,xmm6,XMMWORD PTR [rcx],100
- vdpps xmm2,xmm6,[rcx],100
- vmpsadbw xmm2,xmm6,xmm4,100
- vmpsadbw xmm2,xmm6,XMMWORD PTR [rcx],100
- vmpsadbw xmm2,xmm6,[rcx],100
- vpalignr xmm2,xmm6,xmm4,100
- vpalignr xmm2,xmm6,XMMWORD PTR [rcx],100
- vpalignr xmm2,xmm6,[rcx],100
- vpblendw xmm2,xmm6,xmm4,100
- vpblendw xmm2,xmm6,XMMWORD PTR [rcx],100
- vpblendw xmm2,xmm6,[rcx],100
- vshufpd xmm2,xmm6,xmm4,100
- vshufpd xmm2,xmm6,XMMWORD PTR [rcx],100
- vshufpd xmm2,xmm6,[rcx],100
- vshufps xmm2,xmm6,xmm4,100
- vshufps xmm2,xmm6,XMMWORD PTR [rcx],100
- vshufps xmm2,xmm6,[rcx],100
+ vblendpd xmm2,xmm6,xmm4,7
+ vblendpd xmm2,xmm6,XMMWORD PTR [rcx],7
+ vblendpd xmm2,xmm6,[rcx],7
+ vblendps xmm2,xmm6,xmm4,7
+ vblendps xmm2,xmm6,XMMWORD PTR [rcx],7
+ vblendps xmm2,xmm6,[rcx],7
+ vcmppd xmm2,xmm6,xmm4,7
+ vcmppd xmm2,xmm6,XMMWORD PTR [rcx],7
+ vcmppd xmm2,xmm6,[rcx],7
+ vcmpps xmm2,xmm6,xmm4,7
+ vcmpps xmm2,xmm6,XMMWORD PTR [rcx],7
+ vcmpps xmm2,xmm6,[rcx],7
+ vdppd xmm2,xmm6,xmm4,7
+ vdppd xmm2,xmm6,XMMWORD PTR [rcx],7
+ vdppd xmm2,xmm6,[rcx],7
+ vdpps xmm2,xmm6,xmm4,7
+ vdpps xmm2,xmm6,XMMWORD PTR [rcx],7
+ vdpps xmm2,xmm6,[rcx],7
+ vmpsadbw xmm2,xmm6,xmm4,7
+ vmpsadbw xmm2,xmm6,XMMWORD PTR [rcx],7
+ vmpsadbw xmm2,xmm6,[rcx],7
+ vpalignr xmm2,xmm6,xmm4,7
+ vpalignr xmm2,xmm6,XMMWORD PTR [rcx],7
+ vpalignr xmm2,xmm6,[rcx],7
+ vpblendw xmm2,xmm6,xmm4,7
+ vpblendw xmm2,xmm6,XMMWORD PTR [rcx],7
+ vpblendw xmm2,xmm6,[rcx],7
+ vshufpd xmm2,xmm6,xmm4,7
+ vshufpd xmm2,xmm6,XMMWORD PTR [rcx],7
+ vshufpd xmm2,xmm6,[rcx],7
+ vshufps xmm2,xmm6,xmm4,7
+ vshufps xmm2,xmm6,XMMWORD PTR [rcx],7
+ vshufps xmm2,xmm6,[rcx],7
# Tests for op xmm, xmm/mem128, xmm, xmm
vblendvpd xmm7,xmm2,xmm6,xmm4
vpblendvb xmm7,xmm2,XMMWORD PTR [rcx],xmm4
vpblendvb xmm7,xmm2,[rcx],xmm4
-# Tests for op xmm/mem128, xmm, xmm, xmm
-# Tests for op xmm, xmm/mem128, xmm, xmm
- vfmaddpd xmm7,xmm2,xmm6,xmm4
- vfmaddpd xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vfmaddpd xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vfmaddpd xmm7,xmm2,xmm6,[rcx]
- vfmaddpd xmm7,xmm2,[rcx],xmm4
- vfmaddps xmm7,xmm2,xmm6,xmm4
- vfmaddps xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vfmaddps xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vfmaddps xmm7,xmm2,xmm6,[rcx]
- vfmaddps xmm7,xmm2,[rcx],xmm4
- vfmaddsubpd xmm7,xmm2,xmm6,xmm4
- vfmaddsubpd xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vfmaddsubpd xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vfmaddsubpd xmm7,xmm2,xmm6,[rcx]
- vfmaddsubpd xmm7,xmm2,[rcx],xmm4
- vfmaddsubps xmm7,xmm2,xmm6,xmm4
- vfmaddsubps xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vfmaddsubps xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vfmaddsubps xmm7,xmm2,xmm6,[rcx]
- vfmaddsubps xmm7,xmm2,[rcx],xmm4
- vfmsubaddpd xmm7,xmm2,xmm6,xmm4
- vfmsubaddpd xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vfmsubaddpd xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vfmsubaddpd xmm7,xmm2,xmm6,[rcx]
- vfmsubaddpd xmm7,xmm2,[rcx],xmm4
- vfmsubaddps xmm7,xmm2,xmm6,xmm4
- vfmsubaddps xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vfmsubaddps xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vfmsubaddps xmm7,xmm2,xmm6,[rcx]
- vfmsubaddps xmm7,xmm2,[rcx],xmm4
- vfmsubpd xmm7,xmm2,xmm6,xmm4
- vfmsubpd xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vfmsubpd xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vfmsubpd xmm7,xmm2,xmm6,[rcx]
- vfmsubpd xmm7,xmm2,[rcx],xmm4
- vfmsubps xmm7,xmm2,xmm6,xmm4
- vfmsubps xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vfmsubps xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vfmsubps xmm7,xmm2,xmm6,[rcx]
- vfmsubps xmm7,xmm2,[rcx],xmm4
- vfnmaddpd xmm7,xmm2,xmm6,xmm4
- vfnmaddpd xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vfnmaddpd xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vfnmaddpd xmm7,xmm2,xmm6,[rcx]
- vfnmaddpd xmm7,xmm2,[rcx],xmm4
- vfnmaddps xmm7,xmm2,xmm6,xmm4
- vfnmaddps xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vfnmaddps xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vfnmaddps xmm7,xmm2,xmm6,[rcx]
- vfnmaddps xmm7,xmm2,[rcx],xmm4
- vfnmsubpd xmm7,xmm2,xmm6,xmm4
- vfnmsubpd xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vfnmsubpd xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vfnmsubpd xmm7,xmm2,xmm6,[rcx]
- vfnmsubpd xmm7,xmm2,[rcx],xmm4
- vfnmsubps xmm7,xmm2,xmm6,xmm4
- vfnmsubps xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vfnmsubps xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vfnmsubps xmm7,xmm2,xmm6,[rcx]
- vfnmsubps xmm7,xmm2,[rcx],xmm4
- vpermilmo2pd xmm7,xmm2,xmm6,xmm4
- vpermilmo2pd xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vpermilmo2pd xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vpermilmo2pd xmm7,xmm2,xmm6,[rcx]
- vpermilmo2pd xmm7,xmm2,[rcx],xmm4
- vpermilmz2pd xmm7,xmm2,xmm6,xmm4
- vpermilmz2pd xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vpermilmz2pd xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vpermilmz2pd xmm7,xmm2,xmm6,[rcx]
- vpermilmz2pd xmm7,xmm2,[rcx],xmm4
- vpermiltd2pd xmm7,xmm2,xmm6,xmm4
- vpermiltd2pd xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vpermiltd2pd xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vpermiltd2pd xmm7,xmm2,xmm6,[rcx]
- vpermiltd2pd xmm7,xmm2,[rcx],xmm4
- vpermilmo2ps xmm7,xmm2,xmm6,xmm4
- vpermilmo2ps xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vpermilmo2ps xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vpermilmo2ps xmm7,xmm2,xmm6,[rcx]
- vpermilmo2ps xmm7,xmm2,[rcx],xmm4
- vpermilmz2ps xmm7,xmm2,xmm6,xmm4
- vpermilmz2ps xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vpermilmz2ps xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vpermilmz2ps xmm7,xmm2,xmm6,[rcx]
- vpermilmz2ps xmm7,xmm2,[rcx],xmm4
- vpermiltd2ps xmm7,xmm2,xmm6,xmm4
- vpermiltd2ps xmm7,xmm2,xmm6,XMMWORD PTR [rcx]
- vpermiltd2ps xmm7,xmm2,XMMWORD PTR [rcx],xmm4
- vpermiltd2ps xmm7,xmm2,xmm6,[rcx]
- vpermiltd2ps xmm7,xmm2,[rcx],xmm4
-
-# Tests for op imm4, xmm/mem128, xmm, xmm, xmm
-# Tests for op imm4, xmm, xmm/mem128, xmm, xmm
- vpermil2pd xmm7,xmm2,xmm6,xmm4,10
- vpermil2pd xmm7,xmm2,xmm6,XMMWORD PTR [rcx],10
- vpermil2pd xmm7,xmm2,XMMWORD PTR [rcx],xmm4,10
- vpermil2pd xmm7,xmm2,xmm6,[rcx],10
- vpermil2pd xmm7,xmm2,[rcx],xmm4,10
- vpermil2ps xmm7,xmm2,xmm6,xmm4,10
- vpermil2ps xmm7,xmm2,xmm6,XMMWORD PTR [rcx],10
- vpermil2ps xmm7,xmm2,XMMWORD PTR [rcx],xmm4,10
- vpermil2ps xmm7,xmm2,xmm6,[rcx],10
- vpermil2ps xmm7,xmm2,[rcx],xmm4,10
-
# Tests for op mem64, ymm
vbroadcastsd ymm4,QWORD PTR [rcx]
vbroadcastsd ymm4,[rcx]
# Tests for op regq/mem64, xmm
vmovd rcx,xmm4
vmovd xmm4,rcx
- vmovd QWORD PTR [rcx],xmm4
- vmovd xmm4,QWORD PTR [rcx]
+ vmovd [rcx],xmm4
+ vmovd xmm4,[rcx]
vmovq rcx,xmm4
vmovq xmm4,rcx
vmovq QWORD PTR [rcx],xmm4
vcvtsi2ssq xmm6,xmm4,[rcx]
# Tests for op imm8, regq/mem64, xmm, xmm
- vpinsrq xmm6,xmm4,rcx,100
- vpinsrq xmm6,xmm4,QWORD PTR [rcx],100
- vpinsrq xmm6,xmm4,[rcx],100
+ vpinsrq xmm6,xmm4,rcx,7
+ vpinsrq xmm6,xmm4,QWORD PTR [rcx],7
+ vpinsrq xmm6,xmm4,[rcx],7
# Testsf for op imm8, xmm, regq/mem64
- vpextrq rcx,xmm4,100
- vpextrq QWORD PTR [rcx],xmm4,100
- vpextrq [rcx],xmm4,100
+ vpextrq rcx,xmm4,7
+ vpextrq QWORD PTR [rcx],xmm4,7
+ vpextrq [rcx],xmm4,7
# Tests for op mem64, xmm, xmm
vmovlpd xmm6,xmm4,QWORD PTR [rcx]
vmovhps xmm6,xmm4,[rcx]
# Tests for op imm8, xmm/mem64, xmm, xmm
- vcmpsd xmm2,xmm6,xmm4,100
- vcmpsd xmm2,xmm6,QWORD PTR [rcx],100
- vcmpsd xmm2,xmm6,[rcx],100
- vroundsd xmm2,xmm6,xmm4,100
- vroundsd xmm2,xmm6,QWORD PTR [rcx],100
- vroundsd xmm2,xmm6,[rcx],100
-
-# Tests for op xmm/mem64, xmm, xmm, xmm
-# Tests for op xmm, xmm/mem64, xmm, xmm
- vfmaddsd xmm7,xmm2,xmm6,xmm4
- vfmaddsd xmm7,xmm2,xmm6,QWORD PTR [rcx]
- vfmaddsd xmm7,xmm2,QWORD PTR [rcx],xmm4
- vfmaddsd xmm7,xmm2,xmm6,[rcx]
- vfmaddsd xmm7,xmm2,[rcx],xmm4
- vfmsubsd xmm7,xmm2,xmm6,xmm4
- vfmsubsd xmm7,xmm2,xmm6,QWORD PTR [rcx]
- vfmsubsd xmm7,xmm2,QWORD PTR [rcx],xmm4
- vfmsubsd xmm7,xmm2,xmm6,[rcx]
- vfmsubsd xmm7,xmm2,[rcx],xmm4
- vfnmaddsd xmm7,xmm2,xmm6,xmm4
- vfnmaddsd xmm7,xmm2,xmm6,QWORD PTR [rcx]
- vfnmaddsd xmm7,xmm2,QWORD PTR [rcx],xmm4
- vfnmaddsd xmm7,xmm2,xmm6,[rcx]
- vfnmaddsd xmm7,xmm2,[rcx],xmm4
- vfnmsubsd xmm7,xmm2,xmm6,xmm4
- vfnmsubsd xmm7,xmm2,xmm6,QWORD PTR [rcx]
- vfnmsubsd xmm7,xmm2,QWORD PTR [rcx],xmm4
- vfnmsubsd xmm7,xmm2,xmm6,[rcx]
- vfnmsubsd xmm7,xmm2,[rcx],xmm4
+ vcmpsd xmm2,xmm6,xmm4,7
+ vcmpsd xmm2,xmm6,QWORD PTR [rcx],7
+ vcmpsd xmm2,xmm6,[rcx],7
+ vroundsd xmm2,xmm6,xmm4,7
+ vroundsd xmm2,xmm6,QWORD PTR [rcx],7
+ vroundsd xmm2,xmm6,[rcx],7
# Tests for op xmm/mem64, xmm, xmm
vaddsd xmm2,xmm6,xmm4
vcmptrue_ussd xmm2,xmm6,QWORD PTR [rcx]
vcmptrue_ussd xmm2,xmm6,[rcx]
+# Tests for op mem64
+ vldmxcsr DWORD PTR [rcx]
+ vldmxcsr [rcx]
+ vstmxcsr DWORD PTR [rcx]
+ vstmxcsr [rcx]
+
# Tests for op xmm/mem32, xmm, xmm
vaddss xmm2,xmm6,xmm4
vaddss xmm2,xmm6,DWORD PTR [rcx]
vpmovmskb rcx,xmm4
# Tests for op imm8, xmm, regq/mem32
- vextractps rcx,xmm4,100
- vextractps DWORD PTR [rcx],xmm4,100
- vextractps [rcx],xmm4,100
+ vextractps rcx,xmm4,7
+ vextractps DWORD PTR [rcx],xmm4,7
+ vextractps [rcx],xmm4,7
+
# Tests for op imm8, xmm, regl/mem32
- vpextrd ecx,xmm4,100
- vpextrd DWORD PTR [rcx],xmm4,100
- vpextrd [rcx],xmm4,100
- vextractps ecx,xmm4,100
- vextractps DWORD PTR [rcx],xmm4,100
- vextractps [rcx],xmm4,100
+ vpextrd ecx,xmm4,7
+ vpextrd DWORD PTR [rcx],xmm4,7
+ vpextrd [rcx],xmm4,7
+ vextractps ecx,xmm4,7
+ vextractps DWORD PTR [rcx],xmm4,7
+ vextractps [rcx],xmm4,7
# Tests for op regl/mem32, xmm, xmm
vcvtsi2sd xmm6,xmm4,ecx
vcvtsi2ss xmm6,xmm4,DWORD PTR [rcx]
# Tests for op imm8, xmm/mem32, xmm, xmm
- vcmpss xmm2,xmm6,xmm4,100
- vcmpss xmm2,xmm6,DWORD PTR [rcx],100
- vcmpss xmm2,xmm6,[rcx],100
- vinsertps xmm2,xmm6,xmm4,100
- vinsertps xmm2,xmm6,DWORD PTR [rcx],100
- vinsertps xmm2,xmm6,[rcx],100
- vroundss xmm2,xmm6,xmm4,100
- vroundss xmm2,xmm6,DWORD PTR [rcx],100
- vroundss xmm2,xmm6,[rcx],100
-
-# Tests for op xmm/mem32, xmm, xmm, xmm
-# Tests for op xmm, xmm/mem32, xmm, xmm
- vfmaddss xmm7,xmm2,xmm6,xmm4
- vfmaddss xmm7,xmm2,xmm6,DWORD PTR [rcx]
- vfmaddss xmm7,xmm2,DWORD PTR [rcx],xmm4
- vfmaddss xmm7,xmm2,xmm6,[rcx]
- vfmaddss xmm7,xmm2,[rcx],xmm4
- vfmsubss xmm7,xmm2,xmm6,xmm4
- vfmsubss xmm7,xmm2,xmm6,DWORD PTR [rcx]
- vfmsubss xmm7,xmm2,DWORD PTR [rcx],xmm4
- vfmsubss xmm7,xmm2,xmm6,[rcx]
- vfmsubss xmm7,xmm2,[rcx],xmm4
- vfnmaddss xmm7,xmm2,xmm6,xmm4
- vfnmaddss xmm7,xmm2,xmm6,DWORD PTR [rcx]
- vfnmaddss xmm7,xmm2,DWORD PTR [rcx],xmm4
- vfnmaddss xmm7,xmm2,xmm6,[rcx]
- vfnmaddss xmm7,xmm2,[rcx],xmm4
- vfnmsubss xmm7,xmm2,xmm6,xmm4
- vfnmsubss xmm7,xmm2,xmm6,DWORD PTR [rcx]
- vfnmsubss xmm7,xmm2,DWORD PTR [rcx],xmm4
- vfnmsubss xmm7,xmm2,xmm6,[rcx]
- vfnmsubss xmm7,xmm2,[rcx],xmm4
+ vcmpss xmm2,xmm6,xmm4,7
+ vcmpss xmm2,xmm6,DWORD PTR [rcx],7
+ vcmpss xmm2,xmm6,[rcx],7
+ vinsertps xmm2,xmm6,xmm4,7
+ vinsertps xmm2,xmm6,DWORD PTR [rcx],7
+ vinsertps xmm2,xmm6,[rcx],7
+ vroundss xmm2,xmm6,xmm4,7
+ vroundss xmm2,xmm6,DWORD PTR [rcx],7
+ vroundss xmm2,xmm6,[rcx],7
# Tests for op xmm/m16, xmm
vpmovsxbq xmm6,xmm4
vpmovzxbq xmm4,[rcx]
# Tests for op imm8, xmm, regl/mem16
- vpextrw ecx,xmm4,100
- vpextrw WORD PTR [rcx],xmm4,100
- vpextrw [rcx],xmm4,100
+ vpextrw ecx,xmm4,7
+ vpextrw WORD PTR [rcx],xmm4,7
+ vpextrw [rcx],xmm4,7
# Tests for op imm8, xmm, regq/mem16
- vpextrw rcx,xmm4,100
- vpextrw WORD PTR [rcx],xmm4,100
- vpextrw [rcx],xmm4,100
+ vpextrw rcx,xmm4,7
+ vpextrw WORD PTR [rcx],xmm4,7
+ vpextrw [rcx],xmm4,7
# Tests for op imm8, regl/mem16, xmm, xmm
- vpinsrw xmm6,xmm4,ecx,100
- vpinsrw xmm6,xmm4,WORD PTR [rcx],100
- vpinsrw xmm6,xmm4,[rcx],100
+ vpinsrw xmm6,xmm4,ecx,7
+ vpinsrw xmm6,xmm4,WORD PTR [rcx],7
+ vpinsrw xmm6,xmm4,[rcx],7
- vpinsrw xmm6,xmm4,rcx,100
- vpinsrw xmm6,xmm4,WORD PTR [rcx],100
- vpinsrw xmm6,xmm4,[rcx],100
+ vpinsrw xmm6,xmm4,rcx,7
+ vpinsrw xmm6,xmm4,WORD PTR [rcx],7
+ vpinsrw xmm6,xmm4,[rcx],7
# Tests for op imm8, xmm, regl/mem8
- vpextrb ecx,xmm4,100
- vpextrb BYTE PTR [rcx],xmm4,100
- vpextrb [rcx],xmm4,100
+ vpextrb ecx,xmm4,7
+ vpextrb BYTE PTR [rcx],xmm4,7
+ vpextrb [rcx],xmm4,7
# Tests for op imm8, regl/mem8, xmm, xmm
- vpinsrb xmm6,xmm4,ecx,100
- vpinsrb xmm6,xmm4,BYTE PTR [rcx],100
- vpinsrb xmm6,xmm4,[rcx],100
+ vpinsrb xmm6,xmm4,ecx,7
+ vpinsrb xmm6,xmm4,BYTE PTR [rcx],7
+ vpinsrb xmm6,xmm4,[rcx],7
# Tests for op imm8, xmm, regq
- vpextrw rcx,xmm4,100
+ vpextrw rcx,xmm4,7
+
# Tests for op imm8, xmm, regq/mem8
- vpextrb rcx,xmm4,100
- vpextrb BYTE PTR [rcx],xmm4,100
- vpextrb [rcx],xmm4,100
+ vpextrb rcx,xmm4,7
+ vpextrb BYTE PTR [rcx],xmm4,7
+ vpextrb [rcx],xmm4,7
# Tests for op imm8, regl/mem8, xmm, xmm
- vpinsrb xmm6,xmm4,ecx,100
- vpinsrb xmm6,xmm4,BYTE PTR [rcx],100
- vpinsrb xmm6,xmm4,[rcx],100
+ vpinsrb xmm6,xmm4,ecx,7
+ vpinsrb xmm6,xmm4,BYTE PTR [rcx],7
+ vpinsrb xmm6,xmm4,[rcx],7
# Tests for op xmm, xmm
vmaskmovdqu xmm6,xmm4
vmovmskpd ecx,xmm4
vmovmskps ecx,xmm4
vpmovmskb ecx,xmm4
+
# Tests for op xmm, xmm, xmm
vmovhlps xmm2,xmm6,xmm4
vmovlhps xmm2,xmm6,xmm4
vmovss xmm2,xmm6,xmm4
# Tests for op imm8, xmm, xmm
- vpslld xmm6,xmm4,100
- vpslldq xmm6,xmm4,100
- vpsllq xmm6,xmm4,100
- vpsllw xmm6,xmm4,100
- vpsrad xmm6,xmm4,100
- vpsraw xmm6,xmm4,100
- vpsrld xmm6,xmm4,100
- vpsrldq xmm6,xmm4,100
- vpsrlq xmm6,xmm4,100
- vpsrlw xmm6,xmm4,100
+ vpslld xmm6,xmm4,7
+ vpslldq xmm6,xmm4,7
+ vpsllq xmm6,xmm4,7
+ vpsllw xmm6,xmm4,7
+ vpsrad xmm6,xmm4,7
+ vpsraw xmm6,xmm4,7
+ vpsrld xmm6,xmm4,7
+ vpsrldq xmm6,xmm4,7
+ vpsrlq xmm6,xmm4,7
+ vpsrlw xmm6,xmm4,7
# Tests for op imm8, xmm, regl
- vpextrw ecx,xmm4,100
+ vpextrw ecx,xmm4,7
# Tests for op ymm, regl
vmovmskpd ecx,ymm4
vmovmskpd rcx,ymm4
vmovmskps rcx,ymm4
-
# Default instructions without suffixes.
vcvtpd2dq xmm6,xmm4
vcvtpd2dq xmm6,ymm4
vcvtdq2pd ymm8,XMMWORD PTR ds:0x12345678
vcvtpd2ps xmm8,YMMWORD PTR ds:0x12345678
vpavgb xmm15,xmm8,XMMWORD PTR ds:0x12345678
- vaeskeygenassist xmm8,XMMWORD PTR ds:0x12345678,100
- vpextrb ds:0x12345678,xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR ds:0x12345678,7
+ vpextrb ds:0x12345678,xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR ds:0x12345678
vblendvps xmm14,xmm12,XMMWORD PTR ds:0x12345678,xmm8
- vpinsrb xmm15,xmm8,ds:0x12345678,100
+ vpinsrb xmm15,xmm8,ds:0x12345678,7
vmovdqa ymm8,YMMWORD PTR ds:0x12345678
vmovdqa YMMWORD PTR ds:0x12345678,ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR ds:0x12345678
- vroundpd ymm8,YMMWORD PTR ds:0x12345678,100
- vextractf128 XMMWORD PTR ds:0x12345678,ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0x12345678,100
+ vroundpd ymm8,YMMWORD PTR ds:0x12345678,7
+ vextractf128 XMMWORD PTR ds:0x12345678,ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR ds:0x12345678,7
vblendvpd ymm14,ymm12,YMMWORD PTR ds:0x12345678,ymm8
vldmxcsr DWORD PTR [rbp]
vmovdqa xmm8,XMMWORD PTR [rbp]
vcvtdq2pd ymm8,XMMWORD PTR [rbp]
vcvtpd2ps xmm8,YMMWORD PTR [rbp]
vpavgb xmm15,xmm8,XMMWORD PTR [rbp]
- vaeskeygenassist xmm8,XMMWORD PTR [rbp],100
- vpextrb [rbp],xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR [rbp],7
+ vpextrb [rbp],xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR [rbp]
vblendvps xmm14,xmm12,XMMWORD PTR [rbp],xmm8
- vpinsrb xmm15,xmm8,[rbp],100
+ vpinsrb xmm15,xmm8,[rbp],7
vmovdqa ymm8,YMMWORD PTR [rbp]
vmovdqa YMMWORD PTR [rbp],ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR [rbp]
- vroundpd ymm8,YMMWORD PTR [rbp],100
- vextractf128 XMMWORD PTR [rbp],ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR [rbp],100
+ vroundpd ymm8,YMMWORD PTR [rbp],7
+ vextractf128 XMMWORD PTR [rbp],ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR [rbp],7
vblendvpd ymm14,ymm12,YMMWORD PTR [rbp],ymm8
vldmxcsr DWORD PTR [rbp+0x99]
vmovdqa xmm8,XMMWORD PTR [rbp+0x99]
vcvtdq2pd ymm8,XMMWORD PTR [rbp+0x99]
vcvtpd2ps xmm8,YMMWORD PTR [rbp+0x99]
vpavgb xmm15,xmm8,XMMWORD PTR [rbp+0x99]
- vaeskeygenassist xmm8,XMMWORD PTR [rbp+0x99],100
- vpextrb [rbp+0x99],xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR [rbp+0x99],7
+ vpextrb [rbp+0x99],xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR [rbp+0x99]
vblendvps xmm14,xmm12,XMMWORD PTR [rbp+0x99],xmm8
- vpinsrb xmm15,xmm8,[rbp+0x99],100
+ vpinsrb xmm15,xmm8,[rbp+0x99],7
vmovdqa ymm8,YMMWORD PTR [rbp+0x99]
vmovdqa YMMWORD PTR [rbp+0x99],ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR [rbp+0x99]
- vroundpd ymm8,YMMWORD PTR [rbp+0x99],100
- vextractf128 XMMWORD PTR [rbp+0x99],ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR [rbp+0x99],100
+ vroundpd ymm8,YMMWORD PTR [rbp+0x99],7
+ vextractf128 XMMWORD PTR [rbp+0x99],ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR [rbp+0x99],7
vblendvpd ymm14,ymm12,YMMWORD PTR [rbp+0x99],ymm8
vldmxcsr DWORD PTR [r15+0x99]
vmovdqa xmm8,XMMWORD PTR [r15+0x99]
vcvtdq2pd ymm8,XMMWORD PTR [r15+0x99]
vcvtpd2ps xmm8,YMMWORD PTR [r15+0x99]
vpavgb xmm15,xmm8,XMMWORD PTR [r15+0x99]
- vaeskeygenassist xmm8,XMMWORD PTR [r15+0x99],100
- vpextrb [r15+0x99],xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR [r15+0x99],7
+ vpextrb [r15+0x99],xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR [r15+0x99]
vblendvps xmm14,xmm12,XMMWORD PTR [r15+0x99],xmm8
- vpinsrb xmm15,xmm8,[r15+0x99],100
+ vpinsrb xmm15,xmm8,[r15+0x99],7
vmovdqa ymm8,YMMWORD PTR [r15+0x99]
vmovdqa YMMWORD PTR [r15+0x99],ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR [r15+0x99]
- vroundpd ymm8,YMMWORD PTR [r15+0x99],100
- vextractf128 XMMWORD PTR [r15+0x99],ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR [r15+0x99],100
+ vroundpd ymm8,YMMWORD PTR [r15+0x99],7
+ vextractf128 XMMWORD PTR [r15+0x99],ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR [r15+0x99],7
vblendvpd ymm14,ymm12,YMMWORD PTR [r15+0x99],ymm8
vldmxcsr DWORD PTR [rip+0x99]
vmovdqa xmm8,XMMWORD PTR [rip+0x99]
vcvtdq2pd ymm8,XMMWORD PTR [rip+0x99]
vcvtpd2ps xmm8,YMMWORD PTR [rip+0x99]
vpavgb xmm15,xmm8,XMMWORD PTR [rip+0x99]
- vaeskeygenassist xmm8,XMMWORD PTR [rip+0x99],100
- vpextrb [rip+0x99],xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR [rip+0x99],7
+ vpextrb [rip+0x99],xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR [rip+0x99]
vblendvps xmm14,xmm12,XMMWORD PTR [rip+0x99],xmm8
- vpinsrb xmm15,xmm8,[rip+0x99],100
+ vpinsrb xmm15,xmm8,[rip+0x99],7
vmovdqa ymm8,YMMWORD PTR [rip+0x99]
vmovdqa YMMWORD PTR [rip+0x99],ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR [rip+0x99]
- vroundpd ymm8,YMMWORD PTR [rip+0x99],100
- vextractf128 XMMWORD PTR [rip+0x99],ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR [rip+0x99],100
+ vroundpd ymm8,YMMWORD PTR [rip+0x99],7
+ vextractf128 XMMWORD PTR [rip+0x99],ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR [rip+0x99],7
vblendvpd ymm14,ymm12,YMMWORD PTR [rip+0x99],ymm8
vldmxcsr DWORD PTR [rsp+0x99]
vmovdqa xmm8,XMMWORD PTR [rsp+0x99]
vcvtdq2pd ymm8,XMMWORD PTR [rsp+0x99]
vcvtpd2ps xmm8,YMMWORD PTR [rsp+0x99]
vpavgb xmm15,xmm8,XMMWORD PTR [rsp+0x99]
- vaeskeygenassist xmm8,XMMWORD PTR [rsp+0x99],100
- vpextrb [rsp+0x99],xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR [rsp+0x99],7
+ vpextrb [rsp+0x99],xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR [rsp+0x99]
vblendvps xmm14,xmm12,XMMWORD PTR [rsp+0x99],xmm8
- vpinsrb xmm15,xmm8,[rsp+0x99],100
+ vpinsrb xmm15,xmm8,[rsp+0x99],7
vmovdqa ymm8,YMMWORD PTR [rsp+0x99]
vmovdqa YMMWORD PTR [rsp+0x99],ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR [rsp+0x99]
- vroundpd ymm8,YMMWORD PTR [rsp+0x99],100
- vextractf128 XMMWORD PTR [rsp+0x99],ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR [rsp+0x99],100
+ vroundpd ymm8,YMMWORD PTR [rsp+0x99],7
+ vextractf128 XMMWORD PTR [rsp+0x99],ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR [rsp+0x99],7
vblendvpd ymm14,ymm12,YMMWORD PTR [rsp+0x99],ymm8
vldmxcsr DWORD PTR [r12+0x99]
vmovdqa xmm8,XMMWORD PTR [r12+0x99]
vcvtdq2pd ymm8,XMMWORD PTR [r12+0x99]
vcvtpd2ps xmm8,YMMWORD PTR [r12+0x99]
vpavgb xmm15,xmm8,XMMWORD PTR [r12+0x99]
- vaeskeygenassist xmm8,XMMWORD PTR [r12+0x99],100
- vpextrb [r12+0x99],xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR [r12+0x99],7
+ vpextrb [r12+0x99],xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR [r12+0x99]
vblendvps xmm14,xmm12,XMMWORD PTR [r12+0x99],xmm8
- vpinsrb xmm15,xmm8,[r12+0x99],100
+ vpinsrb xmm15,xmm8,[r12+0x99],7
vmovdqa ymm8,YMMWORD PTR [r12+0x99]
vmovdqa YMMWORD PTR [r12+0x99],ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR [r12+0x99]
- vroundpd ymm8,YMMWORD PTR [r12+0x99],100
- vextractf128 XMMWORD PTR [r12+0x99],ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR [r12+0x99],100
+ vroundpd ymm8,YMMWORD PTR [r12+0x99],7
+ vextractf128 XMMWORD PTR [r12+0x99],ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR [r12+0x99],7
vblendvpd ymm14,ymm12,YMMWORD PTR [r12+0x99],ymm8
vldmxcsr DWORD PTR [riz*1-0x99]
vmovdqa xmm8,XMMWORD PTR [riz*1-0x99]
vcvtdq2pd ymm8,XMMWORD PTR [riz*1-0x99]
vcvtpd2ps xmm8,YMMWORD PTR [riz*1-0x99]
vpavgb xmm15,xmm8,XMMWORD PTR [riz*1-0x99]
- vaeskeygenassist xmm8,XMMWORD PTR [riz*1-0x99],100
- vpextrb [riz*1-0x99],xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR [riz*1-0x99],7
+ vpextrb [riz*1-0x99],xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR [riz*1-0x99]
vblendvps xmm14,xmm12,XMMWORD PTR [riz*1-0x99],xmm8
- vpinsrb xmm15,xmm8,[riz*1-0x99],100
+ vpinsrb xmm15,xmm8,[riz*1-0x99],7
vmovdqa ymm8,YMMWORD PTR [riz*1-0x99]
vmovdqa YMMWORD PTR [riz*1-0x99],ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR [riz*1-0x99]
- vroundpd ymm8,YMMWORD PTR [riz*1-0x99],100
- vextractf128 XMMWORD PTR [riz*1-0x99],ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR [riz*1-0x99],100
+ vroundpd ymm8,YMMWORD PTR [riz*1-0x99],7
+ vextractf128 XMMWORD PTR [riz*1-0x99],ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR [riz*1-0x99],7
vblendvpd ymm14,ymm12,YMMWORD PTR [riz*1-0x99],ymm8
vldmxcsr DWORD PTR [riz*2-0x99]
vmovdqa xmm8,XMMWORD PTR [riz*2-0x99]
vcvtdq2pd ymm8,XMMWORD PTR [riz*2-0x99]
vcvtpd2ps xmm8,YMMWORD PTR [riz*2-0x99]
vpavgb xmm15,xmm8,XMMWORD PTR [riz*2-0x99]
- vaeskeygenassist xmm8,XMMWORD PTR [riz*2-0x99],100
- vpextrb [riz*2-0x99],xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR [riz*2-0x99],7
+ vpextrb [riz*2-0x99],xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR [riz*2-0x99]
vblendvps xmm14,xmm12,XMMWORD PTR [riz*2-0x99],xmm8
- vpinsrb xmm15,xmm8,[riz*2-0x99],100
+ vpinsrb xmm15,xmm8,[riz*2-0x99],7
vmovdqa ymm8,YMMWORD PTR [riz*2-0x99]
vmovdqa YMMWORD PTR [riz*2-0x99],ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR [riz*2-0x99]
- vroundpd ymm8,YMMWORD PTR [riz*2-0x99],100
- vextractf128 XMMWORD PTR [riz*2-0x99],ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR [riz*2-0x99],100
+ vroundpd ymm8,YMMWORD PTR [riz*2-0x99],7
+ vextractf128 XMMWORD PTR [riz*2-0x99],ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR [riz*2-0x99],7
vblendvpd ymm14,ymm12,YMMWORD PTR [riz*2-0x99],ymm8
vldmxcsr DWORD PTR [rbx+riz*1-0x99]
vmovdqa xmm8,XMMWORD PTR [rbx+riz*1-0x99]
vcvtdq2pd ymm8,XMMWORD PTR [rbx+riz*1-0x99]
vcvtpd2ps xmm8,YMMWORD PTR [rbx+riz*1-0x99]
vpavgb xmm15,xmm8,XMMWORD PTR [rbx+riz*1-0x99]
- vaeskeygenassist xmm8,XMMWORD PTR [rbx+riz*1-0x99],100
- vpextrb [rbx+riz*1-0x99],xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR [rbx+riz*1-0x99],7
+ vpextrb [rbx+riz*1-0x99],xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR [rbx+riz*1-0x99]
vblendvps xmm14,xmm12,XMMWORD PTR [rbx+riz*1-0x99],xmm8
- vpinsrb xmm15,xmm8,[rbx+riz*1-0x99],100
+ vpinsrb xmm15,xmm8,[rbx+riz*1-0x99],7
vmovdqa ymm8,YMMWORD PTR [rbx+riz*1-0x99]
vmovdqa YMMWORD PTR [rbx+riz*1-0x99],ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR [rbx+riz*1-0x99]
- vroundpd ymm8,YMMWORD PTR [rbx+riz*1-0x99],100
- vextractf128 XMMWORD PTR [rbx+riz*1-0x99],ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR [rbx+riz*1-0x99],100
+ vroundpd ymm8,YMMWORD PTR [rbx+riz*1-0x99],7
+ vextractf128 XMMWORD PTR [rbx+riz*1-0x99],ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR [rbx+riz*1-0x99],7
vblendvpd ymm14,ymm12,YMMWORD PTR [rbx+riz*1-0x99],ymm8
vldmxcsr DWORD PTR [rbx+riz*2-0x99]
vmovdqa xmm8,XMMWORD PTR [rbx+riz*2-0x99]
vcvtdq2pd ymm8,XMMWORD PTR [rbx+riz*2-0x99]
vcvtpd2ps xmm8,YMMWORD PTR [rbx+riz*2-0x99]
vpavgb xmm15,xmm8,XMMWORD PTR [rbx+riz*2-0x99]
- vaeskeygenassist xmm8,XMMWORD PTR [rbx+riz*2-0x99],100
- vpextrb [rbx+riz*2-0x99],xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR [rbx+riz*2-0x99],7
+ vpextrb [rbx+riz*2-0x99],xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR [rbx+riz*2-0x99]
vblendvps xmm14,xmm12,XMMWORD PTR [rbx+riz*2-0x99],xmm8
- vpinsrb xmm15,xmm8,[rbx+riz*2-0x99],100
+ vpinsrb xmm15,xmm8,[rbx+riz*2-0x99],7
vmovdqa ymm8,YMMWORD PTR [rbx+riz*2-0x99]
vmovdqa YMMWORD PTR [rbx+riz*2-0x99],ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR [rbx+riz*2-0x99]
- vroundpd ymm8,YMMWORD PTR [rbx+riz*2-0x99],100
- vextractf128 XMMWORD PTR [rbx+riz*2-0x99],ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR [rbx+riz*2-0x99],100
+ vroundpd ymm8,YMMWORD PTR [rbx+riz*2-0x99],7
+ vextractf128 XMMWORD PTR [rbx+riz*2-0x99],ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR [rbx+riz*2-0x99],7
vblendvpd ymm14,ymm12,YMMWORD PTR [rbx+riz*2-0x99],ymm8
vldmxcsr DWORD PTR [r12+r15*4-0x99]
vmovdqa xmm8,XMMWORD PTR [r12+r15*4-0x99]
vcvtdq2pd ymm8,XMMWORD PTR [r12+r15*4-0x99]
vcvtpd2ps xmm8,YMMWORD PTR [r12+r15*4-0x99]
vpavgb xmm15,xmm8,XMMWORD PTR [r12+r15*4-0x99]
- vaeskeygenassist xmm8,XMMWORD PTR [r12+r15*4-0x99],100
- vpextrb [r12+r15*4-0x99],xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR [r12+r15*4-0x99],7
+ vpextrb [r12+r15*4-0x99],xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR [r12+r15*4-0x99]
vblendvps xmm14,xmm12,XMMWORD PTR [r12+r15*4-0x99],xmm8
- vpinsrb xmm15,xmm8,[r12+r15*4-0x99],100
+ vpinsrb xmm15,xmm8,[r12+r15*4-0x99],7
vmovdqa ymm8,YMMWORD PTR [r12+r15*4-0x99]
vmovdqa YMMWORD PTR [r12+r15*4-0x99],ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR [r12+r15*4-0x99]
- vroundpd ymm8,YMMWORD PTR [r12+r15*4-0x99],100
- vextractf128 XMMWORD PTR [r12+r15*4-0x99],ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR [r12+r15*4-0x99],100
+ vroundpd ymm8,YMMWORD PTR [r12+r15*4-0x99],7
+ vextractf128 XMMWORD PTR [r12+r15*4-0x99],ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR [r12+r15*4-0x99],7
vblendvpd ymm14,ymm12,YMMWORD PTR [r12+r15*4-0x99],ymm8
vldmxcsr DWORD PTR [r8+r15*8-0x99]
vmovdqa xmm8,XMMWORD PTR [r8+r15*8-0x99]
vcvtdq2pd ymm8,XMMWORD PTR [r8+r15*8-0x99]
vcvtpd2ps xmm8,YMMWORD PTR [r8+r15*8-0x99]
vpavgb xmm15,xmm8,XMMWORD PTR [r8+r15*8-0x99]
- vaeskeygenassist xmm8,XMMWORD PTR [r8+r15*8-0x99],100
- vpextrb [r8+r15*8-0x99],xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR [r8+r15*8-0x99],7
+ vpextrb [r8+r15*8-0x99],xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR [r8+r15*8-0x99]
vblendvps xmm14,xmm12,XMMWORD PTR [r8+r15*8-0x99],xmm8
- vpinsrb xmm15,xmm8,[r8+r15*8-0x99],100
+ vpinsrb xmm15,xmm8,[r8+r15*8-0x99],7
vmovdqa ymm8,YMMWORD PTR [r8+r15*8-0x99]
vmovdqa YMMWORD PTR [r8+r15*8-0x99],ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR [r8+r15*8-0x99]
- vroundpd ymm8,YMMWORD PTR [r8+r15*8-0x99],100
- vextractf128 XMMWORD PTR [r8+r15*8-0x99],ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR [r8+r15*8-0x99],100
+ vroundpd ymm8,YMMWORD PTR [r8+r15*8-0x99],7
+ vextractf128 XMMWORD PTR [r8+r15*8-0x99],ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR [r8+r15*8-0x99],7
vblendvpd ymm14,ymm12,YMMWORD PTR [r8+r15*8-0x99],ymm8
vldmxcsr DWORD PTR [rbp+r12*4-0x99]
vmovdqa xmm8,XMMWORD PTR [rbp+r12*4-0x99]
vcvtdq2pd ymm8,XMMWORD PTR [rbp+r12*4-0x99]
vcvtpd2ps xmm8,YMMWORD PTR [rbp+r12*4-0x99]
vpavgb xmm15,xmm8,XMMWORD PTR [rbp+r12*4-0x99]
- vaeskeygenassist xmm8,XMMWORD PTR [rbp+r12*4-0x99],100
- vpextrb [rbp+r12*4-0x99],xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR [rbp+r12*4-0x99],7
+ vpextrb [rbp+r12*4-0x99],xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR [rbp+r12*4-0x99]
vblendvps xmm14,xmm12,XMMWORD PTR [rbp+r12*4-0x99],xmm8
- vpinsrb xmm15,xmm8,[rbp+r12*4-0x99],100
+ vpinsrb xmm15,xmm8,[rbp+r12*4-0x99],7
vmovdqa ymm8,YMMWORD PTR [rbp+r12*4-0x99]
vmovdqa YMMWORD PTR [rbp+r12*4-0x99],ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR [rbp+r12*4-0x99]
- vroundpd ymm8,YMMWORD PTR [rbp+r12*4-0x99],100
- vextractf128 XMMWORD PTR [rbp+r12*4-0x99],ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR [rbp+r12*4-0x99],100
+ vroundpd ymm8,YMMWORD PTR [rbp+r12*4-0x99],7
+ vextractf128 XMMWORD PTR [rbp+r12*4-0x99],ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR [rbp+r12*4-0x99],7
vblendvpd ymm14,ymm12,YMMWORD PTR [rbp+r12*4-0x99],ymm8
vldmxcsr DWORD PTR [rsp+r13*1-0x99]
vmovdqa xmm8,XMMWORD PTR [rsp+r13*1-0x99]
vcvtdq2pd ymm8,XMMWORD PTR [rsp+r13*1-0x99]
vcvtpd2ps xmm8,YMMWORD PTR [rsp+r13*1-0x99]
vpavgb xmm15,xmm8,XMMWORD PTR [rsp+r13*1-0x99]
- vaeskeygenassist xmm8,XMMWORD PTR [rsp+r13*1-0x99],100
- vpextrb [rsp+r13*1-0x99],xmm8,100
+ vaeskeygenassist xmm8,XMMWORD PTR [rsp+r13*1-0x99],7
+ vpextrb [rsp+r13*1-0x99],xmm8,7
vcvtsi2sd xmm15,xmm8,DWORD PTR [rsp+r13*1-0x99]
vblendvps xmm14,xmm12,XMMWORD PTR [rsp+r13*1-0x99],xmm8
- vpinsrb xmm15,xmm8,[rsp+r13*1-0x99],100
+ vpinsrb xmm15,xmm8,[rsp+r13*1-0x99],7
vmovdqa ymm8,YMMWORD PTR [rsp+r13*1-0x99]
vmovdqa YMMWORD PTR [rsp+r13*1-0x99],ymm8
vpermilpd ymm15,ymm8,YMMWORD PTR [rsp+r13*1-0x99]
- vroundpd ymm8,YMMWORD PTR [rsp+r13*1-0x99],100
- vextractf128 XMMWORD PTR [rsp+r13*1-0x99],ymm8,100
- vperm2f128 ymm15,ymm8,YMMWORD PTR [rsp+r13*1-0x99],100
+ vroundpd ymm8,YMMWORD PTR [rsp+r13*1-0x99],7
+ vextractf128 XMMWORD PTR [rsp+r13*1-0x99],ymm8,7
+ vperm2f128 ymm15,ymm8,YMMWORD PTR [rsp+r13*1-0x99],7
vblendvpd ymm14,ymm12,YMMWORD PTR [rsp+r13*1-0x99],ymm8
# Tests for all register operands.
vmovmskpd r8d,xmm8
- vpslld xmm15,xmm8,100
+ vpslld xmm15,xmm8,7
vmovmskps r8d,ymm8
vmovdqa xmm15,xmm8
vmovd r8d,xmm8
vcvtsd2si r8d,xmm8
vcvtdq2pd ymm8,xmm8
vcvtpd2ps xmm8,ymm8
- vaeskeygenassist xmm15,xmm8,100
- vpextrb r8d,xmm8,100
+ vaeskeygenassist xmm15,xmm8,7
+ vpextrb r8d,xmm8,7
vcvtsi2sd xmm15,xmm8,r8d
vblendvps xmm14,xmm12,xmm8,xmm8
- vpinsrb xmm15,xmm8,r8d,100
+ vpinsrb xmm15,xmm8,r8d,7
vmovdqa ymm15,ymm8
vpermilpd ymm12,ymm15,ymm8
- vroundpd ymm15,ymm8,100
- vextractf128 xmm8,ymm8,100
- vperm2f128 ymm12,ymm15,ymm8,100
+ vroundpd ymm15,ymm8,7
+ vextractf128 xmm8,ymm8,7
+ vperm2f128 ymm12,ymm15,ymm8,7
vblendvpd ymm14,ymm12,ymm15,ymm8
- vinsertf128 ymm15,ymm8,xmm8,100
+ vinsertf128 ymm15,ymm8,xmm8,7
# Tests for different memory/register operand
vcvtsd2si r8,QWORD PTR [rcx]
vextractps r8,xmm8,10
vcvtss2si r8,DWORD PTR [rcx]
- vpinsrw xmm8,xmm15,r8,100
+ vpinsrw xmm8,xmm15,r8,7
.*:4: Error: .*
.*:5: Error: .*
.*:6: Error: .*
-.*:7: Error: .*
-.*:8: Error: .*
.*:9: Error: .*
.*:10: Error: .*
.*:11: Error: .*
-.*:12: Error: .*
-.*:13: Error: .*
-.*:14: Error: .*
-.*:15: Error: .*
-.*:16: Error: .*
-.*:17: Error: .*
-.*:18: Error: .*
-.*:19: Error: .*
-.*:20: Error: .*
-.*:21: Error: .*
-.*:22: Error: .*
-.*:23: Error: .*
-.*:24: Error: .*
-.*:25: Error: .*
-.*:26: Error: .*
-.*:27: Error: .*
-.*:28: Error: .*
-.*:31: Error: .*
-.*:32: Error: .*
-.*:33: Error: .*
-.*:34: Error: .*
-.*:35: Error: .*
-.*:36: Error: .*
-.*:37: Error: .*
-.*:38: Error: .*
-.*:39: Error: .*
-.*:40: Error: .*
-.*:41: Error: .*
-.*:42: Error: .*
-.*:43: Error: .*
-.*:44: Error: .*
-.*:45: Error: .*
-.*:46: Error: .*
-.*:47: Error: .*
-.*:48: Error: .*
-.*:49: Error: .*
-.*:50: Error: .*
-.*:51: Error: .*
-.*:52: Error: .*
-.*:53: Error: .*
-.*:54: Error: .*
-.*:55: Error: .*
GAS LISTING .*
[ ]*4[ ]+vcvtpd2dq \(%rcx\),%xmm2
[ ]*5[ ]+vcvtpd2ps \(%rcx\),%xmm2
[ ]*6[ ]+vcvttpd2dq \(%rcx\),%xmm2
-[ ]*7[ ]+vfmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*8[ ]+vfmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*9[ ]+vfmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*10[ ]+vfmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*11[ ]+vfmaddsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*12[ ]+vfmaddsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*13[ ]+vfmsubaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*14[ ]+vfmsubaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*15[ ]+vfmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*16[ ]+vfmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*17[ ]+vfmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*18[ ]+vfmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*19[ ]+vfnmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*20[ ]+vfnmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*21[ ]+vfnmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*22[ ]+vfnmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*23[ ]+vfnmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*24[ ]+vfnmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*25[ ]+vfnmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*26[ ]+vfnmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*27[ ]+vpermil2pd \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*28[ ]+vpermil2ps \$17,%xmm4,%xmm2,%xmm1,%xmm3
-[ ]*29[ ]+
-[ ]*30[ ]+\.intel_syntax noprefix
-[ ]*31[ ]+vcvtpd2dq xmm2,\[rcx\]
-[ ]*32[ ]+vcvtpd2ps xmm2,\[rcx\]
-[ ]*33[ ]+vcvttpd2dq xmm2,\[rcx\]
-[ ]*34[ ]+vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*35[ ]+vfmaddps xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*36[ ]+vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*37[ ]+vfmaddss xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*38[ ]+vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*39[ ]+vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*40[ ]+vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*41[ ]+vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*42[ ]+vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*43[ ]+vfmsubps xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*44[ ]+vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*45[ ]+vfmsubss xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*46[ ]+vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*47[ ]+vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*48[ ]+vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*49[ ]+vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*50[ ]+vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*51[ ]+vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*52[ ]+vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*53[ ]+vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*54[ ]+vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10
-[ ]*55[ ]+vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10
+[ ]*7[ ]+
+[ ]*8[ ]+\.intel_syntax noprefix
+[ ]*9[ ]+vcvtpd2dq xmm2,\[rcx\]
+[ ]*10[ ]+vcvtpd2ps xmm2,\[rcx\]
+[ ]*11[ ]+vcvttpd2dq xmm2,\[rcx\]
vcvtpd2dq (%rcx),%xmm2
vcvtpd2ps (%rcx),%xmm2
vcvttpd2dq (%rcx),%xmm2
- vfmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmaddsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmaddsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmsubaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmsubaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vfnmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3
- vpermil2pd $17,%xmm4,%xmm2,%xmm1,%xmm3
- vpermil2ps $17,%xmm4,%xmm2,%xmm1,%xmm3
.intel_syntax noprefix
vcvtpd2dq xmm2,[rcx]
vcvtpd2ps xmm2,[rcx]
vcvttpd2dq xmm2,[rcx]
- vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10
- vfmaddps xmm3,xmm1,xmm2,xmm4,0x10
- vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10
- vfmaddss xmm3,xmm1,xmm2,xmm4,0x10
- vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10
- vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10
- vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10
- vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10
- vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10
- vfmsubps xmm3,xmm1,xmm2,xmm4,0x10
- vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10
- vfmsubss xmm3,xmm1,xmm2,xmm4,0x10
- vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10
- vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10
- vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10
- vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10
- vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10
- vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10
- vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10
- vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10
- vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10
- vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10
-2009-01-02 Matthias Klose <doko@ubuntu.com>
-
- * or32-opc.c (or32_print_register, or32_print_immediate,
- disassemble_insn): Don't rely on undefined sprintf behaviour.
-
-2008-12-30 Martin Schwidefsky <schwidefskyy@de.ibm.com>
-
- * s390-opc.txt: Add ptff instruction.
-
-2008-12-24 Jan Kratochvil <jan.kratochvil@redhat.com>
-
- * Makefile.am (CFILES, ALL_MACHINES): Add LM32 source and object files.
- * Makefile.in: Regenerate.
-
-2008-12-23 Jon Beniston <jon@beniston.com>
-
- * Makefile.am: Add LM32 object files and dependencies.
- * Makefile.in: Regenerate.
- * configure.in: Add LM32 target.
- * configure: Regenerate.
- * disassemble.c: Add LM32 disassembler.
- * cgen-asm.in: Update copyright year.
- * cgen-dis.in: Update copyright year.
- * cgen-ibld.in: Update copyright year.
- * lm32-asm.c: New file.
- * lm32-desc.c: New file.
- * lm32-desc.h: New file.
- * lm32-dis.c: New file.
- * lm32-ibld.c: New file.
- * lm32-opc.c: New file.
- * lm32-opc.h: New file.
- * lm32-opinst.c: New file.
-
-2008-12-23 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (EXdS): New.
- (EXdVexS): Likewise.
- (EXqVexS): Likewise.
- (d_swap_mode): Likewise.
- (q_mode): Updated.
- (prefix_table): Use EXdS on movss and EXqS on movsd.
- (vex_len_table): Use EXdVexS on vmovss and EXqVexS on vmovsd.
- (intel_operand_size): Handle d_swap_mode.
- (OP_EX): Likewise.
-
- * i386-opc.h (S): Update comments.
-
- * i386-opc.tbl: Add S to movss, movsd, vmovss and vmovsd.
- * i386-tbl.h: Regenerated.
-
-2008-12-23 Nick Clifton <nickc@redhat.com>
-
- * po/ga.po: Updated Irish translation.
-
-2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (EbS): New.
- (EvS): Likewise.
- (EMS): Likewise.
- (EXqS): Likewise.
- (EXxS): Likewise.
- (b_swap_mode): Likewise.
- (v_swap_mode): Likewise.
- (q_swap_mode): Likewise.
- (x_swap_mode): Likewise.
- (v_mode): Updated.
- (w_mode): Likewise.
- (t_mode): Likewise.
- (xmm_mode): Likewise.
- (swap_operand): Likewise.
- (dis386): Use EbS on movB. Use EvS on moveS.
- (dis386_twobyte): Use EXxS on movapX.
- (prefix_table): Use EXxS on movups, movupd, movdqu, movdqa,
- vmovups, vmovdqu, vmovdqa. Use EMS and EXqS on movq.
- (vex_table): Use EXxS on vmovapX.
- (vex_len_table): Use EXqS on vmovq.
- (intel_operand_size): Handle b_swap_mode, v_swap_mode,
- q_swap_mode and x_swap_mode.
- (OP_E_register): Handle b_swap_mode and v_swap_mode.
- (OP_EM): Handle v_swap_mode.
- (OP_EX): x_swap_mode and q_swap_mode.
-
- * i386-gen.c (opcode_modifiers): Add S.
-
- * i386-opc.h (S): New.
- (Modrm): Updated.
- (i386_opcode_modifier): Add s.
-
- * i386-opc.tbl: Add S to movapd, movaps, movdqa, movdqu, movq,
- movupd, movups, vmovapd, vmovaps, vmovdqa, vmovdqu and vmovq.
- * i386-tbl.h: Regenerated.
-
-2008-12-18 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (mnemonicendp): New.
- (op): Likewise.
- (print_insn): Use mnemonicendp.
- (OP_3DNowSuffix): Likewise.
- (CMP_Fixup): Likewise.
- (CMPXCHG8B_Fixup): Likewise.
- (CRC32_Fixup): Likewise.
- (OP_DREX_FCMP): Likewise.
- (OP_DREX_ICMP): Likewise.
- (VZERO_Fixup): Likewise.
- (VCMP_Fixup): Likewise.
- (PCLMUL_Fixup): Likewise.
- (VPERMIL2_Fixup): Likewise.
- (MOVBE_Fixup): Likewise.
- (putop): Update mnemonicendp.
- (oappend): Use stpcpy.
- (simd_cmp_op): Changed to struct op.
- (vex_cmp_op): Likewise.
- (pclmul_op): Likewise.
- (vpermil2_op): Likewise.
-
-2008-12-18 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
-
- * configure: Regenerate.
-
-2008-12-15 Richard Earnshaw <rearnsha@arm.com>
-
- * arm-dis.c (coprocessor_opcodes): Disassemble VFP instructions using
- unified syntax.
-
-2008-12-08 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (opcode_modifiers): Move VexNDS before VexNDD.
-
-2008-12-08 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (putop): Remove strayed comments.
-
-2008-12-04 Ben Elliston <bje@au.ibm.com>
-
- * ppc-dis.c (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE
- for -Mbooke.
- (print_ppc_disassembler_options): Update usage.
- * ppc-opc.c (DE, DES, DEO, DE_MASK): Remove.
- (BOOKE64): Remove.
- (PPCCHLK64): Likewise.
- (powerpc_opcodes): Remove all BOOKE64 instructions.
-
-2008-11-28 Joshua Kinard <kumba@gentoo.org>
-
- * mips-dis.c (mips_arch_choices): Add r14000, r16000.
-
-2008-11-27 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
-
- * cr16-dis.c (match_opcode): Truncate mcode to 32 bit and
- adjusted the mask for 32-bit branch instruction.
-
-2008-11-27 Alan Modra <amodra@bigpond.net.au>
-
- * ppc-opc.c (extract_sprg): Correct operand range check.
-
-2008-11-26 Andreas Schwab <schwab@suse.de>
-
- * m68k-dis.c (NEXTBYTE, NEXTWORD, NEXTLONG, NEXTULONG, NEXTSINGLE)
- (NEXTDOUBLE, NEXTEXTEND, NEXTPACKED): Fix error handling.
- (save_printer, save_print_address): Remove.
- (fetch_data): Don't use them.
- (match_insn_m68k): Always restore printing functions.
- (print_insn_m68k): Don't save/restore printing functions.
-
-2008-11-25 Nick Clifton <nickc@redhat.com>
-
- * m68k-dis.c: Rewrite to remove use of setjmp/longjmp.
-
-2008-11-18 Catherine Moore <clm@codesourcery.com>
-
- * arm-dis.c (coprocessor_opcodes): Add half-precision vcvt
- instructions.
- (neon_opcodes): Likewise.
- (print_insn_coprocessor): Print 't' or 'b' for vcvt
- instructions.
-
-2008-11-14 Tristan Gingold <gingold@adacore.com>
-
- * makefile.vms (OBJS): Update list of objects.
- (DEFS): Update
- (CFLAGS): Update.
-
-2008-11-06 Chao-ying Fu <fu@mips.com>
-
- * mips-opc.c (synciobdma, syncs, syncw, syncws): Move these
- before sync.
- (sync): New instruction with 5-bit sync type.
- * mips-dis.c (print_insn_args): Add case '1' to print 5-bit values.
-
-2008-11-06 Nick Clifton <nickc@redhat.com>
-
- * avr-dis.c: Replace uses of sprintf without a format string with
- calls to strcpy.
-
-2008-11-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Add cmovpe and cmovpo.
- * i386-tbl.h: Regenerated.
-
-2008-10-22 Nick Clifton <nickc@redhat.com>
-
- PR 6937
- * configure.in (SHARED_LIBADD): Revert previous change.
- Add a comment explaining why.
- (SHARED_DEPENDENCIES): Revert previous change.
- * configure: Regenerate.
-
-2008-10-10 Nick Clifton <nickc@redhat.com>
-
- PR 6937
- * configure.in (SHARED_LIBADD): Add libiberty.a.
- (SHARED_DEPENDENCIES): Add libiberty.a.
-
-2008-09-30 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c: Include "hashtab.h".
- (next_field): Take a new argument, last. Check last.
- (process_i386_cpu_flag): Updated.
- (process_i386_opcode_modifier): Likewise.
- (process_i386_operand_type): Likewise.
- (process_i386_registers): Likewise.
- (output_i386_opcode): New.
- (opcode_hash_entry): Likewise.
- (opcode_hash_table): Likewise.
- (opcode_hash_hash): Likewise.
- (opcode_hash_eq): Likewise.
- (process_i386_opcodes): Use opcode hash table and opcode array.
-
-2008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-
- * s390-opc.txt (stdy, stey): Fix description
-
-2008-09-30 Alan Modra <amodra@bigpond.net.au>
-
- * Makefile.am: Run "make dep-am".
- * Makefile.in: Regenerate.
-
-2008-09-29 H.J. Lu <hongjiu.lu@intel.com>
-
- * aclocal.m4: Regenerated.
- * configure: Likewise.
- * Makefile.in: Likewise.
-
-2008-09-29 Nick Clifton <nickc@redhat.com>
-
- * po/vi.po: Updated Vietnamese translation.
- * po/fr.po: Updated French translation.
-
-2008-09-26 Florian Krohm <fkrohm@us.ibm.com>
-
- * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
- (cfxr, cfdr, cfer, clclu): Add esa flag.
- (sqd): Instruction added.
- (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
- * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
-
-2008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
-
- * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
- (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
-
-2008-09-11 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
- * i386-tbl.h: Regenerated.
-
-2008-08-28 Jan Beulich <jbeulich@novell.com>
-
- * i386-dis.c (dis386): Adjust far return mnemonics.
- * i386-opc.tbl: Add retf.
- * i386-tbl.h: Re-generate.
-
-2008-08-28 Jan Beulich <jbeulich@novell.com>
-
- * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
-
-2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
-
- * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
- * ia64-gen.c (lookup_specifier): Likewise.
-
- * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
- * ia64-raw.tbl: Likewise.
- * ia64-waw.tbl: Likewise.
- * ia64-asmtab.c: Regenerated.
-
-2008-08-27 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Correct fidivr operand size.
-
- * i386-tbl.h: Regenerated.
-
-2008-08-24 Alan Modra <amodra@bigpond.net.au>
-
- * configure.in: Update a number of obsolete autoconf macros.
- * aclocal.m4: Regenerate.
-
-2008-08-20 H.J. Lu <hongjiu.lu@intel.com>
-
- AVX Programming Reference (August, 2008)
- * i386-dis.c (PREFIX_VEX_38DB): New.
- (PREFIX_VEX_38DC): Likewise.
- (PREFIX_VEX_38DD): Likewise.
- (PREFIX_VEX_38DE): Likewise.
- (PREFIX_VEX_38DF): Likewise.
- (PREFIX_VEX_3ADF): Likewise.
- (VEX_LEN_38DB_P_2): Likewise.
- (VEX_LEN_38DC_P_2): Likewise.
- (VEX_LEN_38DD_P_2): Likewise.
- (VEX_LEN_38DE_P_2): Likewise.
- (VEX_LEN_38DF_P_2): Likewise.
- (VEX_LEN_3ADF_P_2): Likewise.
- (PREFIX_VEX_3A04): Updated.
- (VEX_LEN_3A06_P_2): Likewise.
- (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
- PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
- (x86_64_table): Likewise.
- (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
- VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
- VEX_LEN_3ADF_P_2.
-
- * i386-opc.tbl: Add AES + AVX instructions.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
-
- * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
- * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
-
-2008-08-15 Alan Modra <amodra@bigpond.net.au>
-
- PR 6526
- * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
- * Makefile.in: Regenerate.
- * aclocal.m4: Regenerate.
- * config.in: Regenerate.
- * configure: Regenerate.
-
-2008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- PR 6825
- * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
-
-2008-08-12 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Add syscall and sysret for Cpu64.
-
- * i386-tbl.h: Regenerated.
-
-2008-08-04 Alan Modra <amodra@bigpond.net.au>
-
- * Makefile.am (POTFILES.in): Set LC_ALL=C.
- * Makefile.in: Regenerate.
- * po/POTFILES.in: Regenerate.
-
-2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
-
- * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
- (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
- (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
- * ppc-opc.c (insert_xt6): New static function.
- (extract_xt6): Likewise.
- (insert_xa6): Likewise.
- (extract_xa6: Likewise.
- (insert_xb6): Likewise.
- (extract_xb6): Likewise.
- (insert_xb6s): Likewise.
- (extract_xb6s): Likewise.
- (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
- XX3DM_MASK, PPCVSX): New.
- (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
- "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
-
-2008-08-01 Pedro Alves <pedro@codesourcery.com>
-
- * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
- * Makefile.in: Regenerate.
-
-2008-08-01 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-reg.tbl: Use Dw2Inval on AVX registers.
- * i386-tbl.h: Regenerated.
-
-2008-07-30 Michael J. Eager <eager@eagercon.com>
-
- * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
- * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
- (insert_sprg, PPC405): Use PPC_OPCODE_405.
- (powerpc_opcodes): Add Xilinx APU related opcodes.
-
-2008-07-30 Alan Modra <amodra@bigpond.net.au>
-
- * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
-
-2008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
-
- * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
-
-2008-07-07 Adam Nemet <anemet@caviumnetworks.com>
-
- * mips-opc.c (CP): New macro.
- (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
- membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
- dmtc2 Octeon instructions.
-
-2008-07-07 Stan Shebs <stan@codesourcery.com>
-
- * dis-init.c (init_disassemble_info): Init endian_code field.
- * arm-dis.c (print_insn): Disassemble code according to
- setting of endian_code.
- (print_insn_big_arm): Detect when BE8 extension flag has been set.
-
-2008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
-
- * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
- for ELF symbols.
-
-2008-06-25 Peter Bergner <bergner@vnet.ibm.com>
-
- * ppc-dis.c (powerpc_init_dialect): Handle -M464.
- (print_ppc_disassembler_options): Likewise.
- * ppc-opc.c (PPC464): Define.
- (powerpc_opcodes): Add mfdcrux and mtdcrux.
-
-2008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
-
- * configure: Regenerate.
-
-2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
-
- * ppc-dis.c (print_insn_powerpc): Update prototye to use new
- ppc_cpu_t typedef.
- (struct dis_private): New.
- (POWERPC_DIALECT): New define.
- (powerpc_dialect): Renamed to...
- (powerpc_init_dialect): This. Update to use ppc_cpu_t and
- struct dis_private.
- (print_insn_big_powerpc): Update for using structure in
- info->private_data.
- (print_insn_little_powerpc): Likewise.
- (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
- (skip_optional_operands): Likewise.
- (print_insn_powerpc): Likewise. Remove initialization of dialect.
- * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
- extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
- extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
- extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
- insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
- insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
- insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
- param to be of type ppc_cpu_t. Update prototype.
-
-2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
-
- * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
- +s, +S.
- * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
- baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
- syncw, syncws, vm3mulu, vm0 and vmulu.
-
- * mips-dis.c (print_insn_args): Handle field descriptor +Q.
- * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
- seqi, sne and snei.
-
-2008-05-30 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Add vmovd with 64bit operand.
- * i386-tbl.h: Regenerated.
-
-2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
-
- * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
-
-2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
- * i386-tbl.h: Regenerated.
-
-2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/6517
- * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
- into 32bit and 64bit. Remove Reg64|Qword and add
- IgnoreSize|No_qSuf on 32bit version.
- * i386-tbl.h: Regenerated.
-
-2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
- * i386-tbl.h: Regenerated.
-
-2008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
-
- * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
-
-2008-05-14 Alan Modra <amodra@bigpond.net.au>
-
- * Makefile.am: Run "make dep-am".
- * Makefile.in: Regenerate.
-
-2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (MOVBE_Fixup): New.
- (Mo): Likewise.
- (PREFIX_0F3880): Likewise.
- (PREFIX_0F3881): Likewise.
- (PREFIX_0F38F0): Updated.
- (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
- PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
- (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
-
- * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
- CPU_EPT_FLAGS.
- (cpu_flags): Add CpuMovbe and CpuEPT.
-
- * i386-opc.h (CpuMovbe): New.
- (CpuEPT): Likewise.
- (CpuLM): Updated.
- (i386_cpu_flags): Add cpumovbe and cpuept.
-
- * i386-opc.tbl: Add entries for movbe and EPT instructions.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2008-04-29 Adam Nemet <anemet@caviumnetworks.com>
-
- * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
- the two drem and the two dremu macros.
-
-2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
-
- * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
- instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
- cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
- INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
-
-2008-04-25 David S. Miller <davem@davemloft.net>
-
- * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
- instead of %sys_tick_cmpr, as suggested in architecture manuals.
-
-2008-04-23 Paolo Bonzini <bonzini@gnu.org>
-
- * aclocal.m4: Regenerate.
- * configure: Regenerate.
+2009-01-05 H.J. Lu <hongjiu.lu@intel.com>
-2008-04-23 David S. Miller <davem@davemloft.net>
-
- * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
- extended values.
- (prefetch_table): Add missing values.
-
-2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (opcode_modifiers): Add NoAVX.
-
- * i386-opc.h (NoAVX): New.
- (OldGcc): Updated.
- (i386_opcode_modifier): Add noavx.
-
- * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
- instructions which don't have AVX equivalent.
- * i386-tbl.h: Regenerated.
-
-2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (OP_VEX_FMA): New.
- (OP_EX_VexImmW): Likewise.
- (VexFMA): Likewise.
- (Vex128FMA): Likewise.
- (EXVexImmW): Likewise.
- (get_vex_imm8): Likewise.
- (OP_EX_VexReg): Likewise.
- (vex_i4_done): Renamed to ...
- (vex_w_done): This.
- (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
- and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
- FMA instructions.
- (print_insn): Updated.
- (OP_EX_VexW): Rewrite to swap register in VEX with EX.
- (OP_REG_VexI4): Check invalid high registers.
-
-2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
- Michael Meissner <michael.meissner@amd.com>
-
- * i386-opc.tbl: Fix protX to allow memory in the middle operand.
- * i386-tbl.h: Regenerate from i386-opc.tbl.
-
-2008-04-14 Edmar Wienskoski <edmar@freescale.com>
-
- * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
- accept Power E500MC instructions.
- (print_ppc_disassembler_options): Document -Me500mc.
- * ppc-opc.c (DUIS, DUI, T): New.
- (XRT, XRTRA): Likewise.
- (E500MC): Likewise.
- (powerpc_opcodes): Add new Power E500MC instructions.
-
-2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
-
- * s390-dis.c (init_disasm): Evaluate disassembler_options.
- (print_s390_disassembler_options): New function.
- * disassemble.c (disassembler_usage): Invoke
- print_s390_disassembler_options.
-
-2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
-
- * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
- of local variables used for mnemonic parsing: prefix, suffix and
- number.
-
-2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
-
- * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
- extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
- (s390_crb_extensions): New extensions table.
- (insertExpandedMnemonic): Handle '$' tag.
- * s390-opc.txt: Remove conditional jump variants which can now
- be expanded automatically.
- Replace '*' tag with '$' in the compare and branch instructions.
-
-2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
- (PREFIX_VEX_3AXX): Likewis.
-
-2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Remove 4 extra blank lines.
-
-2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
- with CPU_PCLMUL_FLAGS/CpuPCLMUL.
- (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
- * i386-opc.tbl: Likewise.
-
- * i386-opc.h (CpuCLMUL): Renamed to ...
- (CpuPCLMUL): This.
- (CpuFMA): Updated.
- (i386_cpu_flags): Replace cpuclmul with cpupclmul.
-
- * i386-init.h: Regenerated.
-
-2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (OP_E_register): New.
- (OP_E_memory): Likewise.
- (OP_VEX): Likewise.
- (OP_EX_Vex): Likewise.
+ AVX Programming Reference (December, 2008)
+ * i386-dis.c (OP_VEX_FMA): Removed.
(OP_EX_VexW): Likewise.
- (OP_XMM_Vex): Likewise.
+ (OP_EX_VexImmW): Likewise.
(OP_XMM_VexW): Likewise.
- (OP_REG_VexI4): Likewise.
- (PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
- (VZERO_Fixup): Likewise.
- (VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
- (rex_original): Likewise.
- (rex_ignored): Likewise.
- (Mxmm): Likewise.
- (XMM): Likewise.
- (EXxmm): Likewise.
- (EXxmmq): Likewise.
- (EXymmq): Likewise.
- (Vex): Likewise.
- (Vex128): Likewise.
- (Vex256): Likewise.
(VexI4): Likewise.
- (EXdVex): Likewise.
- (EXqVex): Likewise.
+ (VexFMA): Likewise.
+ (Vex128FMA): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
- (XMVex): Likewise.
+ (EXVexImmW): Likewise.
(XMVexW): Likewise.
- (XMVexI4): Likewise.
- (PCLMUL): Likewise.
- (VZERO): Likewise.
- (VCMP): Likewise.
(VPERMIL2): Likewise.
- (xmm_mode): Likewise.
- (xmmq_mode): Likewise.
- (ymmq_mode): Likewise.
- (vex_mode): Likewise.
- (vex128_mode): Likewise.
- (vex256_mode): Likewise.
- (USE_VEX_C4_TABLE): Likewise.
- (USE_VEX_C5_TABLE): Likewise.
- (USE_VEX_LEN_TABLE): Likewise.
- (VEX_C4_TABLE): Likewise.
- (VEX_C5_TABLE): Likewise.
- (VEX_LEN_TABLE): Likewise.
- (REG_VEX_XX): Likewise.
- (MOD_VEX_XXX): Likewise.
- (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
- (PREFIX_0F3A44): Likewise.
- (PREFIX_0F3ADF): Likewise.
- (PREFIX_VEX_XXX): Likewise.
- (VEX_OF): Likewise.
- (VEX_OF38): Likewise.
- (VEX_OF3A): Likewise.
- (VEX_LEN_XXX): Likewise.
- (vex): Likewise.
- (need_vex): Likewise.
- (need_vex_reg): Likewise.
- (vex_i4_done): Likewise.
+ (PREFIX_VEX_3A48...PREFIX_VEX_3A4A): Likewise.
+ (PREFIX_VEX_3A5C...PREFIX_VEX_3A5F): Likewise.
+ (PREFIX_VEX_3A68...PREFIX_VEX_3A6F): Likewise.
+ (PREFIX_VEX_3A78...PREFIX_VEX_3A7F): Likewise.
+ (VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2): Likewise.
+ (VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2): Likewise.
+ (get_vex_imm8): Likewise.
+ (OP_EX_VexReg): Likewise.
+ vpermil2_op): Likewise.
+ (EXVexWdq): New.
+ (vex_w_dq_mode): Likewise.
+ (PREFIX_VEX_3896...PREFIX_VEX_389F): Likewise.
+ (PREFIX_VEX_38A6...PREFIX_VEX_38AF): Likewise.
+ (PREFIX_VEX_38B6...PREFIX_VEX_38BF): Likewise.
+ (es_reg): Updated.
+ (PREFIX_VEX_38DB): Likewise.
+ (PREFIX_VEX_3A4A): Likewise.
+ (PREFIX_VEX_3A60): Likewise.
+ (PREFIX_VEX_3ADF): Likewise.
+ (VEX_LEN_3ADF_P_2): Likewise.
+ (prefix_table): Remove PREFIX_VEX_3A48...PREFIX_VEX_3A4A,
+ PREFIX_VEX_3A5C...PREFIX_VEX_3A5F,
+ PREFIX_VEX_3A68...PREFIX_VEX_3A6F and
+ PREFIX_VEX_3A78...PREFIX_VEX_3A7F. Add
+ PREFIX_VEX_3896...PREFIX_VEX_389F,
+ PREFIX_VEX_38A6...PREFIX_VEX_38AF and
+ PREFIX_VEX_38B6...PREFIX_VEX_38BF.
(vex_table): Likewise.
- (vex_len_table): Likewise.
- (OP_REG_VexI4): Likewise.
- (vex_cmp_op): Likewise.
- (pclmul_op): Likewise.
- (vpermil2_op): Likewise.
- (m_mode): Updated.
- (es_reg): Likewise.
- (PREFIX_0F38F0): Likewise.
- (PREFIX_0F3A60): Likewise.
- (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
- (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
- and PREFIX_VEX_XXX entries.
- (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
- (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
- PREFIX_0F3ADF.
- (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
- Add MOD_VEX_XXX entries.
- (ckprefix): Initialize rex_original and rex_ignored. Store the
- REX byte in rex_original.
- (get_valid_dis386): Handle the implicit prefix in VEX prefix
- bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
- (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
- calling get_valid_dis386. Use rex_original and rex_ignored when
- printing out REX.
- (putop): Handle "XY".
- (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
- ymmq_mode.
- (OP_E_extended): Updated to use OP_E_register and
- OP_E_memory.
- (OP_XMM): Handle VEX.
- (OP_EX): Likewise.
- (XMM_Fixup): Likewise.
- (CMP_Fixup): Use ARRAY_SIZE.
-
- * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
- CPU_FMA_FLAGS and CPU_AVX_FLAGS.
- (operand_type_init): Add OPERAND_TYPE_REGYMM and
- OPERAND_TYPE_VEX_IMM4.
- (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
- (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
- VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
- VexImmExt and SSE2AVX.
- (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
-
- * i386-opc.h (CpuAVX): New.
- (CpuAES): Likewise.
- (CpuCLMUL): Likewise.
- (CpuFMA): Likewise.
- (Vex): Likewise.
- (Vex256): Likewise.
- (VexNDS): Likewise.
- (VexNDD): Likewise.
- (VexW0): Likewise.
- (VexW1): Likewise.
- (Vex0F): Likewise.
- (Vex0F38): Likewise.
- (Vex0F3A): Likewise.
- (Vex3Sources): Likewise.
- (VexImmExt): Likewise.
- (SSE2AVX): Likewise.
- (RegYMM): Likewise.
- (Ymmword): Likewise.
- (Vex_Imm4): Likewise.
- (Implicit1stXmm0): Likewise.
- (CpuXsave): Updated.
- (CpuLM): Likewise.
- (ByteOkIntel): Likewise.
- (OldGcc): Likewise.
- (Control): Likewise.
- (Unspecified): Likewise.
- (OTMax): Likewise.
- (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
- (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
- vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
- vex3sources, veximmext and sse2avx.
- (i386_operand_type): Add regymm, ymmword and vex_imm4.
-
- * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
-
- * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
-
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
-
- From Robin Getz <robin.getz@analog.com>
- * bfin-dis.c (bu32): Typedef.
- (enum const_forms_t): Add c_uimm32 and c_huimm32.
- (constant_formats[]): Add uimm32 and huimm16.
- (fmtconst_val): New.
- (uimm32): Define.
- (huimm32): Define.
- (imm16_val): Define.
- (luimm16_val): Define.
- (struct saved_state): Define.
- (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
- A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
- LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
- (get_allreg): New.
- (decode_LDIMMhalf_0): Print out the whole register value.
-
- From Jie Zhang <jie.zhang@analog.com>
- * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
- multiply and multiply-accumulate to data register instruction.
-
- * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
- c_imm32, c_huimm32e): Define.
- (constant_formats): Add flags for printing decimal, leading spaces, and
- exact symbols.
- (comment, parallel): Add global flags in all disassembly.
- (fmtconst): Take advantage of new flags, and print default in hex.
- (fmtconst_val): Likewise.
- (decode_macfunc): Be consistant with spaces, tabs, comments,
- capitalization in disassembly, fix minor coding style issues.
- (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
- (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
- decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
- decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
- decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
- decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
- decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
- decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
- decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
- decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
- _print_insn_bfin, print_insn_bfin): Likewise.
-
-2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
+ (vex_len_table): Remove VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2
+ and VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2.
+ (putop): Support "%XW".
+ (intel_operand_size): Handle vex_w_dq_mode.
- * aclocal.m4: Regenerate.
- * configure: Likewise.
- * Makefile.in: Likewise.
+ * i386-opc.h (VexNDS): Add a comment for VEX NDS and VEX DDS.
-2008-03-13 Alan Modra <amodra@bigpond.net.au>
-
- * Makefile.am: Run "make dep-am".
- * Makefile.in: Regenerate.
- * configure: Regenerate.
-
-2008-03-07 Alan Modra <amodra@bigpond.net.au>
-
- * ppc-opc.c (powerpc_opcodes): Order and format.
-
-2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
+ * i386-opc.tbl: Remove vpermil2pd/vpermil2ps and old FMA
+ instructions. Add new FMA instructions.
* i386-tbl.h: Regenerated.
-2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Disallow 16-bit near indirect branches for
- x86-64.
- * i386-tbl.h: Regenerated.
-
-2008-02-21 Jan Beulich <jbeulich@novell.com>
-
- * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
- and Fword for far indirect jmp. Allow Reg16 and Word for near
- indirect jmp on x86-64. Disallow Fword for lcall.
- * i386-tbl.h: Re-generate.
-
-2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
-
- * cr16-opc.c (cr16_num_optab): Defined
-
-2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
- * i386-init.h: Regenerated.
-
-2008-02-14 Nick Clifton <nickc@redhat.com>
-
- PR binutils/5524
- * configure.in (SHARED_LIBADD): Select the correct host specific
- file extension for shared libraries.
- * configure: Regenerate.
-
-2008-02-13 Jan Beulich <jbeulich@novell.com>
-
- * i386-opc.h (RegFlat): New.
- * i386-reg.tbl (flat): Add.
- * i386-tbl.h: Re-generate.
-
-2008-02-13 Jan Beulich <jbeulich@novell.com>
-
- * i386-dis.c (a_mode): New.
- (cond_jump_mode): Adjust.
- (Ma): Change to a_mode.
- (intel_operand_size): Handle a_mode.
- * i386-opc.tbl: Allow Dword and Qword for bound.
- * i386-tbl.h: Re-generate.
-
-2008-02-13 Jan Beulich <jbeulich@novell.com>
-
- * i386-gen.c (process_i386_registers): Process new fields.
- * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
- unsigned char. Add dw2_regnum and Dw2Inval.
- * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
- register names.
- * i386-tbl.h: Re-generate.
-
-2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
- * i386-init.h: Updated.
-
-2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (cpu_flags): Add CpuXsave.
-
- * i386-opc.h (CpuXsave): New.
- (CpuLM): Updated.
- (i386_cpu_flags): Add cpuxsave.
-
- * i386-dis.c (MOD_0FAE_REG_4): New.
- (RM_0F01_REG_2): Likewise.
- (MOD_0FAE_REG_5): Updated.
- (RM_0F01_REG_3): Likewise.
- (reg_table): Use MOD_0FAE_REG_4.
- (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
- for xrstor.
- (rm_table): Add RM_0F01_REG_2.
-
- * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2008-02-11 Jan Beulich <jbeulich@novell.com>
-
- * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
- Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
- * i386-tbl.h: Re-generate.
-
-2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
-
- PR 5715
- * configure: Regenerated.
-
-2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
-
- * mips-dis.c: Update copyright.
- (mips_arch_choices): Add Octeon.
- * mips-opc.c: Update copyright.
- (IOCT): New macro.
- (mips_builtin_opcodes): Add Octeon instruction synciobdma.
-
-2008-01-29 Alan Modra <amodra@bigpond.net.au>
-
- * ppc-opc.c: Support optional L form mtmsr.
-
-2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (OP_E_extended): Handle r12 like rsp.
-
-2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
- * i386-init.h: Regenerated.
-
-2008-01-23 Tristan Gingold <gingold@adacore.com>
-
- * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
- ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
-
-2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
- (cpu_flags): Likewise.
-
- * i386-opc.h (CpuMMX2): Removed.
- (CpuSSE): Updated.
-
- * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
- CPU_SMX_FLAGS.
- * i386-init.h: Regenerated.
-
-2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Use Qword on movddup.
- * i386-tbl.h: Regenerated.
-
-2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
- * i386-tbl.h: Regenerated.
-
-2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (Mx): New.
- (PREFIX_0FC3): Likewise.
- (PREFIX_0FC7_REG_6): Updated.
- (dis386_twobyte): Use PREFIX_0FC3.
- (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
- Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
- movntss.
-
-2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (opcode_modifiers): Add IntelSyntax.
- (operand_types): Add Mem.
-
- * i386-opc.h (IntelSyntax): New.
- * i386-opc.h (Mem): New.
- (Byte): Updated.
- (Opcode_Modifier_Max): Updated.
- (i386_opcode_modifier): Add intelsyntax.
- (i386_operand_type): Add mem.
-
- * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
- instructions.
-
- * i386-reg.tbl: Add size for accumulator.
-
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.h (Byte): Fix a typo.
-
-2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/5534
- * i386-gen.c (operand_type_init): Add Dword to
- OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
- (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
- Qword and Xmmword.
- (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
- Xmmword, Unspecified and Anysize.
- (set_bitfield): Make Mmword an alias of Qword. Make Oword
- an alias of Xmmword.
-
- * i386-opc.h (CheckSize): Removed.
- (Byte): Updated.
- (Word): Likewise.
- (Dword): Likewise.
- (Qword): Likewise.
- (Xmmword): Likewise.
- (FWait): Updated.
- (OTMax): Likewise.
- (i386_opcode_modifier): Remove checksize, byte, word, dword,
- qword and xmmword.
- (Fword): New.
- (TBYTE): Likewise.
- (Unspecified): Likewise.
- (Anysize): Likewise.
- (i386_operand_type): Add byte, word, dword, fword, qword,
- tbyte xmmword, unspecified and anysize.
-
- * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
- Tbyte, Xmmword, Unspecified and Anysize.
-
- * i386-reg.tbl: Add size for accumulator.
-
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
- (REG_0F18): Updated.
- (reg_table): Updated.
- (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
- (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
-
-2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (set_bitfield): Use fail () on error.
-
-2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (lineno): New.
- (filename): Likewise.
- (set_bitfield): Report filename and line numer on error.
- (process_i386_opcodes): Set filename and update lineno.
- (process_i386_registers): Likewise.
-
-2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
- ATTSyntax.
-
- * i386-opc.h (IntelMnemonic): Renamed to ..
- (ATTSyntax): This
- (Opcode_Modifier_Max): Updated.
- (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
- and intelsyntax.
-
- * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
- on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
- * i386-tbl.h: Regenerated.
-
-2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c: Update copyright to 2008.
- * i386-opc.h: Likewise.
- * i386-opc.tbl: Likewise.
-
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
- pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
- * i386-tbl.h: Regenerated.
-
-2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
- CpuSSE4_2_Or_ABM.
- (cpu_flags): Likewise.
-
- * i386-opc.h (CpuSSE4_1_Or_5): Removed.
- (CpuSSE4_2_Or_ABM): Likewise.
- (CpuLM): Updated.
- (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
-
- * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
- Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
- and CpuPadLock, respectively.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (opcode_modifiers): Remove No_xSuf.
-
- * i386-opc.h (No_xSuf): Removed.
- (CheckSize): Updated.
-
- * i386-tbl.h: Regenerated.
-
-2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
- CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
- CPU_SSE5_FLAGS.
- (cpu_flags): Add CpuSSE4_2_Or_ABM.
-
- * i386-opc.h (CpuSSE4_2_Or_ABM): New.
- (CpuLM): Updated.
- (i386_cpu_flags): Add cpusse4_2_or_abm.
-
- * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
- CpuABM|CpuSSE4_2 on popcnt.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.h: Update comments.
-
-2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
- * i386-opc.h: Likewise.
- * i386-opc.tbl: Likewise.
-
-2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/5534
- * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
- Byte, Word, Dword, QWord and Xmmword.
-
- * i386-opc.h (No_xSuf): New.
- (CheckSize): Likewise.
- (Byte): Likewise.
- (Word): Likewise.
- (Dword): Likewise.
- (QWord): Likewise.
- (Xmmword): Likewise.
- (FWait): Updated.
- (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
- Dword, QWord and Xmmword.
-
- * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
- used.
- * i386-tbl.h: Regenerated.
-
-2008-01-02 Mark Kettenis <kettenis@gnu.org>
+2009-01-02 Matthias Klose <doko@ubuntu.com>
- * m88k-dis.c (instructions): Fix fcvt.* instructions.
- From Miod Vallat.
+ * or32-opc.c (or32_print_register, or32_print_immediate,
+ disassemble_insn): Don't rely on undefined sprintf behaviour.
-For older changes see ChangeLog-2007
+For older changes see ChangeLog-2008
\f
Local Variables:
mode: change-log
--- /dev/null
+2008-12-30 Martin Schwidefsky <schwidefskyy@de.ibm.com>
+
+ * s390-opc.txt: Add ptff instruction.
+
+2008-12-24 Jan Kratochvil <jan.kratochvil@redhat.com>
+
+ * Makefile.am (CFILES, ALL_MACHINES): Add LM32 source and object files.
+ * Makefile.in: Regenerate.
+
+2008-12-23 Jon Beniston <jon@beniston.com>
+
+ * Makefile.am: Add LM32 object files and dependencies.
+ * Makefile.in: Regenerate.
+ * configure.in: Add LM32 target.
+ * configure: Regenerate.
+ * disassemble.c: Add LM32 disassembler.
+ * cgen-asm.in: Update copyright year.
+ * cgen-dis.in: Update copyright year.
+ * cgen-ibld.in: Update copyright year.
+ * lm32-asm.c: New file.
+ * lm32-desc.c: New file.
+ * lm32-desc.h: New file.
+ * lm32-dis.c: New file.
+ * lm32-ibld.c: New file.
+ * lm32-opc.c: New file.
+ * lm32-opc.h: New file.
+ * lm32-opinst.c: New file.
+
+2008-12-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (EXdS): New.
+ (EXdVexS): Likewise.
+ (EXqVexS): Likewise.
+ (d_swap_mode): Likewise.
+ (q_mode): Updated.
+ (prefix_table): Use EXdS on movss and EXqS on movsd.
+ (vex_len_table): Use EXdVexS on vmovss and EXqVexS on vmovsd.
+ (intel_operand_size): Handle d_swap_mode.
+ (OP_EX): Likewise.
+
+ * i386-opc.h (S): Update comments.
+
+ * i386-opc.tbl: Add S to movss, movsd, vmovss and vmovsd.
+ * i386-tbl.h: Regenerated.
+
+2008-12-23 Nick Clifton <nickc@redhat.com>
+
+ * po/ga.po: Updated Irish translation.
+
+2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (EbS): New.
+ (EvS): Likewise.
+ (EMS): Likewise.
+ (EXqS): Likewise.
+ (EXxS): Likewise.
+ (b_swap_mode): Likewise.
+ (v_swap_mode): Likewise.
+ (q_swap_mode): Likewise.
+ (x_swap_mode): Likewise.
+ (v_mode): Updated.
+ (w_mode): Likewise.
+ (t_mode): Likewise.
+ (xmm_mode): Likewise.
+ (swap_operand): Likewise.
+ (dis386): Use EbS on movB. Use EvS on moveS.
+ (dis386_twobyte): Use EXxS on movapX.
+ (prefix_table): Use EXxS on movups, movupd, movdqu, movdqa,
+ vmovups, vmovdqu, vmovdqa. Use EMS and EXqS on movq.
+ (vex_table): Use EXxS on vmovapX.
+ (vex_len_table): Use EXqS on vmovq.
+ (intel_operand_size): Handle b_swap_mode, v_swap_mode,
+ q_swap_mode and x_swap_mode.
+ (OP_E_register): Handle b_swap_mode and v_swap_mode.
+ (OP_EM): Handle v_swap_mode.
+ (OP_EX): x_swap_mode and q_swap_mode.
+
+ * i386-gen.c (opcode_modifiers): Add S.
+
+ * i386-opc.h (S): New.
+ (Modrm): Updated.
+ (i386_opcode_modifier): Add s.
+
+ * i386-opc.tbl: Add S to movapd, movaps, movdqa, movdqu, movq,
+ movupd, movups, vmovapd, vmovaps, vmovdqa, vmovdqu and vmovq.
+ * i386-tbl.h: Regenerated.
+
+2008-12-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (mnemonicendp): New.
+ (op): Likewise.
+ (print_insn): Use mnemonicendp.
+ (OP_3DNowSuffix): Likewise.
+ (CMP_Fixup): Likewise.
+ (CMPXCHG8B_Fixup): Likewise.
+ (CRC32_Fixup): Likewise.
+ (OP_DREX_FCMP): Likewise.
+ (OP_DREX_ICMP): Likewise.
+ (VZERO_Fixup): Likewise.
+ (VCMP_Fixup): Likewise.
+ (PCLMUL_Fixup): Likewise.
+ (VPERMIL2_Fixup): Likewise.
+ (MOVBE_Fixup): Likewise.
+ (putop): Update mnemonicendp.
+ (oappend): Use stpcpy.
+ (simd_cmp_op): Changed to struct op.
+ (vex_cmp_op): Likewise.
+ (pclmul_op): Likewise.
+ (vpermil2_op): Likewise.
+
+2008-12-18 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
+
+ * configure: Regenerate.
+
+2008-12-15 Richard Earnshaw <rearnsha@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): Disassemble VFP instructions using
+ unified syntax.
+
+2008-12-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Move VexNDS before VexNDD.
+
+2008-12-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (putop): Remove strayed comments.
+
+2008-12-04 Ben Elliston <bje@au.ibm.com>
+
+ * ppc-dis.c (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE
+ for -Mbooke.
+ (print_ppc_disassembler_options): Update usage.
+ * ppc-opc.c (DE, DES, DEO, DE_MASK): Remove.
+ (BOOKE64): Remove.
+ (PPCCHLK64): Likewise.
+ (powerpc_opcodes): Remove all BOOKE64 instructions.
+
+2008-11-28 Joshua Kinard <kumba@gentoo.org>
+
+ * mips-dis.c (mips_arch_choices): Add r14000, r16000.
+
+2008-11-27 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+ * cr16-dis.c (match_opcode): Truncate mcode to 32 bit and
+ adjusted the mask for 32-bit branch instruction.
+
+2008-11-27 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc-opc.c (extract_sprg): Correct operand range check.
+
+2008-11-26 Andreas Schwab <schwab@suse.de>
+
+ * m68k-dis.c (NEXTBYTE, NEXTWORD, NEXTLONG, NEXTULONG, NEXTSINGLE)
+ (NEXTDOUBLE, NEXTEXTEND, NEXTPACKED): Fix error handling.
+ (save_printer, save_print_address): Remove.
+ (fetch_data): Don't use them.
+ (match_insn_m68k): Always restore printing functions.
+ (print_insn_m68k): Don't save/restore printing functions.
+
+2008-11-25 Nick Clifton <nickc@redhat.com>
+
+ * m68k-dis.c: Rewrite to remove use of setjmp/longjmp.
+
+2008-11-18 Catherine Moore <clm@codesourcery.com>
+
+ * arm-dis.c (coprocessor_opcodes): Add half-precision vcvt
+ instructions.
+ (neon_opcodes): Likewise.
+ (print_insn_coprocessor): Print 't' or 'b' for vcvt
+ instructions.
+
+2008-11-14 Tristan Gingold <gingold@adacore.com>
+
+ * makefile.vms (OBJS): Update list of objects.
+ (DEFS): Update
+ (CFLAGS): Update.
+
+2008-11-06 Chao-ying Fu <fu@mips.com>
+
+ * mips-opc.c (synciobdma, syncs, syncw, syncws): Move these
+ before sync.
+ (sync): New instruction with 5-bit sync type.
+ * mips-dis.c (print_insn_args): Add case '1' to print 5-bit values.
+
+2008-11-06 Nick Clifton <nickc@redhat.com>
+
+ * avr-dis.c: Replace uses of sprintf without a format string with
+ calls to strcpy.
+
+2008-11-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add cmovpe and cmovpo.
+ * i386-tbl.h: Regenerated.
+
+2008-10-22 Nick Clifton <nickc@redhat.com>
+
+ PR 6937
+ * configure.in (SHARED_LIBADD): Revert previous change.
+ Add a comment explaining why.
+ (SHARED_DEPENDENCIES): Revert previous change.
+ * configure: Regenerate.
+
+2008-10-10 Nick Clifton <nickc@redhat.com>
+
+ PR 6937
+ * configure.in (SHARED_LIBADD): Add libiberty.a.
+ (SHARED_DEPENDENCIES): Add libiberty.a.
+
+2008-09-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c: Include "hashtab.h".
+ (next_field): Take a new argument, last. Check last.
+ (process_i386_cpu_flag): Updated.
+ (process_i386_opcode_modifier): Likewise.
+ (process_i386_operand_type): Likewise.
+ (process_i386_registers): Likewise.
+ (output_i386_opcode): New.
+ (opcode_hash_entry): Likewise.
+ (opcode_hash_table): Likewise.
+ (opcode_hash_hash): Likewise.
+ (opcode_hash_eq): Likewise.
+ (process_i386_opcodes): Use opcode hash table and opcode array.
+
+2008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * s390-opc.txt (stdy, stey): Fix description
+
+2008-09-30 Alan Modra <amodra@bigpond.net.au>
+
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+
+2008-09-29 H.J. Lu <hongjiu.lu@intel.com>
+
+ * aclocal.m4: Regenerated.
+ * configure: Likewise.
+ * Makefile.in: Likewise.
+
+2008-09-29 Nick Clifton <nickc@redhat.com>
+
+ * po/vi.po: Updated Vietnamese translation.
+ * po/fr.po: Updated French translation.
+
+2008-09-26 Florian Krohm <fkrohm@us.ibm.com>
+
+ * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
+ (cfxr, cfdr, cfer, clclu): Add esa flag.
+ (sqd): Instruction added.
+ (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
+ * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
+
+2008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
+
+ * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
+ (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
+
+2008-09-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
+ * i386-tbl.h: Regenerated.
+
+2008-08-28 Jan Beulich <jbeulich@novell.com>
+
+ * i386-dis.c (dis386): Adjust far return mnemonics.
+ * i386-opc.tbl: Add retf.
+ * i386-tbl.h: Re-generate.
+
+2008-08-28 Jan Beulich <jbeulich@novell.com>
+
+ * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
+
+2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
+ * ia64-gen.c (lookup_specifier): Likewise.
+
+ * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
+ * ia64-raw.tbl: Likewise.
+ * ia64-waw.tbl: Likewise.
+ * ia64-asmtab.c: Regenerated.
+
+2008-08-27 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Correct fidivr operand size.
+
+ * i386-tbl.h: Regenerated.
+
+2008-08-24 Alan Modra <amodra@bigpond.net.au>
+
+ * configure.in: Update a number of obsolete autoconf macros.
+ * aclocal.m4: Regenerate.
+
+2008-08-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ AVX Programming Reference (August, 2008)
+ * i386-dis.c (PREFIX_VEX_38DB): New.
+ (PREFIX_VEX_38DC): Likewise.
+ (PREFIX_VEX_38DD): Likewise.
+ (PREFIX_VEX_38DE): Likewise.
+ (PREFIX_VEX_38DF): Likewise.
+ (PREFIX_VEX_3ADF): Likewise.
+ (VEX_LEN_38DB_P_2): Likewise.
+ (VEX_LEN_38DC_P_2): Likewise.
+ (VEX_LEN_38DD_P_2): Likewise.
+ (VEX_LEN_38DE_P_2): Likewise.
+ (VEX_LEN_38DF_P_2): Likewise.
+ (VEX_LEN_3ADF_P_2): Likewise.
+ (PREFIX_VEX_3A04): Updated.
+ (VEX_LEN_3A06_P_2): Likewise.
+ (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
+ PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
+ (x86_64_table): Likewise.
+ (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
+ VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
+ VEX_LEN_3ADF_P_2.
+
+ * i386-opc.tbl: Add AES + AVX instructions.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
+ * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
+
+2008-08-15 Alan Modra <amodra@bigpond.net.au>
+
+ PR 6526
+ * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
+ * Makefile.in: Regenerate.
+ * aclocal.m4: Regenerate.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+
+2008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+ PR 6825
+ * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
+
+2008-08-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add syscall and sysret for Cpu64.
+
+ * i386-tbl.h: Regenerated.
+
+2008-08-04 Alan Modra <amodra@bigpond.net.au>
+
+ * Makefile.am (POTFILES.in): Set LC_ALL=C.
+ * Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
+ (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
+ (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
+ * ppc-opc.c (insert_xt6): New static function.
+ (extract_xt6): Likewise.
+ (insert_xa6): Likewise.
+ (extract_xa6: Likewise.
+ (insert_xb6): Likewise.
+ (extract_xb6): Likewise.
+ (insert_xb6s): Likewise.
+ (extract_xb6s): Likewise.
+ (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
+ XX3DM_MASK, PPCVSX): New.
+ (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
+ "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
+
+2008-08-01 Pedro Alves <pedro@codesourcery.com>
+
+ * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
+ * Makefile.in: Regenerate.
+
+2008-08-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-reg.tbl: Use Dw2Inval on AVX registers.
+ * i386-tbl.h: Regenerated.
+
+2008-07-30 Michael J. Eager <eager@eagercon.com>
+
+ * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
+ * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
+ (insert_sprg, PPC405): Use PPC_OPCODE_405.
+ (powerpc_opcodes): Add Xilinx APU related opcodes.
+
+2008-07-30 Alan Modra <amodra@bigpond.net.au>
+
+ * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
+
+2008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
+
+2008-07-07 Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips-opc.c (CP): New macro.
+ (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
+ membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
+ dmtc2 Octeon instructions.
+
+2008-07-07 Stan Shebs <stan@codesourcery.com>
+
+ * dis-init.c (init_disassemble_info): Init endian_code field.
+ * arm-dis.c (print_insn): Disassemble code according to
+ setting of endian_code.
+ (print_insn_big_arm): Detect when BE8 extension flag has been set.
+
+2008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
+ for ELF symbols.
+
+2008-06-25 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-dis.c (powerpc_init_dialect): Handle -M464.
+ (print_ppc_disassembler_options): Likewise.
+ * ppc-opc.c (PPC464): Define.
+ (powerpc_opcodes): Add mfdcrux and mtdcrux.
+
+2008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
+
+ * configure: Regenerate.
+
+2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-dis.c (print_insn_powerpc): Update prototye to use new
+ ppc_cpu_t typedef.
+ (struct dis_private): New.
+ (POWERPC_DIALECT): New define.
+ (powerpc_dialect): Renamed to...
+ (powerpc_init_dialect): This. Update to use ppc_cpu_t and
+ struct dis_private.
+ (print_insn_big_powerpc): Update for using structure in
+ info->private_data.
+ (print_insn_little_powerpc): Likewise.
+ (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
+ (skip_optional_operands): Likewise.
+ (print_insn_powerpc): Likewise. Remove initialization of dialect.
+ * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
+ extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
+ extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
+ extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
+ insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
+ insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
+ insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
+ param to be of type ppc_cpu_t. Update prototype.
+
+2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
+ +s, +S.
+ * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
+ baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
+ syncw, syncws, vm3mulu, vm0 and vmulu.
+
+ * mips-dis.c (print_insn_args): Handle field descriptor +Q.
+ * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
+ seqi, sne and snei.
+
+2008-05-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add vmovd with 64bit operand.
+ * i386-tbl.h: Regenerated.
+
+2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
+
+ * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
+
+2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
+ * i386-tbl.h: Regenerated.
+
+2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/6517
+ * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
+ into 32bit and 64bit. Remove Reg64|Qword and add
+ IgnoreSize|No_qSuf on 32bit version.
+ * i386-tbl.h: Regenerated.
+
+2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
+ * i386-tbl.h: Regenerated.
+
+2008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+ * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
+
+2008-05-14 Alan Modra <amodra@bigpond.net.au>
+
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+
+2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (MOVBE_Fixup): New.
+ (Mo): Likewise.
+ (PREFIX_0F3880): Likewise.
+ (PREFIX_0F3881): Likewise.
+ (PREFIX_0F38F0): Updated.
+ (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
+ PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
+ (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
+
+ * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
+ CPU_EPT_FLAGS.
+ (cpu_flags): Add CpuMovbe and CpuEPT.
+
+ * i386-opc.h (CpuMovbe): New.
+ (CpuEPT): Likewise.
+ (CpuLM): Updated.
+ (i386_cpu_flags): Add cpumovbe and cpuept.
+
+ * i386-opc.tbl: Add entries for movbe and EPT instructions.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2008-04-29 Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
+ the two drem and the two dremu macros.
+
+2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
+ instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
+ cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
+ INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
+
+2008-04-25 David S. Miller <davem@davemloft.net>
+
+ * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
+ instead of %sys_tick_cmpr, as suggested in architecture manuals.
+
+2008-04-23 Paolo Bonzini <bonzini@gnu.org>
+
+ * aclocal.m4: Regenerate.
+ * configure: Regenerate.
+
+2008-04-23 David S. Miller <davem@davemloft.net>
+
+ * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
+ extended values.
+ (prefetch_table): Add missing values.
+
+2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Add NoAVX.
+
+ * i386-opc.h (NoAVX): New.
+ (OldGcc): Updated.
+ (i386_opcode_modifier): Add noavx.
+
+ * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
+ instructions which don't have AVX equivalent.
+ * i386-tbl.h: Regenerated.
+
+2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (OP_VEX_FMA): New.
+ (OP_EX_VexImmW): Likewise.
+ (VexFMA): Likewise.
+ (Vex128FMA): Likewise.
+ (EXVexImmW): Likewise.
+ (get_vex_imm8): Likewise.
+ (OP_EX_VexReg): Likewise.
+ (vex_i4_done): Renamed to ...
+ (vex_w_done): This.
+ (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
+ and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
+ FMA instructions.
+ (print_insn): Updated.
+ (OP_EX_VexW): Rewrite to swap register in VEX with EX.
+ (OP_REG_VexI4): Check invalid high registers.
+
+2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+ Michael Meissner <michael.meissner@amd.com>
+
+ * i386-opc.tbl: Fix protX to allow memory in the middle operand.
+ * i386-tbl.h: Regenerate from i386-opc.tbl.
+
+2008-04-14 Edmar Wienskoski <edmar@freescale.com>
+
+ * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
+ accept Power E500MC instructions.
+ (print_ppc_disassembler_options): Document -Me500mc.
+ * ppc-opc.c (DUIS, DUI, T): New.
+ (XRT, XRTRA): Likewise.
+ (E500MC): Likewise.
+ (powerpc_opcodes): Add new Power E500MC instructions.
+
+2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * s390-dis.c (init_disasm): Evaluate disassembler_options.
+ (print_s390_disassembler_options): New function.
+ * disassemble.c (disassembler_usage): Invoke
+ print_s390_disassembler_options.
+
+2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
+ of local variables used for mnemonic parsing: prefix, suffix and
+ number.
+
+2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
+ extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
+ (s390_crb_extensions): New extensions table.
+ (insertExpandedMnemonic): Handle '$' tag.
+ * s390-opc.txt: Remove conditional jump variants which can now
+ be expanded automatically.
+ Replace '*' tag with '$' in the compare and branch instructions.
+
+2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
+ (PREFIX_VEX_3AXX): Likewis.
+
+2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Remove 4 extra blank lines.
+
+2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
+ with CPU_PCLMUL_FLAGS/CpuPCLMUL.
+ (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
+ * i386-opc.tbl: Likewise.
+
+ * i386-opc.h (CpuCLMUL): Renamed to ...
+ (CpuPCLMUL): This.
+ (CpuFMA): Updated.
+ (i386_cpu_flags): Replace cpuclmul with cpupclmul.
+
+ * i386-init.h: Regenerated.
+
+2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (OP_E_register): New.
+ (OP_E_memory): Likewise.
+ (OP_VEX): Likewise.
+ (OP_EX_Vex): Likewise.
+ (OP_EX_VexW): Likewise.
+ (OP_XMM_Vex): Likewise.
+ (OP_XMM_VexW): Likewise.
+ (OP_REG_VexI4): Likewise.
+ (PCLMUL_Fixup): Likewise.
+ (VEXI4_Fixup): Likewise.
+ (VZERO_Fixup): Likewise.
+ (VCMP_Fixup): Likewise.
+ (VPERMIL2_Fixup): Likewise.
+ (rex_original): Likewise.
+ (rex_ignored): Likewise.
+ (Mxmm): Likewise.
+ (XMM): Likewise.
+ (EXxmm): Likewise.
+ (EXxmmq): Likewise.
+ (EXymmq): Likewise.
+ (Vex): Likewise.
+ (Vex128): Likewise.
+ (Vex256): Likewise.
+ (VexI4): Likewise.
+ (EXdVex): Likewise.
+ (EXqVex): Likewise.
+ (EXVexW): Likewise.
+ (EXdVexW): Likewise.
+ (EXqVexW): Likewise.
+ (XMVex): Likewise.
+ (XMVexW): Likewise.
+ (XMVexI4): Likewise.
+ (PCLMUL): Likewise.
+ (VZERO): Likewise.
+ (VCMP): Likewise.
+ (VPERMIL2): Likewise.
+ (xmm_mode): Likewise.
+ (xmmq_mode): Likewise.
+ (ymmq_mode): Likewise.
+ (vex_mode): Likewise.
+ (vex128_mode): Likewise.
+ (vex256_mode): Likewise.
+ (USE_VEX_C4_TABLE): Likewise.
+ (USE_VEX_C5_TABLE): Likewise.
+ (USE_VEX_LEN_TABLE): Likewise.
+ (VEX_C4_TABLE): Likewise.
+ (VEX_C5_TABLE): Likewise.
+ (VEX_LEN_TABLE): Likewise.
+ (REG_VEX_XX): Likewise.
+ (MOD_VEX_XXX): Likewise.
+ (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
+ (PREFIX_0F3A44): Likewise.
+ (PREFIX_0F3ADF): Likewise.
+ (PREFIX_VEX_XXX): Likewise.
+ (VEX_OF): Likewise.
+ (VEX_OF38): Likewise.
+ (VEX_OF3A): Likewise.
+ (VEX_LEN_XXX): Likewise.
+ (vex): Likewise.
+ (need_vex): Likewise.
+ (need_vex_reg): Likewise.
+ (vex_i4_done): Likewise.
+ (vex_table): Likewise.
+ (vex_len_table): Likewise.
+ (OP_REG_VexI4): Likewise.
+ (vex_cmp_op): Likewise.
+ (pclmul_op): Likewise.
+ (vpermil2_op): Likewise.
+ (m_mode): Updated.
+ (es_reg): Likewise.
+ (PREFIX_0F38F0): Likewise.
+ (PREFIX_0F3A60): Likewise.
+ (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
+ (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
+ and PREFIX_VEX_XXX entries.
+ (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
+ (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
+ PREFIX_0F3ADF.
+ (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
+ Add MOD_VEX_XXX entries.
+ (ckprefix): Initialize rex_original and rex_ignored. Store the
+ REX byte in rex_original.
+ (get_valid_dis386): Handle the implicit prefix in VEX prefix
+ bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
+ (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
+ calling get_valid_dis386. Use rex_original and rex_ignored when
+ printing out REX.
+ (putop): Handle "XY".
+ (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
+ ymmq_mode.
+ (OP_E_extended): Updated to use OP_E_register and
+ OP_E_memory.
+ (OP_XMM): Handle VEX.
+ (OP_EX): Likewise.
+ (XMM_Fixup): Likewise.
+ (CMP_Fixup): Use ARRAY_SIZE.
+
+ * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
+ CPU_FMA_FLAGS and CPU_AVX_FLAGS.
+ (operand_type_init): Add OPERAND_TYPE_REGYMM and
+ OPERAND_TYPE_VEX_IMM4.
+ (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
+ (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
+ VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
+ VexImmExt and SSE2AVX.
+ (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
+
+ * i386-opc.h (CpuAVX): New.
+ (CpuAES): Likewise.
+ (CpuCLMUL): Likewise.
+ (CpuFMA): Likewise.
+ (Vex): Likewise.
+ (Vex256): Likewise.
+ (VexNDS): Likewise.
+ (VexNDD): Likewise.
+ (VexW0): Likewise.
+ (VexW1): Likewise.
+ (Vex0F): Likewise.
+ (Vex0F38): Likewise.
+ (Vex0F3A): Likewise.
+ (Vex3Sources): Likewise.
+ (VexImmExt): Likewise.
+ (SSE2AVX): Likewise.
+ (RegYMM): Likewise.
+ (Ymmword): Likewise.
+ (Vex_Imm4): Likewise.
+ (Implicit1stXmm0): Likewise.
+ (CpuXsave): Updated.
+ (CpuLM): Likewise.
+ (ByteOkIntel): Likewise.
+ (OldGcc): Likewise.
+ (Control): Likewise.
+ (Unspecified): Likewise.
+ (OTMax): Likewise.
+ (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
+ (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
+ vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
+ vex3sources, veximmext and sse2avx.
+ (i386_operand_type): Add regymm, ymmword and vex_imm4.
+
+ * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
+
+ * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
+
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
+
+ From Robin Getz <robin.getz@analog.com>
+ * bfin-dis.c (bu32): Typedef.
+ (enum const_forms_t): Add c_uimm32 and c_huimm32.
+ (constant_formats[]): Add uimm32 and huimm16.
+ (fmtconst_val): New.
+ (uimm32): Define.
+ (huimm32): Define.
+ (imm16_val): Define.
+ (luimm16_val): Define.
+ (struct saved_state): Define.
+ (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
+ A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
+ LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
+ (get_allreg): New.
+ (decode_LDIMMhalf_0): Print out the whole register value.
+
+ From Jie Zhang <jie.zhang@analog.com>
+ * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
+ multiply and multiply-accumulate to data register instruction.
+
+ * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
+ c_imm32, c_huimm32e): Define.
+ (constant_formats): Add flags for printing decimal, leading spaces, and
+ exact symbols.
+ (comment, parallel): Add global flags in all disassembly.
+ (fmtconst): Take advantage of new flags, and print default in hex.
+ (fmtconst_val): Likewise.
+ (decode_macfunc): Be consistant with spaces, tabs, comments,
+ capitalization in disassembly, fix minor coding style issues.
+ (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
+ (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
+ decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
+ decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
+ decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
+ decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
+ decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
+ decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
+ decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
+ decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
+ _print_insn_bfin, print_insn_bfin): Likewise.
+
+2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
+
+ * aclocal.m4: Regenerate.
+ * configure: Likewise.
+ * Makefile.in: Likewise.
+
+2008-03-13 Alan Modra <amodra@bigpond.net.au>
+
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+
+2008-03-07 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc-opc.c (powerpc_opcodes): Order and format.
+
+2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
+ * i386-tbl.h: Regenerated.
+
+2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Disallow 16-bit near indirect branches for
+ x86-64.
+ * i386-tbl.h: Regenerated.
+
+2008-02-21 Jan Beulich <jbeulich@novell.com>
+
+ * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
+ and Fword for far indirect jmp. Allow Reg16 and Word for near
+ indirect jmp on x86-64. Disallow Fword for lcall.
+ * i386-tbl.h: Re-generate.
+
+2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+ * cr16-opc.c (cr16_num_optab): Defined
+
+2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
+ * i386-init.h: Regenerated.
+
+2008-02-14 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/5524
+ * configure.in (SHARED_LIBADD): Select the correct host specific
+ file extension for shared libraries.
+ * configure: Regenerate.
+
+2008-02-13 Jan Beulich <jbeulich@novell.com>
+
+ * i386-opc.h (RegFlat): New.
+ * i386-reg.tbl (flat): Add.
+ * i386-tbl.h: Re-generate.
+
+2008-02-13 Jan Beulich <jbeulich@novell.com>
+
+ * i386-dis.c (a_mode): New.
+ (cond_jump_mode): Adjust.
+ (Ma): Change to a_mode.
+ (intel_operand_size): Handle a_mode.
+ * i386-opc.tbl: Allow Dword and Qword for bound.
+ * i386-tbl.h: Re-generate.
+
+2008-02-13 Jan Beulich <jbeulich@novell.com>
+
+ * i386-gen.c (process_i386_registers): Process new fields.
+ * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
+ unsigned char. Add dw2_regnum and Dw2Inval.
+ * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
+ register names.
+ * i386-tbl.h: Re-generate.
+
+2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
+ * i386-init.h: Updated.
+
+2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flags): Add CpuXsave.
+
+ * i386-opc.h (CpuXsave): New.
+ (CpuLM): Updated.
+ (i386_cpu_flags): Add cpuxsave.
+
+ * i386-dis.c (MOD_0FAE_REG_4): New.
+ (RM_0F01_REG_2): Likewise.
+ (MOD_0FAE_REG_5): Updated.
+ (RM_0F01_REG_3): Likewise.
+ (reg_table): Use MOD_0FAE_REG_4.
+ (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
+ for xrstor.
+ (rm_table): Add RM_0F01_REG_2.
+
+ * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2008-02-11 Jan Beulich <jbeulich@novell.com>
+
+ * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
+ Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
+ * i386-tbl.h: Re-generate.
+
+2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR 5715
+ * configure: Regenerated.
+
+2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips-dis.c: Update copyright.
+ (mips_arch_choices): Add Octeon.
+ * mips-opc.c: Update copyright.
+ (IOCT): New macro.
+ (mips_builtin_opcodes): Add Octeon instruction synciobdma.
+
+2008-01-29 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc-opc.c: Support optional L form mtmsr.
+
+2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (OP_E_extended): Handle r12 like rsp.
+
+2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
+ * i386-init.h: Regenerated.
+
+2008-01-23 Tristan Gingold <gingold@adacore.com>
+
+ * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
+ ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
+
+2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
+ (cpu_flags): Likewise.
+
+ * i386-opc.h (CpuMMX2): Removed.
+ (CpuSSE): Updated.
+
+ * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
+ CPU_SMX_FLAGS.
+ * i386-init.h: Regenerated.
+
+2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Use Qword on movddup.
+ * i386-tbl.h: Regenerated.
+
+2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
+ * i386-tbl.h: Regenerated.
+
+2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (Mx): New.
+ (PREFIX_0FC3): Likewise.
+ (PREFIX_0FC7_REG_6): Updated.
+ (dis386_twobyte): Use PREFIX_0FC3.
+ (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
+ Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
+ movntss.
+
+2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Add IntelSyntax.
+ (operand_types): Add Mem.
+
+ * i386-opc.h (IntelSyntax): New.
+ * i386-opc.h (Mem): New.
+ (Byte): Updated.
+ (Opcode_Modifier_Max): Updated.
+ (i386_opcode_modifier): Add intelsyntax.
+ (i386_operand_type): Add mem.
+
+ * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
+ instructions.
+
+ * i386-reg.tbl: Add size for accumulator.
+
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.h (Byte): Fix a typo.
+
+2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/5534
+ * i386-gen.c (operand_type_init): Add Dword to
+ OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
+ (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
+ Qword and Xmmword.
+ (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
+ Xmmword, Unspecified and Anysize.
+ (set_bitfield): Make Mmword an alias of Qword. Make Oword
+ an alias of Xmmword.
+
+ * i386-opc.h (CheckSize): Removed.
+ (Byte): Updated.
+ (Word): Likewise.
+ (Dword): Likewise.
+ (Qword): Likewise.
+ (Xmmword): Likewise.
+ (FWait): Updated.
+ (OTMax): Likewise.
+ (i386_opcode_modifier): Remove checksize, byte, word, dword,
+ qword and xmmword.
+ (Fword): New.
+ (TBYTE): Likewise.
+ (Unspecified): Likewise.
+ (Anysize): Likewise.
+ (i386_operand_type): Add byte, word, dword, fword, qword,
+ tbyte xmmword, unspecified and anysize.
+
+ * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
+ Tbyte, Xmmword, Unspecified and Anysize.
+
+ * i386-reg.tbl: Add size for accumulator.
+
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
+ (REG_0F18): Updated.
+ (reg_table): Updated.
+ (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
+ (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
+
+2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (set_bitfield): Use fail () on error.
+
+2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (lineno): New.
+ (filename): Likewise.
+ (set_bitfield): Report filename and line numer on error.
+ (process_i386_opcodes): Set filename and update lineno.
+ (process_i386_registers): Likewise.
+
+2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
+ ATTSyntax.
+
+ * i386-opc.h (IntelMnemonic): Renamed to ..
+ (ATTSyntax): This
+ (Opcode_Modifier_Max): Updated.
+ (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
+ and intelsyntax.
+
+ * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
+ on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
+ * i386-tbl.h: Regenerated.
+
+2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c: Update copyright to 2008.
+ * i386-opc.h: Likewise.
+ * i386-opc.tbl: Likewise.
+
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
+ pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
+ * i386-tbl.h: Regenerated.
+
+2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
+ CpuSSE4_2_Or_ABM.
+ (cpu_flags): Likewise.
+
+ * i386-opc.h (CpuSSE4_1_Or_5): Removed.
+ (CpuSSE4_2_Or_ABM): Likewise.
+ (CpuLM): Updated.
+ (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
+
+ * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
+ Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
+ and CpuPadLock, respectively.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Remove No_xSuf.
+
+ * i386-opc.h (No_xSuf): Removed.
+ (CheckSize): Updated.
+
+ * i386-tbl.h: Regenerated.
+
+2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
+ CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
+ CPU_SSE5_FLAGS.
+ (cpu_flags): Add CpuSSE4_2_Or_ABM.
+
+ * i386-opc.h (CpuSSE4_2_Or_ABM): New.
+ (CpuLM): Updated.
+ (i386_cpu_flags): Add cpusse4_2_or_abm.
+
+ * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
+ CpuABM|CpuSSE4_2 on popcnt.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.h: Update comments.
+
+2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
+ * i386-opc.h: Likewise.
+ * i386-opc.tbl: Likewise.
+
+2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/5534
+ * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
+ Byte, Word, Dword, QWord and Xmmword.
+
+ * i386-opc.h (No_xSuf): New.
+ (CheckSize): Likewise.
+ (Byte): Likewise.
+ (Word): Likewise.
+ (Dword): Likewise.
+ (QWord): Likewise.
+ (Xmmword): Likewise.
+ (FWait): Updated.
+ (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
+ Dword, QWord and Xmmword.
+
+ * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
+ used.
+ * i386-tbl.h: Regenerated.
+
+2008-01-02 Mark Kettenis <kettenis@gnu.org>
+
+ * m88k-dis.c (instructions): Fix fcvt.* instructions.
+ From Miod Vallat.
+
+For older changes see ChangeLog-2007
+\f
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
/* Print i386 instructions for GDB, the GNU debugger.
Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
static void OP_XS (int, int);
static void OP_M (int, int);
static void OP_VEX (int, int);
-static void OP_VEX_FMA (int, int);
static void OP_EX_Vex (int, int);
-static void OP_EX_VexW (int, int);
-static void OP_EX_VexImmW (int, int);
static void OP_XMM_Vex (int, int);
-static void OP_XMM_VexW (int, int);
static void OP_REG_VexI4 (int, int);
static void PCLMUL_Fixup (int, int);
-static void VEXI4_Fixup (int, int);
static void VZERO_Fixup (int, int);
static void VCMP_Fixup (int, int);
-static void VPERMIL2_Fixup (int, int);
static void OP_0f07 (int, int);
static void OP_Monitor (int, int);
static void OP_Mwait (int, int);
#define EXxmm { OP_EX, xmm_mode }
#define EXxmmq { OP_EX, xmmq_mode }
#define EXymmq { OP_EX, ymmq_mode }
+#define EXVexWdq { OP_EX, vex_w_dq_mode }
#define MS { OP_MS, v_mode }
#define XS { OP_XS, v_mode }
#define EMCq { OP_EMC, q_mode }
#define Vex { OP_VEX, vex_mode }
#define Vex128 { OP_VEX, vex128_mode }
#define Vex256 { OP_VEX, vex256_mode }
-#define VexI4 { VEXI4_Fixup, 0}
-#define VexFMA { OP_VEX_FMA, vex_mode }
-#define Vex128FMA { OP_VEX_FMA, vex128_mode }
#define EXdVex { OP_EX_Vex, d_mode }
#define EXdVexS { OP_EX_Vex, d_swap_mode }
#define EXqVex { OP_EX_Vex, q_mode }
#define EXqVexS { OP_EX_Vex, q_swap_mode }
-#define EXVexW { OP_EX_VexW, x_mode }
-#define EXdVexW { OP_EX_VexW, d_mode }
-#define EXqVexW { OP_EX_VexW, q_mode }
-#define EXVexImmW { OP_EX_VexImmW, x_mode }
#define XMVex { OP_XMM_Vex, 0 }
-#define XMVexW { OP_XMM_VexW, 0 }
#define XMVexI4 { OP_REG_VexI4, x_mode }
#define PCLMUL { PCLMUL_Fixup, 0 }
#define VZERO { VZERO_Fixup, 0 }
#define VCMP { VCMP_Fixup, 0 }
-#define VPERMIL2 { VPERMIL2_Fixup, 0 }
/* Used handle "rep" prefix for string instructions. */
#define Xbr { REP_Fixup, eSI_reg }
#define vex128_mode (vex_mode + 1)
/* 256bit vex mode */
#define vex256_mode (vex128_mode + 1)
+/* operand size depends on the VEX.W bit. */
+#define vex_w_dq_mode (vex256_mode + 1)
-#define es_reg (vex256_mode + 1)
+#define es_reg (vex_w_dq_mode + 1)
#define cs_reg (es_reg + 1)
#define ss_reg (cs_reg + 1)
#define ds_reg (ss_reg + 1)
#define PREFIX_VEX_383F (PREFIX_VEX_383E + 1)
#define PREFIX_VEX_3840 (PREFIX_VEX_383F + 1)
#define PREFIX_VEX_3841 (PREFIX_VEX_3840 + 1)
-#define PREFIX_VEX_38DB (PREFIX_VEX_3841 + 1)
+#define PREFIX_VEX_3896 (PREFIX_VEX_3841 + 1)
+#define PREFIX_VEX_3897 (PREFIX_VEX_3896 + 1)
+#define PREFIX_VEX_3898 (PREFIX_VEX_3897 + 1)
+#define PREFIX_VEX_3899 (PREFIX_VEX_3898 + 1)
+#define PREFIX_VEX_389A (PREFIX_VEX_3899 + 1)
+#define PREFIX_VEX_389B (PREFIX_VEX_389A + 1)
+#define PREFIX_VEX_389C (PREFIX_VEX_389B + 1)
+#define PREFIX_VEX_389D (PREFIX_VEX_389C + 1)
+#define PREFIX_VEX_389E (PREFIX_VEX_389D + 1)
+#define PREFIX_VEX_389F (PREFIX_VEX_389E + 1)
+#define PREFIX_VEX_38A6 (PREFIX_VEX_389F + 1)
+#define PREFIX_VEX_38A7 (PREFIX_VEX_38A6 + 1)
+#define PREFIX_VEX_38A8 (PREFIX_VEX_38A7 + 1)
+#define PREFIX_VEX_38A9 (PREFIX_VEX_38A8 + 1)
+#define PREFIX_VEX_38AA (PREFIX_VEX_38A9 + 1)
+#define PREFIX_VEX_38AB (PREFIX_VEX_38AA + 1)
+#define PREFIX_VEX_38AC (PREFIX_VEX_38AB + 1)
+#define PREFIX_VEX_38AD (PREFIX_VEX_38AC + 1)
+#define PREFIX_VEX_38AE (PREFIX_VEX_38AD + 1)
+#define PREFIX_VEX_38AF (PREFIX_VEX_38AE + 1)
+#define PREFIX_VEX_38B6 (PREFIX_VEX_38AF + 1)
+#define PREFIX_VEX_38B7 (PREFIX_VEX_38B6 + 1)
+#define PREFIX_VEX_38B8 (PREFIX_VEX_38B7 + 1)
+#define PREFIX_VEX_38B9 (PREFIX_VEX_38B8 + 1)
+#define PREFIX_VEX_38BA (PREFIX_VEX_38B9 + 1)
+#define PREFIX_VEX_38BB (PREFIX_VEX_38BA + 1)
+#define PREFIX_VEX_38BC (PREFIX_VEX_38BB + 1)
+#define PREFIX_VEX_38BD (PREFIX_VEX_38BC + 1)
+#define PREFIX_VEX_38BE (PREFIX_VEX_38BD + 1)
+#define PREFIX_VEX_38BF (PREFIX_VEX_38BE + 1)
+#define PREFIX_VEX_38DB (PREFIX_VEX_38BF + 1)
#define PREFIX_VEX_38DC (PREFIX_VEX_38DB + 1)
#define PREFIX_VEX_38DD (PREFIX_VEX_38DC + 1)
#define PREFIX_VEX_38DE (PREFIX_VEX_38DD + 1)
#define PREFIX_VEX_3A40 (PREFIX_VEX_3A22 + 1)
#define PREFIX_VEX_3A41 (PREFIX_VEX_3A40 + 1)
#define PREFIX_VEX_3A42 (PREFIX_VEX_3A41 + 1)
-#define PREFIX_VEX_3A48 (PREFIX_VEX_3A42 + 1)
-#define PREFIX_VEX_3A49 (PREFIX_VEX_3A48 + 1)
-#define PREFIX_VEX_3A4A (PREFIX_VEX_3A49 + 1)
+#define PREFIX_VEX_3A4A (PREFIX_VEX_3A42 + 1)
#define PREFIX_VEX_3A4B (PREFIX_VEX_3A4A + 1)
#define PREFIX_VEX_3A4C (PREFIX_VEX_3A4B + 1)
-#define PREFIX_VEX_3A5C (PREFIX_VEX_3A4C + 1)
-#define PREFIX_VEX_3A5D (PREFIX_VEX_3A5C + 1)
-#define PREFIX_VEX_3A5E (PREFIX_VEX_3A5D + 1)
-#define PREFIX_VEX_3A5F (PREFIX_VEX_3A5E + 1)
-#define PREFIX_VEX_3A60 (PREFIX_VEX_3A5F + 1)
+#define PREFIX_VEX_3A60 (PREFIX_VEX_3A4C + 1)
#define PREFIX_VEX_3A61 (PREFIX_VEX_3A60 + 1)
#define PREFIX_VEX_3A62 (PREFIX_VEX_3A61 + 1)
#define PREFIX_VEX_3A63 (PREFIX_VEX_3A62 + 1)
-#define PREFIX_VEX_3A68 (PREFIX_VEX_3A63 + 1)
-#define PREFIX_VEX_3A69 (PREFIX_VEX_3A68 + 1)
-#define PREFIX_VEX_3A6A (PREFIX_VEX_3A69 + 1)
-#define PREFIX_VEX_3A6B (PREFIX_VEX_3A6A + 1)
-#define PREFIX_VEX_3A6C (PREFIX_VEX_3A6B + 1)
-#define PREFIX_VEX_3A6D (PREFIX_VEX_3A6C + 1)
-#define PREFIX_VEX_3A6E (PREFIX_VEX_3A6D + 1)
-#define PREFIX_VEX_3A6F (PREFIX_VEX_3A6E + 1)
-#define PREFIX_VEX_3A78 (PREFIX_VEX_3A6F + 1)
-#define PREFIX_VEX_3A79 (PREFIX_VEX_3A78 + 1)
-#define PREFIX_VEX_3A7A (PREFIX_VEX_3A79 + 1)
-#define PREFIX_VEX_3A7B (PREFIX_VEX_3A7A + 1)
-#define PREFIX_VEX_3A7C (PREFIX_VEX_3A7B + 1)
-#define PREFIX_VEX_3A7D (PREFIX_VEX_3A7C + 1)
-#define PREFIX_VEX_3A7E (PREFIX_VEX_3A7D + 1)
-#define PREFIX_VEX_3A7F (PREFIX_VEX_3A7E + 1)
-#define PREFIX_VEX_3ADF (PREFIX_VEX_3A7F + 1)
+#define PREFIX_VEX_3ADF (PREFIX_VEX_3A63 + 1)
#define X86_64_06 0
#define X86_64_07 (X86_64_06 + 1)
#define VEX_LEN_3A61_P_2 (VEX_LEN_3A60_P_2 + 1)
#define VEX_LEN_3A62_P_2 (VEX_LEN_3A61_P_2 + 1)
#define VEX_LEN_3A63_P_2 (VEX_LEN_3A62_P_2 + 1)
-#define VEX_LEN_3A6A_P_2 (VEX_LEN_3A63_P_2 + 1)
-#define VEX_LEN_3A6B_P_2 (VEX_LEN_3A6A_P_2 + 1)
-#define VEX_LEN_3A6E_P_2 (VEX_LEN_3A6B_P_2 + 1)
-#define VEX_LEN_3A6F_P_2 (VEX_LEN_3A6E_P_2 + 1)
-#define VEX_LEN_3A7A_P_2 (VEX_LEN_3A6F_P_2 + 1)
-#define VEX_LEN_3A7B_P_2 (VEX_LEN_3A7A_P_2 + 1)
-#define VEX_LEN_3A7E_P_2 (VEX_LEN_3A7B_P_2 + 1)
-#define VEX_LEN_3A7F_P_2 (VEX_LEN_3A7E_P_2 + 1)
-#define VEX_LEN_3ADF_P_2 (VEX_LEN_3A7F_P_2 + 1)
+#define VEX_LEN_3ADF_P_2 (VEX_LEN_3A63_P_2 + 1)
typedef void (*op_rtn) (int bytemode, int sizeflag);
2 upper case letter macros:
"XY" => print 'x' or 'y' if no register operands or suffix_always
is true.
+ 'XW' => print 's', 'd' depending on the VEX.W bit (for FMA)
'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
or suffix_always is true
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_38DB */
+ /* PREFIX_VEX_3896 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
+ { "vfmaddsub132p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_38DC */
+ /* PREFIX_VEX_3897 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
+ { "vfmsubadd132p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_38DD */
+ /* PREFIX_VEX_3898 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
+ { "vfmadd132p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_38DE */
+ /* PREFIX_VEX_3899 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
+ { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_38DF */
+ /* PREFIX_VEX_389A */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
+ { "vfmsub132p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A04 */
+ /* PREFIX_VEX_389B */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vpermilps", { XM, EXx, Ib } },
+ { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A05 */
+ /* PREFIX_VEX_389C */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vpermilpd", { XM, EXx, Ib } },
+ { "vfnmadd132p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A06 */
+ /* PREFIX_VEX_389D */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
+ { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A08 */
+ /* PREFIX_VEX_389E */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vroundps", { XM, EXx, Ib } },
+ { "vfnmsub132p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A09 */
+ /* PREFIX_VEX_389F */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vroundpd", { XM, EXx, Ib } },
+ { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A0A */
+ /* PREFIX_VEX_38A6 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
+ { "vfmaddsub213p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A0B */
+ /* PREFIX_VEX_38A7 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
+ { "vfmsubadd213p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A0C */
+ /* PREFIX_VEX_38A8 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vblendps", { XM, Vex, EXx, Ib } },
+ { "vfmadd213p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A0D */
+ /* PREFIX_VEX_38A9 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vblendpd", { XM, Vex, EXx, Ib } },
+ { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A0E */
+ /* PREFIX_VEX_38AA */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
+ { "vfmsub213p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A0F */
+ /* PREFIX_VEX_38AB */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
+ { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A14 */
+ /* PREFIX_VEX_38AC */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
+ { "vfnmadd213p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A15 */
+ /* PREFIX_VEX_38AD */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
+ { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A16 */
+ /* PREFIX_VEX_38AE */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
+ { "vfnmsub213p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A17 */
+ /* PREFIX_VEX_38AF */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
+ { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A18 */
+ /* PREFIX_VEX_38B6 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
+ { "vfmaddsub231p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A19 */
+ /* PREFIX_VEX_38B7 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
+ { "vfmsubadd231p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A20 */
+ /* PREFIX_VEX_38B8 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
+ { "vfmadd231p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A21 */
+ /* PREFIX_VEX_38B9 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
+ { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A22 */
+ /* PREFIX_VEX_38BA */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
+ { "vfmsub231p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A40 */
+ /* PREFIX_VEX_38BB */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vdpps", { XM, Vex, EXx, Ib } },
+ { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A41 */
+ /* PREFIX_VEX_38BC */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
+ { "vfnmadd231p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A42 */
+ /* PREFIX_VEX_38BD */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
+ { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A48 */
+ /* PREFIX_VEX_38BE */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
+ { "vfnmsub231p%XW", { XM, Vex, EXx } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A49 */
+ /* PREFIX_VEX_38BF */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
+ { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A4A */
+ /* PREFIX_VEX_38DB */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
+ { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A4B */
+ /* PREFIX_VEX_38DC */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
+ { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A4C */
+ /* PREFIX_VEX_38DD */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A5C */
+ /* PREFIX_VEX_38DE */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
+ { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A5D */
+ /* PREFIX_VEX_38DF */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
+ { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A5E */
+ /* PREFIX_VEX_3A04 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
+ { "vpermilps", { XM, EXx, Ib } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A5F */
+ /* PREFIX_VEX_3A05 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
+ { "vpermilpd", { XM, EXx, Ib } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A60 */
+ /* PREFIX_VEX_3A06 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A61 */
+ /* PREFIX_VEX_3A08 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
+ { "vroundps", { XM, EXx, Ib } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A62 */
+ /* PREFIX_VEX_3A09 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
+ { "vroundpd", { XM, EXx, Ib } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A63 */
+ /* PREFIX_VEX_3A0A */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
+ { "(bad)", { XX } },
+ },
+
+ /* PREFIX_VEX_3A0B */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
+ { "(bad)", { XX } },
+ },
+
+ /* PREFIX_VEX_3A0C */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "vblendps", { XM, Vex, EXx, Ib } },
+ { "(bad)", { XX } },
+ },
+
+ /* PREFIX_VEX_3A0D */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "vblendpd", { XM, Vex, EXx, Ib } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A68 */
+ /* PREFIX_VEX_3A0E */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
+ { "(bad)", { XX } },
+ },
+
+ /* PREFIX_VEX_3A0F */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
+ { "(bad)", { XX } },
+ },
+
+ /* PREFIX_VEX_3A14 */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
+ { "(bad)", { XX } },
+ },
+
+ /* PREFIX_VEX_3A15 */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
+ { "(bad)", { XX } },
+ },
+
+ /* PREFIX_VEX_3A16 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
+ { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A69 */
+ /* PREFIX_VEX_3A17 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
+ { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A6A */
+ /* PREFIX_VEX_3A18 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A6B */
+ /* PREFIX_VEX_3A19 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A6C */
+ /* PREFIX_VEX_3A20 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
+ { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A6D */
+ /* PREFIX_VEX_3A21 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
+ { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A6E */
+ /* PREFIX_VEX_3A22 */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
+ { "(bad)", { XX } },
+ },
+
+ /* PREFIX_VEX_3A40 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
+ { "vdpps", { XM, Vex, EXx, Ib } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A6F */
+ /* PREFIX_VEX_3A41 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A78 */
+ /* PREFIX_VEX_3A42 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
+ { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A79 */
+ /* PREFIX_VEX_3A4A */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
+ { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A7A */
+ /* PREFIX_VEX_3A4B */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
+ { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A7B */
+ /* PREFIX_VEX_3A4C */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A7C */
+ /* PREFIX_VEX_3A60 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
+ { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A7D */
+ /* PREFIX_VEX_3A61 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
+ { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A7E */
+ /* PREFIX_VEX_3A62 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
{ "(bad)", { XX } },
},
- /* PREFIX_VEX_3A7F */
+ /* PREFIX_VEX_3A63 */
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
{ "(bad)", { XX } },
},
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
+ { PREFIX_TABLE (PREFIX_VEX_3896) },
+ { PREFIX_TABLE (PREFIX_VEX_3897) },
/* 98 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
+ { PREFIX_TABLE (PREFIX_VEX_3898) },
+ { PREFIX_TABLE (PREFIX_VEX_3899) },
+ { PREFIX_TABLE (PREFIX_VEX_389A) },
+ { PREFIX_TABLE (PREFIX_VEX_389B) },
+ { PREFIX_TABLE (PREFIX_VEX_389C) },
+ { PREFIX_TABLE (PREFIX_VEX_389D) },
+ { PREFIX_TABLE (PREFIX_VEX_389E) },
+ { PREFIX_TABLE (PREFIX_VEX_389F) },
/* a0 */
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
+ { PREFIX_TABLE (PREFIX_VEX_38A6) },
+ { PREFIX_TABLE (PREFIX_VEX_38A7) },
/* a8 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
+ { PREFIX_TABLE (PREFIX_VEX_38A8) },
+ { PREFIX_TABLE (PREFIX_VEX_38A9) },
+ { PREFIX_TABLE (PREFIX_VEX_38AA) },
+ { PREFIX_TABLE (PREFIX_VEX_38AB) },
+ { PREFIX_TABLE (PREFIX_VEX_38AC) },
+ { PREFIX_TABLE (PREFIX_VEX_38AD) },
+ { PREFIX_TABLE (PREFIX_VEX_38AE) },
+ { PREFIX_TABLE (PREFIX_VEX_38AF) },
/* b0 */
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
+ { PREFIX_TABLE (PREFIX_VEX_38B6) },
+ { PREFIX_TABLE (PREFIX_VEX_38B7) },
/* b8 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
+ { PREFIX_TABLE (PREFIX_VEX_38B8) },
+ { PREFIX_TABLE (PREFIX_VEX_38B9) },
+ { PREFIX_TABLE (PREFIX_VEX_38BA) },
+ { PREFIX_TABLE (PREFIX_VEX_38BB) },
+ { PREFIX_TABLE (PREFIX_VEX_38BC) },
+ { PREFIX_TABLE (PREFIX_VEX_38BD) },
+ { PREFIX_TABLE (PREFIX_VEX_38BE) },
+ { PREFIX_TABLE (PREFIX_VEX_38BF) },
/* c0 */
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
/* 48 */
- { PREFIX_TABLE (PREFIX_VEX_3A48) },
- { PREFIX_TABLE (PREFIX_VEX_3A49) },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
{ PREFIX_TABLE (PREFIX_VEX_3A4A) },
{ PREFIX_TABLE (PREFIX_VEX_3A4B) },
{ PREFIX_TABLE (PREFIX_VEX_3A4C) },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { PREFIX_TABLE (PREFIX_VEX_3A5C) },
- { PREFIX_TABLE (PREFIX_VEX_3A5D) },
- { PREFIX_TABLE (PREFIX_VEX_3A5E) },
- { PREFIX_TABLE (PREFIX_VEX_3A5F) },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
/* 60 */
{ PREFIX_TABLE (PREFIX_VEX_3A60) },
{ PREFIX_TABLE (PREFIX_VEX_3A61) },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
/* 68 */
- { PREFIX_TABLE (PREFIX_VEX_3A68) },
- { PREFIX_TABLE (PREFIX_VEX_3A69) },
- { PREFIX_TABLE (PREFIX_VEX_3A6A) },
- { PREFIX_TABLE (PREFIX_VEX_3A6B) },
- { PREFIX_TABLE (PREFIX_VEX_3A6C) },
- { PREFIX_TABLE (PREFIX_VEX_3A6D) },
- { PREFIX_TABLE (PREFIX_VEX_3A6E) },
- { PREFIX_TABLE (PREFIX_VEX_3A6F) },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
/* 70 */
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
/* 78 */
- { PREFIX_TABLE (PREFIX_VEX_3A78) },
- { PREFIX_TABLE (PREFIX_VEX_3A79) },
- { PREFIX_TABLE (PREFIX_VEX_3A7A) },
- { PREFIX_TABLE (PREFIX_VEX_3A7B) },
- { PREFIX_TABLE (PREFIX_VEX_3A7C) },
- { PREFIX_TABLE (PREFIX_VEX_3A7D) },
- { PREFIX_TABLE (PREFIX_VEX_3A7E) },
- { PREFIX_TABLE (PREFIX_VEX_3A7F) },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
/* 80 */
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
},
- /* VEX_LEN_3A6A_P_2 */
- {
- { "vfmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
- { "(bad)", { XX } },
- },
-
- /* VEX_LEN_3A6B_P_2 */
- {
- { "vfmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
- { "(bad)", { XX } },
- },
-
- /* VEX_LEN_3A6E_P_2 */
- {
- { "vfmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
- { "(bad)", { XX } },
- },
-
- /* VEX_LEN_3A6F_P_2 */
- {
- { "vfmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
- { "(bad)", { XX } },
- },
-
- /* VEX_LEN_3A7A_P_2 */
- {
- { "vfnmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
- { "(bad)", { XX } },
- },
-
- /* VEX_LEN_3A7B_P_2 */
- {
- { "vfnmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
- { "(bad)", { XX } },
- },
-
- /* VEX_LEN_3A7E_P_2 */
- {
- { "vfnmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
- { "(bad)", { XX } },
- },
-
- /* VEX_LEN_3A7F_P_2 */
- {
- { "vfnmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
- { "(bad)", { XX } },
- },
-
/* VEX_LEN_3ADF_P_2 */
{
{ "vaeskeygenassist", { XM, EXx, Ib } },
}
break;
case 'W':
- /* operand size flag for cwtl, cbtw */
- USED_REX (REX_W);
- if (rex & REX_W)
+ if (l == 0 && len == 1)
{
- if (intel_syntax)
- *obufp++ = 'd';
+ /* operand size flag for cwtl, cbtw */
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ {
+ if (intel_syntax)
+ *obufp++ = 'd';
+ else
+ *obufp++ = 'l';
+ }
+ else if (sizeflag & DFLAG)
+ *obufp++ = 'w';
else
- *obufp++ = 'l';
+ *obufp++ = 'b';
+ if (!(rex & REX_W))
+ used_prefixes |= (prefixes & PREFIX_DATA);
}
- else if (sizeflag & DFLAG)
- *obufp++ = 'w';
else
- *obufp++ = 'b';
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
+ {
+ if (l != 1 || len != 2 || last[0] != 'X')
+ {
+ SAVE_LAST (*p);
+ break;
+ }
+ if (!need_vex)
+ abort ();
+ *obufp++ = vex.w ? 'd': 's';
+ }
break;
}
alt = 0;
case o_mode:
oappend ("OWORD PTR ");
break;
+ case vex_w_dq_mode:
+ if (!need_vex)
+ abort ();
+
+ if (vex.w)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ break;
default:
break;
}
oappend (scratchbuf + intel_syntax);
}
-/* Get the VEX immediate byte without moving codep. */
-
-static unsigned char
-get_vex_imm8 (int sizeflag)
-{
- int bytes_before_imm = 0;
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- if (modrm.mod != 3)
- {
- /* There are SIB/displacement bytes. */
- if ((sizeflag & AFLAG) || address_mode == mode_64bit)
- {
- /* 32/64 bit address mode */
- int base = modrm.rm;
-
- /* Check SIB byte. */
- if (base == 4)
- {
- FETCH_DATA (the_info, codep + 1);
- base = *codep & 7;
- bytes_before_imm++;
- }
-
- switch (modrm.mod)
- {
- case 0:
- /* When modrm.rm == 5 or modrm.rm == 4 and base in
- SIB == 5, there is a 4 byte displacement. */
- if (base != 5)
- /* No displacement. */
- break;
- case 2:
- /* 4 byte displacement. */
- bytes_before_imm += 4;
- break;
- case 1:
- /* 1 byte displacement. */
- bytes_before_imm++;
- break;
- }
- }
- else
- { /* 16 bit address mode */
- switch (modrm.mod)
- {
- case 0:
- /* When modrm.rm == 6, there is a 2 byte displacement. */
- if (modrm.rm != 6)
- /* No displacement. */
- break;
- case 2:
- /* 2 byte displacement. */
- bytes_before_imm += 2;
- break;
- case 1:
- /* 1 byte displacement. */
- bytes_before_imm++;
- break;
- }
- }
- }
-
- FETCH_DATA (the_info, codep + bytes_before_imm + 1);
- return codep [bytes_before_imm];
-}
-
-static void
-OP_EX_VexReg (int bytemode, int sizeflag, int reg)
-{
- if (reg == -1 && modrm.mod != 3)
- {
- OP_E_memory (bytemode, sizeflag, 0);
- return;
- }
- else
- {
- if (reg == -1)
- {
- reg = modrm.rm;
- USED_REX (REX_B);
- if (rex & REX_B)
- reg += 8;
- }
- else if (reg > 7 && address_mode != mode_64bit)
- BadOp ();
- }
-
- switch (vex.length)
- {
- case 128:
- sprintf (scratchbuf, "%%xmm%d", reg);
- break;
- case 256:
- sprintf (scratchbuf, "%%ymm%d", reg);
- break;
- default:
- abort ();
- }
- oappend (scratchbuf + intel_syntax);
-}
-
-static void
-OP_EX_VexImmW (int bytemode, int sizeflag)
-{
- int reg = -1;
- static unsigned char vex_imm8;
-
- if (!vex_w_done)
- {
- vex_imm8 = get_vex_imm8 (sizeflag);
- if (vex.w)
- reg = vex_imm8 >> 4;
- vex_w_done = 1;
- }
- else
- {
- if (!vex.w)
- reg = vex_imm8 >> 4;
- }
-
- OP_EX_VexReg (bytemode, sizeflag, reg);
-}
-
-static void
-OP_EX_VexW (int bytemode, int sizeflag)
-{
- int reg = -1;
-
- if (!vex_w_done)
- {
- vex_w_done = 1;
- if (vex.w)
- reg = vex.register_specifier;
- }
- else
- {
- if (!vex.w)
- reg = vex.register_specifier;
- }
-
- OP_EX_VexReg (bytemode, sizeflag, reg);
-}
-
-static void
-OP_VEX_FMA (int bytemode, int sizeflag)
-{
- int reg = get_vex_imm8 (sizeflag) >> 4;
-
- if (reg > 7 && address_mode != mode_64bit)
- BadOp ();
-
- switch (vex.length)
- {
- case 128:
- switch (bytemode)
- {
- case vex_mode:
- case vex128_mode:
- break;
- default:
- abort ();
- return;
- }
-
- sprintf (scratchbuf, "%%xmm%d", reg);
- break;
- case 256:
- switch (bytemode)
- {
- case vex_mode:
- break;
- default:
- abort ();
- return;
- }
-
- sprintf (scratchbuf, "%%ymm%d", reg);
- break;
- default:
- abort ();
- }
- oappend (scratchbuf + intel_syntax);
-}
-
-static void
-VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
-{
- /* Skip the immediate byte and check for invalid bits. */
- FETCH_DATA (the_info, codep + 1);
- if (*codep++ & 0xf)
- BadOp ();
-}
-
static void
OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
oappend (scratchbuf + intel_syntax);
}
-static void
-OP_XMM_VexW (int bytemode, int sizeflag)
-{
- /* Turn off the REX.W bit since it is used for swapping operands
- now. */
- rex &= ~REX_W;
- OP_XMM (bytemode, sizeflag);
-}
-
static void
OP_EX_Vex (int bytemode, int sizeflag)
{
}
}
-static const struct op vpermil2_op[] =
-{
- { STRING_COMMA_LEN ("td") },
- { STRING_COMMA_LEN ("td") },
- { STRING_COMMA_LEN ("mo") },
- { STRING_COMMA_LEN ("mz") }
-};
-
-static void
-VPERMIL2_Fixup (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
-{
- unsigned int vpermil2_type;
-
- FETCH_DATA (the_info, codep + 1);
- vpermil2_type = *codep++ & 0xf;
- if (vpermil2_type < ARRAY_SIZE (vpermil2_op))
- {
- char suffix [4];
- char *p = mnemonicendp - 3;
- suffix[0] = p[0];
- suffix[1] = p[1];
- suffix[2] = p[2];
- suffix[3] = '\0';
- sprintf (p, "%s%s", vpermil2_op[vpermil2_type].name, suffix);
- mnemonicendp += vpermil2_op[vpermil2_type].len;
- }
- else
- {
- /* We have a reserved extension byte. Output it directly. */
- scratchbuf[0] = '$';
- print_operand_value (scratchbuf + 1, 1, vpermil2_type);
- oappend (scratchbuf + intel_syntax);
- scratchbuf[0] = '\0';
- }
-}
-
static void
MOVBE_Fixup (int bytemode, int sizeflag)
{
/* Declarations for Intel 80386 opcode table
- Copyright 2007, 2008
+ Copyright 2007, 2008, 2009
Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
#define Vex (Drexc + 1)
/* insn has 256bit VEX prefix. */
#define Vex256 (Vex + 1)
-/* insn has VEX NDS. Register-only source is encoded in Vex
- prefix. */
+/* insn has VEX NDS. Register-only source is encoded in Vex prefix.
+ We use VexNDS on insns with VEX DDS since the register-only source
+ is the second source register. */
#define VexNDS (Vex256 + 1)
/* insn has VEX NDD. Register destination is encoded in Vex
prefix. */
// i386 opcode table.
-// Copyright 2007, 2008
+// Copyright 2007, 2008, 2009
// Free Software Foundation, Inc.
//
// This file is part of the GNU opcodes library.
vpcmpistri, 3, 0x6663, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
vpcmpistrm, 3, 0x6662, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
vperm2f128, 4, 0x6606, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vpermil2pd, 5, 0x6649, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vpermil2ps, 5, 0x6648, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Vex_Imm4, RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
vpermilpd, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|Vex0F38|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
-vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vpermilmo2pd, 4, 0x6649, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vpermilmz2pd, 4, 0x6649, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vpermiltd2pd, 4, 0x6649, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vpermilmo2ps, 4, 0x6648, 0x2, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vpermilmz2ps, 4, 0x6648, 0x3, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vpermiltd2ps, 4, 0x6648, 0x0, 1, CpuAVX, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|VexImmExt, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ByteOkIntel|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
vpextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
vpextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F3A|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S }
// FMA instructions
-vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmaddpd, 4, 0x6669, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmaddps, 4, 0x6668, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vfmaddsd, 4, 0x666b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmaddsd, 4, 0x666b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddss, 4, 0x666a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmaddss, 4, 0x666a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmaddsubpd, 4, 0x665d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmaddsubps, 4, 0x665c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmsubaddpd, 4, 0x665f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmsubaddps, 4, 0x665e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmsubpd, 4, 0x666d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfmsubps, 4, 0x666c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vfmsubsd, 4, 0x666f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmsubsd, 4, 0x666f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfmsubss, 4, 0x666e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfmsubss, 4, 0x666e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfnmaddpd, 4, 0x6679, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfnmaddps, 4, 0x6678, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vfnmaddsd, 4, 0x667b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfnmaddsd, 4, 0x667b, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmaddss, 4, 0x667a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfnmaddss, 4, 0x667a, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfnmsubpd, 4, 0x667d, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM, RegYMM }
-vfnmsubps, 4, 0x667c, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|Vex256|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
-vfnmsubsd, 4, 0x667f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfnmsubsd, 4, 0x667f, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-vfnmsubss, 4, 0x667e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
-vfnmsubss, 4, 0x667e, None, 1, CpuFMA, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmadd132pd, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmadd132pd, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmadd132ps, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmadd132ps, 3, 0x6698, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmadd213pd, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmadd213pd, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmadd213ps, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmadd213ps, 3, 0x66a8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmadd231pd, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmadd231pd, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmadd231ps, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmadd231ps, 3, 0x66b8, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmadd132sd, 3, 0x6699, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmadd132ss, 3, 0x6699, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmadd213sd, 3, 0x66a9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmadd213ss, 3, 0x66a9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmadd231sd, 3, 0x66b9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmadd231ss, 3, 0x66b9, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmaddsub132pd, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmaddsub132pd, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddsub132ps, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmaddsub132ps, 3, 0x6696, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddsub213pd, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmaddsub213pd, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddsub213ps, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmaddsub213ps, 3, 0x66a6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddsub231pd, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmaddsub231pd, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmaddsub231ps, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmaddsub231ps, 3, 0x66b6, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubadd132pd, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsubadd132pd, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubadd132ps, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsubadd132ps, 3, 0x6697, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubadd213pd, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsubadd213pd, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubadd213ps, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsubadd213ps, 3, 0x66a7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubadd231pd, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsubadd231pd, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsubadd231ps, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsubadd231ps, 3, 0x66b7, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsub132pd, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsub132pd, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsub132ps, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsub132ps, 3, 0x669a, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsub213pd, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsub213pd, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsub213ps, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsub213ps, 3, 0x66aa, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsub231pd, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsub231pd, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsub231ps, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsub231ps, 3, 0x66ba, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfmsub132sd, 3, 0x669b, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsub132ss, 3, 0x669b, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsub213sd, 3, 0x66ab, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsub213ss, 3, 0x66ab, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsub231sd, 3, 0x66bb, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfmsub231ss, 3, 0x66bb, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmadd132pd, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmadd132pd, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmadd132ps, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmadd132ps, 3, 0x669c, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmadd213pd, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmadd213pd, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmadd213ps, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmadd213ps, 3, 0x66ac, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmadd231pd, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmadd231pd, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmadd231ps, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmadd231ps, 3, 0x66bc, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmadd132sd, 3, 0x669d, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmadd132ss, 3, 0x669d, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmadd213sd, 3, 0x66ad, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmadd213ss, 3, 0x66ad, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmadd231sd, 3, 0x66bd, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmadd231ss, 3, 0x66bd, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmsub132pd, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmsub132pd, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmsub132ps, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmsub132ps, 3, 0x669e, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmsub213pd, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmsub213pd, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmsub213ps, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmsub213ps, 3, 0x66ae, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmsub231pd, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmsub231pd, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm|Vex|Vex0F38|Vex256|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+vfnmsub132sd, 3, 0x669f, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmsub132ss, 3, 0x669f, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmsub213sd, 3, 0x66af, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmsub213ss, 3, 0x66af, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmsub231sd, 3, 0x66bf, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+vfnmsub231ss, 3, 0x66bf, None, 1, CpuFMA, Modrm|Vex|Vex0F38|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
// AMD 3DNow! instructions.
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } } } },
- { "vpermil2pd", 5, 0x6649, None, 1,
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0 } } } },
+ { "vfnmsub231ss", 3, 0x66bf, None, 1,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } },
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
+ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
0, 0, 1, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
projects / binutils-gdb.git / commitdiff