liteeth/phy/gmii_mii: avoid doubling pads register on TX

diff --git a/misoclib/com/liteeth/phy/gmii.py b/misoclib/com/liteeth/phy/gmii.py
index 3d020b92802e7bd21a31e9f424067e1fd6dc8d3b..429eea62557bf5212b61ef67d9d4a3dee68d5108 100644 (file)
--- a/misoclib/com/liteeth/phy/gmii.py
+++ b/misoclib/com/liteeth/phy/gmii.py
@@ -4,15 +4,19 @@ from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 
 class LiteEthPHYGMIITX(Module):
-       def __init__(self, pads):
+       def __init__(self, pads, pads_register):
                self.sink = sink = Sink(eth_phy_description(8))
                ###
                if hasattr(pads, "tx_er"):
                        self.sync += pads.tx_er.eq(0)
-               self.sync += [
+               pads_eq = [
                        pads.tx_en.eq(sink.stb),
                        pads.tx_data.eq(sink.data)
                ]
+               if pads_register:
+                       self.sync += pads_eq
+               else:
+                       self.comb += pads_eq
                self.comb += sink.ack.eq(1)
 
 class LiteEthPHYGMIIRX(Module):

diff --git a/misoclib/com/liteeth/phy/gmii_mii.py b/misoclib/com/liteeth/phy/gmii_mii.py
index 91a122d5f794a582e7d9d9dc52e3b181d55b66c7..b270d462ae77c1953d8654676083a560f98ffd6b 100644 (file)
--- a/misoclib/com/liteeth/phy/gmii_mii.py
+++ b/misoclib/com/liteeth/phy/gmii_mii.py
@@ -21,11 +21,11 @@ class LiteEthPHYGMIIMIITX(Module):
                tx_pads_layout = [("tx_er", 1), ("tx_en", 1), ("tx_data", 8)]
 
                gmii_tx_pads = Record(tx_pads_layout)
-               gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads)
+               gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads, pads_register=False)
                self.submodules += gmii_tx
 
                mii_tx_pads = Record(tx_pads_layout)
-               mii_tx = LiteEthPHYMIITX(mii_tx_pads)
+               mii_tx = LiteEthPHYMIITX(mii_tx_pads, pads_register=False)
                self.submodules += mii_tx
 
                demux = Demultiplexer(eth_phy_description(8), 2)

diff --git a/misoclib/com/liteeth/phy/mii.py b/misoclib/com/liteeth/phy/mii.py
index 0a0b9b40f14eb9dbd5ee78bb77b757d350c9e263..3f7b48e373e995eff6565c03676e0b7506082cc8 100644 (file)
--- a/misoclib/com/liteeth/phy/mii.py
+++ b/misoclib/com/liteeth/phy/mii.py
@@ -6,7 +6,7 @@ def converter_description(dw):
        return EndpointDescription(payload_layout, packetized=True)
 
 class LiteEthPHYMIITX(Module):
-       def __init__(self, pads):
+       def __init__(self, pads, pads_register=True):
                self.sink = sink = Sink(eth_phy_description(8))
                ###
                if hasattr(pads, "tx_er"):
@@ -19,10 +19,14 @@ class LiteEthPHYMIITX(Module):
                        sink.ack.eq(converter.sink.ack),
                        converter.source.ack.eq(1)
                ]
-               self.sync += [
+               pads_eq = [
                        pads.tx_en.eq(converter.source.stb),
                        pads.tx_data.eq(converter.source.data)
                ]
+               if pads_register:
+                       self.sync += pads_eq
+               else:
+                       self.comb += pads_eq
 
 class LiteEthPHYMIIRX(Module):
        def __init__(self, pads):