cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 6c8525f611b0dd340085c23ef7fdd6b411435c5f..037d367d05f5d39937474b5e3f4b8399bbf07373 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -214,9 +214,9 @@ class S7PLL(XilinxClocking):
         XilinxClocking.__init__(self)
         self.divclk_divide_range = (1, 56+1)
         self.vco_freq_range = {
-            -1: (800e6, 2133e6),
+            -1: (800e6, 1600e6),
             -2: (800e6, 1866e6),
-            -3: (800e6, 1600e6),
+            -3: (800e6, 2133e6),
         }[speedgrade]
 
     def do_finalize(self):