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diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index fd8327225c9f68f0fb700caa734c55e4a147af3e..dbc08e9b2feda7f35c9e6365de7bedf0bae91e04 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -148,6 +148,16 @@ from different sources is as follows:
 The reasoning here is that the opportunity to set RT equal to the
 immediate `SVi+1` is sacrificed in favour of setting from CTR.
 
+# Rc=1
+
+CR Field 0, when `Rc=1`, may be set even if `RT=0`. The reason is that
+overflow may occur: `VL`, if set either from an immediate or from `CTR`,
+may not exceed `MAXVL`, and if it is, `CR0.SO` must be set.
+
+Additionally, in reality it is **`VL`** being set. Therefore, rather
+than `CR0` testing `RT` when `Rc=1`, CR0.EQ is set if `VL=0`, CR0.GE
+is set if `VL` is non-zero.
+
 # Vertical First Mode
 
 Vertical First is effectively like an implicit single bit predicate