/* Should but doesnt work */
//#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
-//#define TMU_ENABLED(ctx, unit) (hw_tcl_on ? ctx->Texture.Unit[unit]._ReallyEnabled && (OutputsWritten & (1<<(VERT_RESULT_TEX0+(unit)))) :
-// (r300->state.render_inputs & (_TNL_BIT_TEX0<<(unit))))
-//#define TMU_ENABLED(ctx, unit) (hw_tcl_on ? ctx->Texture.Unit[unit]._ReallyEnabled && OutputsWritten & (1<<(VERT_RESULT_TEX0+(unit))) :
-// ctx->Texture.Unit[unit]._ReallyEnabled && r300->state.render_inputs & (_TNL_BIT_TEX0<<(unit)))
-
-#define TMU_ENABLED(ctx, unit) (ctx->Texture.Unit[unit]._ReallyEnabled)
/* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
* Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
* Most likely this is used to ignore rest of the program in cases
* where group of verts arent visible. For some reason this "section"
* is sometimes accepted other instruction that have no relationship with
- *position calculations.
+ *position calculations.
*/
#define R300_VAP_PVS_CNTL_1 0x22D0
# define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0
#define R300_RE_FOG_SCALE 0x4294
#define R300_RE_FOG_START 0x4298
-/* Not sure why there are duplicate of factor and constant values.
- * My best guess so far is that there are seperate zbiases for test and write.
+/* Not sure why there are duplicate of factor and constant values.
+ * My best guess so far is that there are seperate zbiases for test and write.
* Ordering might be wrong.
* Some of the tests indicate that fgl has a fallback implementation of zbias
* via pixel shaders.
/* 32 bit chroma key */
#define R300_TX_CHROMA_KEY_0 0x4580
/* ff00ff00 == { 0, 1.0, 0, 1.0 } */
-#define R300_TX_BORDER_COLOR_0 0x45C0
+#define R300_TX_BORDER_COLOR_0 0x45C0
/* END: Texture specification */
# define R300_FPITX_OP_KIL 2
# define R300_FPITX_OP_TXP 3
# define R300_FPITX_OP_TXB 4
+# define R300_FPITX_OPCODE_MASK (7 << 15)
/* ALU
* The ALU instructions register blocks are enumerated according to the order
/* We cannot let disabled tmu offsets pass DRM */
for(i=0; i < mtu; i++) {
- if(TMU_ENABLED(ctx, i)) {
+ if (ctx->Texture.Unit[i]._ReallyEnabled) {
#if 0 /* Enables old behaviour */
hw_tmu = i;
for(i = 0; i < rp->tex.length; i++){
int unit;
+ int opcode;
unsigned long val;
unit = rp->tex.inst[i] >> R300_FPITX_IMAGE_SHIFT;
val = rp->tex.inst[i];
val &= ~R300_FPITX_IMAGE_MASK;
- if (((val >> R300_FPITX_OPCODE_SHIFT) & 7) == R300_FPITX_OP_KIL) {
+ opcode = (val & R300_FPITX_OPCODE_MASK) >> R300_FPITX_OPCODE_SHIFT;
+ if (opcode == R300_FPITX_OP_KIL) {
r300->hw.fpt.cmd[R300_FPT_INSTR_0+i] = val;
} else {
- assert(tmu_mappings[unit] >= 0);
-
- val |= tmu_mappings[unit] << R300_FPITX_IMAGE_SHIFT;
- r300->hw.fpt.cmd[R300_FPT_INSTR_0+i] = val;
+ if (tmu_mappings[unit] >= 0) {
+ val |= tmu_mappings[unit] << R300_FPITX_IMAGE_SHIFT;
+ r300->hw.fpt.cmd[R300_FPT_INSTR_0+i] = val;
+ } else {
+ // We get here when the corresponding texture image is incomplete
+ // (e.g. incomplete mipmaps etc.)
+ r300->hw.fpt.cmd[R300_FPT_INSTR_0+i] = val;
+ }
}
}