ssa-fre-4.c: Remove mips*-*-* target.

2015-12-14  Steve Ellcey  <sellcey@imgtec.com>

	* gcc.dg/tree-ssa/ssa-fre-4.c: Remove mips*-*-* target.
	* gcc.target/mips/ext-2.c: Update scan checks.

From-SVN: r231635

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ff02575e4d4b0291a3001851d64054b17254955c..a4d593b217a468550bbaea58bc092e3122ec9da0 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2015-12-14  Steve Ellcey  <sellcey@imgtec.com>
+
+       * gcc.dg/tree-ssa/ssa-fre-4.c: Remove mips*-*-* target.
+       * gcc.target/mips/ext-2.c: Update scan checks.
+
 2015-12-14  Nathan Sidwell  <nathan@acm.org>
 
        * g++.dg/abi/nvptx-nrv1.C: New.

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-4.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-4.c
index 02b6719ea85152789f122bdc76b5800e4f17a1f3..5a7588febaa35c8a62055bd86d9dd211d8d4ca07 100644 (file)
--- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-4.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-4.c
@@ -1,6 +1,6 @@
 /* If the target returns false for TARGET_PROMOTE_PROTOTYPES, then there
    will be no casts for FRE to eliminate and the test will fail.  */
-/* { dg-do compile { target i?86-*-* x86_64-*-* hppa*-*-* mips*-*-* m68k*-*-* } } */
+/* { dg-do compile { target i?86-*-* x86_64-*-* hppa*-*-* m68k*-*-* } } */
 /* { dg-options "-O -fno-tree-ccp -fno-tree-forwprop -fdump-tree-fre1-details" } */
 
 /* From PR21608.  */

diff --git a/gcc/testsuite/gcc.target/mips/ext-2.c b/gcc/testsuite/gcc.target/mips/ext-2.c
index 320d42d2f6998e07339831bf836e68525af49493..97703217991903c324f0f0dc615cfd8e76ba4110 100644 (file)
--- a/gcc/testsuite/gcc.target/mips/ext-2.c
+++ b/gcc/testsuite/gcc.target/mips/ext-2.c
@@ -1,12 +1,13 @@
 /* Turn the truncate,zero_extend,lshiftrt sequence before the or into a
    zero_extract.  The truncate is due to TARGET_PROMOTE_PROTOTYPES, the
-   zero_extend to PROMOTE_MODE.  */
+   zero_extend to PROMOTE_MODE.  As of GCC 6, we no longer define
+   TARGET_PROMOTE_PROTOTYPES so that truncate is gone and we can
+   generate either a single extract or a single shift instruction.  */
 /* { dg-do compile } */
 /* { dg-options "isa_rev>=2 -mgp64 -mlong64" } */
 /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
-/* { dg-final { scan-assembler "\tdext\t" } } */
+/* { dg-final { scan-assembler-times "\tdext\t|\td?srl" 1 } } */
 /* { dg-final { scan-assembler-not "\tand" } } */
-/* { dg-final { scan-assembler-not "\td?srl" } } */
 
 NOMIPS16 void
 f (unsigned char x, unsigned char *r)