move sv remap function to sv.cc (not inline)

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index c52d5c0addf6aed2ab6ad57fe8258b800fbcc215..045d58ab88e620b7f2c8e695c6d9e03e5591e26f 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -52,6 +52,7 @@ riscv_srcs = \
        clint.cc \
        debug_module.cc \
        remote_bitbang.cc \
+       sv.cc \
        jtag_dtm.cc \
        $(riscv_gen_srcs) \
 

diff --git a/riscv/sv.cc b/riscv/sv.cc
index 296e2d39ef24323bde6a7469c9056f73e15508d6..ad6b0e070b2b67a64026383b10788f9be07c2f27 100644 (file)
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -1,4 +1,5 @@
 #include "sv.h"
+#include "sv_decode.h"
 
 sv_reg_csr_entry sv_csrs[SV_CSR_SZ];
 sv_reg_entry sv_int_tb[NXPR];
@@ -27,3 +28,9 @@ bool sv_check_reg(bool intreg, uint64_t reg)
   }
   return false;
 }
+
+uint64_t sv_insn_t::remap(uint64_t reg)
+{
+    return reg;
+}
+

diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 14dad03f2a09d5a72006234469b0a987eac8046b..a92661027d2a620a58c230ddaf191c3e1f436f6c 100644 (file)
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -18,7 +18,7 @@ private:
   int &voffs;
   // remaps the register through the lookup table.
   // will need to take the current loop index/offset somehow
-  uint64_t remap(uint64_t reg) { return reg; } // TODO
+  uint64_t remap(uint64_t reg);
 };
 
 #endif