Fix various NDEBUG compiler warnings, closes #1255

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index f49ecbedabda1d85be52b5184ab653ec824e5fd6..5e12e9a340951cdae05caa61ce9defc7ce780f0c 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -312,7 +312,7 @@ struct XAigerWriter
 #if 0
                        toposort.analyze_loops = true;
 #endif
-                       bool no_loops = toposort.sort();
+                       bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
 #if 0
                        unsigned i = 0;
                        for (auto &it : toposort.loops) {

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index bd0596cc04460155769595e006e6e5a56d2cd942..534cc0daa8d444ee47c8f418a0ae33de82e123a5 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -67,7 +67,7 @@ struct ConstEvalAig
                                continue;
                        for (auto &it2 : it.second->connections())
                                if (yosys_celltypes.cell_output(it.second->type, it2.first)) {
-                                       auto r = sig2driver.insert(std::make_pair(it2.second, it.second));
+                                       auto r YS_ATTRIBUTE(unused) = sig2driver.insert(std::make_pair(it2.second, it.second));
                                        log_assert(r.second);
                                }
                }
@@ -389,9 +389,9 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
                        f.ignore(1);
                        // XAIGER extensions
                        if (c == 'm') {
-                               uint32_t dataSize = parse_xaiger_literal(f);
+                               uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
                                uint32_t lutNum = parse_xaiger_literal(f);
-                               uint32_t lutSize = parse_xaiger_literal(f);
+                               uint32_t lutSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
                                log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
                                ConstEvalAig ce(module);
                                for (unsigned i = 0; i < lutNum; ++i) {
@@ -416,7 +416,7 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
                                                int gray = j ^ (j >> 1);
                                                ce.set_incremental(input_sig, RTLIL::Const{gray, static_cast<int>(cutLeavesM)});
                                                RTLIL::SigBit o(output_sig);
-                                               bool success = ce.eval(o);
+                                               bool success YS_ATTRIBUTE(unused) = ce.eval(o);
                                                log_assert(success);
                                                log_assert(o.wire == nullptr);
                                                lut_mask[gray] = o.data;
@@ -428,7 +428,7 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
                                }
                        }
                        else if (c == 'r') {
-                               uint32_t dataSize = parse_xaiger_literal(f);
+                               uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
                                flopNum = parse_xaiger_literal(f);
                                log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
                                f.ignore(flopNum * sizeof(uint32_t));
@@ -440,15 +440,15 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
                        }
                        else if (c == 'h') {
                                f.ignore(sizeof(uint32_t));
-                               uint32_t version = parse_xaiger_literal(f);
+                               uint32_t version YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
                                log_assert(version == 1);
-                               uint32_t ciNum = parse_xaiger_literal(f);
+                               uint32_t ciNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
                                log_debug("ciNum = %u\n", ciNum);
-                               uint32_t coNum = parse_xaiger_literal(f);
+                               uint32_t coNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
                                log_debug("coNum = %u\n", coNum);
                                piNum = parse_xaiger_literal(f);
                                log_debug("piNum = %u\n", piNum);
-                               uint32_t poNum = parse_xaiger_literal(f);
+                               uint32_t poNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
                                log_debug("poNum = %u\n", poNum);
                                uint32_t boxNum = parse_xaiger_literal(f);
                                log_debug("boxNum = %u\n", poNum);
@@ -901,8 +901,10 @@ void AigerReader::post_process()
                                RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));
                                if (cell) { // ABC could have optimised this box away
                                        module->rename(cell, escaped_s);
+                               #ifndef NDEBUG
                                        RTLIL::Module* box_module = design->module(cell->type);
                                        log_assert(box_module);
+                               #endif
 
                                        for (const auto &i : cell->connections()) {
                                                RTLIL::IdString port_name = i.first;

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 17c4a1e5bc9989a693067d031c38e80ee6dd84fa..64152c9cb2ceb807fa8c7d4f8ac6befc33f43733 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1789,8 +1789,10 @@ struct VerificExtNets
                                new_net = new Net(name.c_str());
                                nl->Add(new_net);
 
+                       #ifndef NDEBUG
                                Net *n = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
                                log_assert(n == ca_net);
+                       #endif
                        }
 
                        if (verific_verbose)

diff --git a/kernel/log.h b/kernel/log.h
index 3e1facae87c0353dcfb754c130a0b914ce348374..5f53f533a6845484d2ce3a63130e6ce53e640a7a 100644 (file)
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -91,7 +91,7 @@ YS_NORETURN void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(prin
 static inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; }
 #  define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)
 #else
-static inline bool ys_debug(int n = 0) { return false; }
+static inline bool ys_debug(int = 0) { return false; }
 #  define log_debug(_fmt, ...) do { } while (0)
 #endif
 

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index b2dc9a44817bcd2f78d5dbba426b688545fb82a1..1512cea1bab23e174babea935012e335ecb57fcb 100644 (file)
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -117,7 +117,8 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
        }
 }
 
-void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
+void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell,
+               const std::string &info YS_ATTRIBUTE(unused), IdString out_port, RTLIL::SigSpec out_val)
 {
        RTLIL::SigSpec Y = cell->getPort(out_port);
        out_val.extend_u0(Y.size(), false);

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 7418ed4a3e6f0f97bc4c8e04ea49e3cec2f6463a..da376d09eba9d4f6df3a30a62189b4326fbe1704 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -741,7 +741,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                                for (auto driver_cell : bit_drivers.at(it.first))
                                for (auto user_cell : it.second)
                                        toposort.edge(driver_cell, user_cell);
-               bool no_loops = toposort.sort();
+               bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
                log_assert(no_loops);
 
                for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {