add link to alternative memory interface idea

diff --git a/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/architecture/memory_and_cache.mdwn
index 85f84dac34380998c4df3bceb59e86eb7becc459..ac02a3248c7b5c570a7dbba426c8b73203846c72 100644 (file)
--- a/3d_gpu/architecture/memory_and_cache.mdwn
+++ b/3d_gpu/architecture/memory_and_cache.mdwn
@@ -38,6 +38,10 @@ Basic diagram:
 * Memory is the silicon-proven OpenCores [SDRAM|sdram] interface,
   and it is Wishbone compliant.
 
+## Alternative Design Idea
+
+[[alternative-design-idea]]
+
 # 28-45nm Quad-Core SoC
 
 This is full SMP, requires analog PLLs, clock gating, full SMP