soc/interconnect/stream: add support for buffered async fifo

diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index 1bf81ef134ab77a0fd1beff45211412cf7a0b291..0c185a197a3d368b64fe54475eacb8cb77feb063 100644 (file)
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -106,8 +106,11 @@ class SyncFIFO(_FIFOWrapper):
 
 
 class AsyncFIFO(_FIFOWrapper):
-    def __init__(self, layout, depth):
-        _FIFOWrapper.__init__(self, fifo.AsyncFIFO, layout, depth)
+    def __init__(self, layout, depth, buffered=False):
+        _FIFOWrapper.__init__(
+            self,
+            fifo.AsyncFIFOBuffered if buffered else fifo.AsyncFIFO,
+            layout, depth)
 
 
 class Multiplexer(Module):