More fixes for bugs found using xsthammer

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index cb59246c6a857342a6a429f125a3ce1108a5feec..aa5a98c4133069c3d6f6264287f0a0e904c4306b 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -752,7 +752,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint)
                        RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint);
                        is_signed = type == AST_NEG || (type == AST_POS && children[0]->is_signed);
                        int width = type == AST_NEG && arg.width < width_hint ? arg.width+1 : arg.width;
-                       if (width > width_hint && width_hint > 0)
+                       if (width_hint > 0)
                                width = width_hint;
                        return uniop2rtlil(this, type_name, width, arg);
                }
@@ -766,9 +766,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint)
                        RTLIL::SigSpec left = children[0]->genRTLIL(width_hint);
                        RTLIL::SigSpec right = children[1]->genRTLIL(width_hint);
                        int width = std::max(left.width, right.width);
-                       if (width > width_hint && width_hint > 0)
-                               width = width_hint;
-                       if (width < width_hint)
+                       if (width_hint > 0)
                                width = width_hint;
                        return binop2rtlil(this, type_name, width, left, right);
                }

diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l
index 783b790b0f895242c49461e7c82bf8dea88090c0..78f1d3674be428e948659a17d2b32fd95f6fa99a 100644 (file)
--- a/frontends/verilog/lexer.l
+++ b/frontends/verilog/lexer.l
@@ -236,8 +236,8 @@ supply1 { return TOK_SUPPLY1; }
 "===" { return OP_EQ; }
 "!==" { return OP_NE; }
 
- /* "~&" { return OP_NAND; } */
- /* "~|" { return OP_NOR;  } */
+"~&" { return OP_NAND; }
+"~|" { return OP_NOR;  }
 "~^" { return OP_XNOR; }
 "^~" { return OP_XNOR; }
 

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index ea39e83d4734fecdec7b1450debf455ed958d74a..68ac26bf9846bc4912aa460294f5e48995031058 100644 (file)
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -113,9 +113,9 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 // operator precedence from low to high
 %left OP_LOR
 %left OP_LAND
-%left '|'
+%left '|' OP_NOR
 %left '^' OP_XNOR
-%left '&'
+%left '&' OP_NAND
 %left OP_EQ OP_NE
 %left '<' OP_LE OP_GE '>'
 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
@@ -982,10 +982,20 @@ basic_expr:
                $$ = new AstNode(AST_REDUCE_AND, $3);
                append_attr($$, $2);
        } |
+       OP_NAND attr basic_expr %prec UNARY_OPS {
+               $$ = new AstNode(AST_REDUCE_AND, $3);
+               append_attr($$, $2);
+               $$ = new AstNode(AST_LOGIC_NOT, $$);
+       } |
        '|' attr basic_expr %prec UNARY_OPS {
                $$ = new AstNode(AST_REDUCE_OR, $3);
                append_attr($$, $2);
        } |
+       OP_NOR attr basic_expr %prec UNARY_OPS {
+               $$ = new AstNode(AST_REDUCE_OR, $3);
+               append_attr($$, $2);
+               $$ = new AstNode(AST_LOGIC_NOT, $$);
+       } |
        '^' attr basic_expr %prec UNARY_OPS {
                $$ = new AstNode(AST_REDUCE_XOR, $3);
                append_attr($$, $2);

diff --git a/kernel/satgen.h b/kernel/satgen.h
index 05afeabf51b18e5c8f28d5cac727a64c14f80fc7..991853c2cca0f0790101a528d881b7f1d12625b2 100644 (file)
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -128,6 +128,7 @@ struct SatGen
                if (cell->type == "$_INV_" || cell->type == "$not") {
                        std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
                        std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
+                       extendSignalWidthUnary(a, y, cell);
                        ez->assume(ez->vec_eq(ez->vec_not(a), y));
                        return true;
                }

diff --git a/techlibs/stdcells.v b/techlibs/stdcells.v
index 41e20214d245598e3ef21eab1023c6977c3d4238..59209f9bc7c28b9305a82f07e087aab454e899da 100644 (file)
--- a/techlibs/stdcells.v
+++ b/techlibs/stdcells.v
@@ -41,17 +41,16 @@ parameter Y_WIDTH = 1;
 input [A_WIDTH-1:0] A;
 output [Y_WIDTH-1:0] Y;
 
+wire [Y_WIDTH-1:0] A_buf;
+\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+
 genvar i;
 generate
        for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
-               if (i < A_WIDTH) begin
-                        \$_INV_ gate (
-                               .A(A[i]),
-                               .Y(Y[i])
-                       );
-               end else begin
-                       assign Y[i] = 0;
-               end
+                \$_INV_ gate (
+                       .A(A_buf[i]),
+                       .Y(Y[i])
+               );
        end
 endgenerate