rs6000: Don't call movsi_from_sf in 32 bit mode.

movsi_from_sf uses rldimi instruction, which will cause the compiler to ICE
in 32 bit mode.  This patch limits the recently added pattern and call to
TARGET_POWERPC64.

2020-07-14  David Edelsohn  <dje.gcc@gmail.com>

gcc/ChangeLog

	* config/rs6000/rs6000.md (rotldi3_insert_sf): Add TARGET_POWERPC64
	condition.
	* config/rs6000/rs6000.c (rs6000_expand_vector_init): Add
	TARGET_POWERPC64 requirement to TARGET_P8_VECTOR case.

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 378f761e3fd04237b35a38d81be2e914e4aec230..dda51d5877a2a366b5937853f48a6995eadbf5c8 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6498,7 +6498,7 @@ rs6000_expand_vector_init (rtx target, rtx vals)
        }
       else
        {
-         if (TARGET_P8_VECTOR)
+         if (TARGET_P8_VECTOR && TARGET_POWERPC64)
            {
              rtx tmp_sf[4];
              rtx tmp_si[4];

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3a339821e515a951b0cd7a1d6e5ea40693b72587..c0d9877c7150dbadb525841a0f0f0199bfe954a4 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4251,7 +4251,7 @@
           [(match_operand:SF 3 "memory_operand")]
           UNSPEC_SI_FROM_SF))))
   (clobber (match_scratch:V4SF 4))]
-  "INTVAL (operands[2]) == <bits>"
+  "TARGET_POWERPC64 && INTVAL (operands[2]) == <bits>"
   "#"
   ""
   [(parallel [(set (match_dup 5)