from migen.fhdl.structure import *
+from migen.fhdl.specials import Instance
from migen.flow.actor import *
from migen.flow.network import *
from migen.flow.transactions import *
self.busy.eq(0)
],
- instances=[asfifo])
+ specials={asfifo})
def sim_fifo_gen():
while True:
from migen.fhdl.structure import *
+from migen.fhdl.specials import Instance
from migen.bus import wishbone
class LM32:
self.ibus.adr.eq(self._i_adr_o[2:]),
self.dbus.adr.eq(self._d_adr_o[2:])
]
- return Fragment(comb=comb, instances=[self._inst])
+ return Fragment(comb, specials={self._inst})
from fractions import Fraction
from migen.fhdl.structure import *
+from migen.fhdl.specials import Instance
from mibuild.crg import CRG
class M1CRG(CRG):
self._inst = Instance("m1crg", *inst_items)
def get_fragment(self):
- return Fragment(instances=[self._inst])
+ return Fragment(specials={self._inst})
from migen.fhdl.structure import *
+from migen.fhdl.specials import Instance
from migen.bank.description import *
from migen.bank.eventmanager import *
from migen.bank import csrgen
rx_pending_0_r.eq(rx_pending_0),
rx_pending_1_r.eq(rx_pending_1)
]
- inst = [
- Instance("minimac3",
+ inst = Instance("minimac3",
Instance.ClockPort("sys_clk"),
Instance.ResetPort("sys_rst"),
Instance.Input("phy_rx_er", self.phy_rx_er),
Instance.Input("phy_col", self.phy_col),
Instance.Input("phy_crs", self.phy_crs))
- ]
- return Fragment(comb, sync, instances=inst) \
+ return Fragment(comb, sync, specials={inst}) \
+ self.events.get_fragment() \
+ self.bank.get_fragment()
from migen.fhdl.structure import *
+from migen.fhdl.specials import Instance
from migen.bus import dfi
class S6DDRPHY:
self._inst = Instance("s6ddrphy", *inst_items)
def get_fragment(self):
- return Fragment(instances=[self._inst])
+ return Fragment(specials={self._inst})